STM32 ADC update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4194 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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87ad1594c3
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@ -236,17 +236,17 @@
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# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
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# define ADC_CR2_JEXTSEL_MASK (15 << ADC_CR2_JEXTSEL_SHIFT)
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# define ADC_CR2_JEXTSEL_T1CC4 (0 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */
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# define ADC_CR2_JEXTSEL_T1TRG0 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */
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# define ADC_CR2_JEXTSEL_T1TRGO (1 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */
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# define ADC_CR2_JEXTSEL_T2CC1 (2 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */
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# define ADC_CR2_JEXTSEL_T2TRG0 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */
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# define ADC_CR2_JEXTSEL_T2TRGO (3 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */
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# define ADC_CR2_JEXTSEL_T3CC2 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */
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# define ADC_CR2_JEXTSEL_T3CC4 (5 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */
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# define ADC_CR2_JEXTSEL_T4CC1 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */
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# define ADC_CR2_JEXTSEL_T4CC2 (7 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */
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# define ADC_CR2_JEXTSEL_T4CC3 (8 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */
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# define ADC_CR2_JEXTSEL_T4TRG0 (9 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
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# define ADC_CR2_JEXTSEL_T4TRGO (9 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */
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# define ADC_CR2_JEXTSEL_T5CC4 (10 << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */
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# define ADC_CR2_JEXTSEL_T5TRG0 (11 << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */
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# define ADC_CR2_JEXTSEL_T5TRGO (11 << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */
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# define ADC_CR2_JEXTSEL_T8CC2 (12 << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */
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# define ADC_CR2_JEXTSEL_T8CC3 (13 << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */
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# define ADC_CR2_JEXTSEL_T8CC4 (14 << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */
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@ -277,7 +277,7 @@
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# define ADC_CR2_EXTSEL_T5CC2 (11 << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */
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# define ADC_CR2_EXTSEL_T5CC3 (12 << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */
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# define ADC_CR2_EXTSEL_T8CC1 (13 << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */
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# define ADC_CR2_EXTSEL_T8TRG0 (14 << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
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# define ADC_CR2_EXTSEL_T8TRGO (14 << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */
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# define ADC_CR2_EXTSEL_EXTI (15 << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line11 */
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# define ACD_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
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@ -292,12 +292,12 @@
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#else
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# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */
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# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
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# define ADC_CR2_JEXTSEL_T1TRG0 (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
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# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
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# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */
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# define ADC_CR2_JEXTSEL_T2TRG0 (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
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# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
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# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
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# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
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# define ADC_CR2_JEXTSEL_T4TRG0 (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
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# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
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# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */
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# define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
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@ -308,7 +308,7 @@
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# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */
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# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */
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# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
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# define ADC_CR2_EXTSEL_T3TRG0 (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
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# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
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# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
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# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */
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# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
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@ -44,6 +44,7 @@
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <unistd.h>
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#include <string.h>
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#include <semaphore.h>
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#include <errno.h>
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@ -62,151 +63,11 @@
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#include "stm32_adc.h"
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#ifdef CONFIG_ADC
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#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Up to 3 ADC interfaces are supported */
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#if STM32_NADC < 3
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# undef CONFIG_STM32_ADC3
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#endif
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#if STM32_NADC < 2
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# undef CONFIG_STM32_ADC2
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#endif
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#if STM32_NADC < 1
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# undef CONFIG_STM32_ADC1
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#endif
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#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
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/* Timer configuration: If a timer trigger is specified, then get information
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* about the timer.
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*/
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#if defined(CONFIG_STM32_TIM1_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1
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# define ADC1_TIMER_BASE STM32_TIM1_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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#elif defined(CONFIG_STM32_TIM2_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2
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# define ADC1_TIMER_BASE STM32_TIM2_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM3_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1
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# define ADC1_TIMER_BASE STM32_TIM3_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM4_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4
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# define ADC1_TIMER_BASE STM32_TIM4_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM5_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1
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# define ADC1_TIMER_BASE STM32_TIM5_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM8_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_EXTSEL_VALUE ??? which ????
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# define ADC1_TIMER_BASE STM32_TIM8_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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#else
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# undef ADC1_HAVE_TIMER
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#endif
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#if defined(ADC1_HAVE_TIMER) && !defined(CONFIG_STM32_ADC1_SAMPLE_FREQUENCY)
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# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined"
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#endif
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#if defined(CONFIG_STM32_TIM1_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1
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# define ADC2_TIMER_BASE STM32_TIM1_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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#elif defined(CONFIG_STM32_TIM2_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2
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# define ADC2_TIMER_BASE STM32_TIM2_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM3_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1
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# define ADC2_TIMER_BASE STM32_TIM3_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM4_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4
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# define ADC2_TIMER_BASE STM32_TIM4_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM5_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1
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# define ADC2_TIMER_BASE STM32_TIM5_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM8_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1
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# define ADC2_TIMER_BASE STM32_TIM8_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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#else
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# undef ADC2_HAVE_TIMER
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#endif
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#if defined(ADC2_HAVE_TIMER) && !defined(CONFIG_STM32_ADC2_SAMPLE_FREQUENCY)
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# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined"
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#endif
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#if defined(CONFIG_STM32_TIM1_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1
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# define ADC3_TIMER_BASE STM32_TIM1_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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#elif defined(CONFIG_STM32_TIM2_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2
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# define ADC3_TIMER_BASE STM32_TIM2_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM3_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1
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# define ADC3_TIMER_BASE STM32_TIM3_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM4_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4
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# define ADC3_TIMER_BASE STM32_TIM4_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM5_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1
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# define ADC3_TIMER_BASE STM32_TIM5_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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#elif defined(CONFIG_STM32_TIM8_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1
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# define ADC3_TIMER_BASE STM32_TIM8_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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#else
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# undef ADC3_HAVE_TIMER
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#endif
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#if defined(ADC3_HAVE_TIMER) && !defined(CONFIG_STM32_ADC3_SAMPLE_FREQUENCY)
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# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined"
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#endif
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#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER)
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# define ADC_HAVE_TIMER 1
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#else
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# undef ADC_HAVE_TIMER
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#endif
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/* ADC interrupts ***********************************************************/
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#ifdef CONFIG_STM32_STM32F10XX
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@ -221,23 +82,6 @@
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# define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE | ADC_CR1_OVRIE)
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#endif
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/* Timer Setup **************************************************************/
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/* Calculate timer divider values based upon ADCn_TIMER_PCLK_FREQUENCY and
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* CONFIG_STM32_ADCn_SAMPLE_FREQUENCY.
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*/
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#ifdef ADC1_HAVE_TIMER
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# warning "Missing Logic"
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#endif
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#ifdef ADC2_HAVE_TIMER
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# warning "Missing Logic"
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#endif
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#ifdef ADC3_HAVE_TIMER
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# warning "Missing Logic"
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#endif
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/* The maximum number of channels that can be sampled */
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#define ADC_MAX_SAMPLES 16
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@ -259,7 +103,7 @@ struct stm32_dev_s
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#ifdef ADC_HAVE_TIMER
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uint32_t tbase; /* Base address of timer used by this ADC block */
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uint32_t extsel; /* EXTSEL value used by this ADC block */
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uint32_t pclck; /* The PCLK frequency that drivers this timer */
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uint32_t presc; /* Timer prescaler value */
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#endif
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uint8_t chanlist[ADC_MAX_SAMPLES];
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@ -334,7 +178,7 @@ static struct stm32_dev_s g_adcpriv1 =
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#ifdef ADC1_HAVE_TIMER
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.tbase = ADC1_TIMER_BASE,
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.extsel = ADC1_EXTSEL_VALUE,
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.pclck = ADC1_TIMER_PCLK_FREQUENCY,
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.presc = ADC1_TIMER_PCLK_FREQUENCY / CONFIG_STM32_ADC1_SAMPLE_FREQUENCY,
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#endif
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};
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@ -362,7 +206,7 @@ static struct stm32_dev_s g_adcpriv2 =
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#ifdef ADC2_HAVE_TIMER
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.tbase = ADC2_TIMER_BASE,
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.extsel = ADC2_EXTSEL_VALUE,
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.pclck = ADC2_TIMER_PCLK_FREQUENCY,
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.presc = ADC2_TIMER_PCLK_FREQUENCY / CONFIG_STM32_ADC2_SAMPLE_FREQUENCY,
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#endif
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};
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@ -390,7 +234,7 @@ static struct stm32_dev_s g_adcpriv3 =
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#ifdef ADC3_HAVE_TIMER
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.tbase = ADC3_TIMER_BASE,
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.extsel = ADC3_EXTSEL_VALUE,
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.pclck = ADC3_TIMER_PCLK_FREQUENCY,
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.presc = ADC3_TIMER_PCLK_FREQUENCY / CONFIG_STM32_ADC3_SAMPLE_FREQUENCY,
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#endif
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};
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@ -458,7 +302,7 @@ static void adc_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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*
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****************************************************************************/
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#ifdef HAVE_DMA
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#ifdef ADC_HAVE_TIMER
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static uint32_t tim_getreg(struct stm32_dev_s *priv, int offset)
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{
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return getreg32(priv->tbase + offset);
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@ -480,6 +324,7 @@ static uint32_t tim_getreg(struct stm32_dev_s *priv, int offset)
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*
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****************************************************************************/
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#ifdef ADC_HAVE_TIMER
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static void tim_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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{
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putreg32(value, priv->tbase + offset);
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@ -494,7 +339,7 @@ static void tim_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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* the pre-calculated timer divider definitions.
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*
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* Input Parameters:
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* chan - A reference to the DAC channel state data
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* priv - A reference to the ADC block status
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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@ -504,16 +349,67 @@ static void tim_putreg(struct stm32_dev_s *priv, int offset, uint32_t value)
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#ifdef ADC_HAVE_TIMER
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static int adc_timinit(FAR struct stm32_dev_s *priv)
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{
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uint32_t regval;
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/* Configure the time base: Timer period, prescaler, clock division,
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* counter mode (up).
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*
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* EXTTRIG: External Trigger Conversion mode for regular channels
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*/
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#warning "Missing Logic"
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/* Selection EXTSEL selection: update */
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#warning "Missing Logic"
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regval = tim_getreg(priv, STM32_ADC_CR2_OFFSET)
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regval |= ADC_CR2_EXTTRIG;
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/* EXTSEL selection: These bits select the external event used to trigger
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* the start of conversion of a regular group. NOTE:
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*
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* - The position with with of the EXTSEL field varies from one STM32 MCU
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* to another.
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* - The width of the EXTSEL field varies from one STM3 MCU to another.
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* - The value in priv->extsel is already shifted into the correct bit position.
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||||
*/
|
||||
|
||||
regval &= ~ADC_CR2_EXTSEL_MASK;
|
||||
regval |= priv->extsel;
|
||||
tim_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
|
||||
|
||||
/* ADC Prescaler (ADCPRE) selection: Set and cleared by software to select
|
||||
* the frequency of the clock to the ADCs.
|
||||
*/
|
||||
|
||||
regval = priv->presc;
|
||||
|
||||
/* We need to decrement the prescaler value by one, but only, the value does
|
||||
* not underflow.
|
||||
*/
|
||||
|
||||
if (regval > 0)
|
||||
{
|
||||
regval--;
|
||||
}
|
||||
|
||||
/* Check for overflow */
|
||||
|
||||
if (regval > 0xffff)
|
||||
{
|
||||
regval = 0xffff;
|
||||
}
|
||||
|
||||
/* Save the timer prescaler value */
|
||||
|
||||
tim_putreg(priv, STM32_BTIM_PSC_OFFSET, regval);
|
||||
|
||||
#if 0 // What is this?
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval |= presc << RCC_CFGR_ADCPRE_SHIFT;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
#endif
|
||||
|
||||
/* Enable the counter */
|
||||
#warning "Missing Logic"
|
||||
|
||||
regval = stm32_tim_getreg(priv, STM32_BTIM_CR1_OFFSET);
|
||||
regval |= ATIM_CR1_CEN;
|
||||
tim_putreg(priv, STM32_BTIM_CR1_OFFSET, val);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -655,10 +551,6 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
|
||||
regval &= ~ADC_CR2_ADON;
|
||||
}
|
||||
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
|
||||
|
||||
/* Enable or disable conversions */
|
||||
|
||||
//adc_startconv(priv, enable);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -704,7 +596,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000);
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F40XX
|
||||
/* Initialize ADC Prescaler*/
|
||||
/* Initialize ADC Prescaler */
|
||||
|
||||
regval = getreg32(STM32_ADC_CCR_OFFSET);
|
||||
|
||||
@ -730,6 +622,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, 0x00b6db6d);
|
||||
adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, 0x00b6db6d);
|
||||
|
||||
#ifdef ADC_HAVE_TIMER
|
||||
adc_timinit(priv);
|
||||
#endif
|
||||
|
||||
/* ADC CR1 Configuration */
|
||||
|
||||
@ -771,26 +667,6 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
regval &= ~ADC_CR2_ALIGN;
|
||||
regval &= ~ADC_CR2_EXTSEL_MASK;
|
||||
|
||||
/* EXTTRIG: External Trigger Conversion mode for regular channels enable*/
|
||||
|
||||
//regval |= ADC_CR2_EXTTRIG;
|
||||
|
||||
/* EXTSEL[2:0]: External event select for regular group
|
||||
* These bits select the external event used to trigger the start
|
||||
* of conversion of a regular group:
|
||||
* 000: Timer 1 CC1 event
|
||||
* 001: Timer 1 CC2 event
|
||||
* 010: Timer 1 CC3 event
|
||||
* 011: Timer 2 CC2 event
|
||||
* 100: Timer 3 TRGO event
|
||||
* 101: Timer 4 CC4 event
|
||||
* 110: EXTI line11/TIM8_TRGO event (TIM8_TRGO is available only in high-density devices)
|
||||
* 111: SWSTART
|
||||
*/
|
||||
|
||||
/* Select trigger when SWSTART is set */
|
||||
//regval |= ADC_CR2_EXTSEL_SWSTART;
|
||||
|
||||
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
|
||||
|
||||
/* Configuration of the channel conversions */
|
||||
@ -825,11 +701,15 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
/* Set the channel index of the first conversion */
|
||||
|
||||
priv->current = 0;
|
||||
|
||||
|
||||
/* Set ADON to wake up the ADC from Power Down state. */
|
||||
|
||||
usleep(10);
|
||||
adc_enable(priv, true);
|
||||
|
||||
/* Set ADON (Again) to start the conversion. */
|
||||
|
||||
adc_enable(priv, true);
|
||||
adc_startconv(priv, true);
|
||||
irqrestore(flags);
|
||||
|
||||
avdbg("SR: %08x CR1: 0x%08x CR2: 0x%08x\n",
|
||||
@ -1005,20 +885,29 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
|
||||
* 3) The third is the converted data for the channel.
|
||||
*/
|
||||
|
||||
avdbg("Calling adc_receive(priv, ch=%d, value=%d)\n",
|
||||
priv->chanlist[priv->current], value);
|
||||
|
||||
adc_receive(dev, priv->chanlist[priv->current], value);
|
||||
|
||||
|
||||
/* Set the channel number of the next channel that will complete conversion */
|
||||
#if 0
|
||||
#error "This logic force to read the following channels but never reads the real converted value"
|
||||
if (++priv->current < priv->nchannels)
|
||||
{
|
||||
adc_enable(priv, true);
|
||||
return OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
priv->current = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (++priv->current >= priv->nchannels)
|
||||
{
|
||||
/* Restart the conversion sequence from the beginning */
|
||||
#warning "Missing logic"
|
||||
|
||||
|
||||
/* Reset the index to the first channel to be converted */
|
||||
|
||||
|
||||
priv->current = 0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -145,6 +145,411 @@
|
||||
#undef CONFIG_STM32_TIM14_ADC2
|
||||
#undef CONFIG_STM32_TIM14_ADC3
|
||||
|
||||
/* Up to 3 ADC interfaces are supported */
|
||||
|
||||
#if STM32_NADC < 3
|
||||
# undef CONFIG_STM32_ADC3
|
||||
#endif
|
||||
|
||||
#if STM32_NADC < 2
|
||||
# undef CONFIG_STM32_ADC2
|
||||
#endif
|
||||
|
||||
#if STM32_NADC < 1
|
||||
# undef CONFIG_STM32_ADC1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3)
|
||||
|
||||
/* Timer configuration: If a timer trigger is specified, then get information
|
||||
* about the timer.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM2_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM3_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM4_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM5_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM5_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM8_ADC1)
|
||||
# define ADC1_HAVE_TIMER 1
|
||||
# define ADC1_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#else
|
||||
# undef ADC1_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#ifdef ADC1_HAVE_TIMER
|
||||
# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY
|
||||
# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined"
|
||||
# endif
|
||||
# ifndef CONFIG_STM32_ADC1_TIMTRIG
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG not defined"
|
||||
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM2_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM3_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM4_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM5_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM5_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM8_ADC2)
|
||||
# define ADC2_HAVE_TIMER 1
|
||||
# define ADC2_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#else
|
||||
# undef ADC2_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#ifdef ADC2_HAVE_TIMER
|
||||
# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY
|
||||
# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined"
|
||||
# endif
|
||||
# ifndef CONFIG_STM32_ADC2_TIMTRIG
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG not defined"
|
||||
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM1_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM2_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM2_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM3_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM3_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM4_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM4_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM5_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM5_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
|
||||
#elif defined(CONFIG_STM32_TIM8_ADC3)
|
||||
# define ADC3_HAVE_TIMER 1
|
||||
# define ADC3_TIMER_BASE STM32_TIM8_BASE
|
||||
# define ADC3_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
|
||||
#else
|
||||
# undef ADC3_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
#ifdef ADC3_HAVE_TIMER
|
||||
# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY
|
||||
# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined"
|
||||
# endif
|
||||
# ifndef CONFIG_STM32_ADC3_TIMTRIG
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG not defined"
|
||||
# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER)
|
||||
# define ADC_HAVE_TIMER 1
|
||||
#else
|
||||
# undef ADC_HAVE_TIMER
|
||||
#endif
|
||||
|
||||
/* NOTE: The following assumes that all possible combinations of timers and
|
||||
* values are support EXTSEL. That is not so and it varies from one STM32 to another.
|
||||
* But this (wrong) assumptions keeps the logic as simple as possible. If un
|
||||
* unsupported combination is used, an error will show up later during compilation
|
||||
* although it may be difficult to track it back to this simplification.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM2_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM3_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM4_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM5_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM8_ADC1)
|
||||
# if CONFIG_STM32_ADC1_TIMTRIG == 0
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 1
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 2
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4
|
||||
# elif CONFIG_STM32_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC1_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC2)
|
||||
# if CONFIG_STM32_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM2_ADC2)
|
||||
# if CONFIG_STM32_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM3_ADC2)
|
||||
# if CONFIG_STM32_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM4_ADC2)
|
||||
# if CONFIG_STM32_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM5_ADC2)
|
||||
# if CONFIG_STM32_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM8_ADC2)
|
||||
# if CONFIG_STM32_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4
|
||||
# elif CONFIG_STM32_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC2_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_ADC3)
|
||||
# if CONFIG_STM32_ADC3_TIMTRIG == 0
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC1
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC2
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC3
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1CC4
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T1TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM2_ADC3)
|
||||
# if CONFIG_STM32_ADC3_TIMTRIG == 0
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC1
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC2
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC3
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2CC4
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T2TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM3_ADC3)
|
||||
# if CONFIG_STM32_ADC3_TIMTRIG == 0
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC1
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC2
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC3
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T3TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM4_ADC3)
|
||||
# if CONFIG_STM32_ADC3_TIMTRIG == 0
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC1
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC2
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC3
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T4TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM5_ADC3)
|
||||
# if CONFIG_STM32_ADC3_TIMTRIG == 0
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC1
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC2
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC3
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5CC4
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T5TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32_TIM8_ADC3)
|
||||
# if CONFIG_STM32_ADC3_TIMTRIG == 0
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC1
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 1
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC2
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 2
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC3
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 3
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8CC4
|
||||
# elif CONFIG_STM32_ADC3_TIMTRIG == 4
|
||||
# define ADC3_EXTSEL_VALUE ADC_CR2_EXTSEL_T8TRGO
|
||||
# else
|
||||
# error "CONFIG_STM32_ADC3_TIMTRIG is out of range"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
@ -183,5 +588,6 @@ EXTERN struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* CONFIG_STM32_ADC || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */
|
||||
|
||||
|
||||
@ -87,43 +87,43 @@
|
||||
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || defined(CONFIG_STM32_TIM1_DAC)
|
||||
# undef CONFIG_STM32_TIM1
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM2_PWM || defined (CONFIG_STM32_TIM2_ADC) || defined(CONFIG_STM32_TIM2_DAC)
|
||||
#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || defined(CONFIG_STM32_TIM2_DAC)
|
||||
# undef CONFIG_STM32_TIM2
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM3_PWM || defined (CONFIG_STM32_TIM3_ADC) || defined(CONFIG_STM32_TIM3_DAC)
|
||||
#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || defined(CONFIG_STM32_TIM3_DAC)
|
||||
# undef CONFIG_STM32_TIM3
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM4_PWM || defined (CONFIG_STM32_TIM4_ADC) || defined(CONFIG_STM32_TIM4_DAC)
|
||||
#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || defined(CONFIG_STM32_TIM4_DAC)
|
||||
# undef CONFIG_STM32_TIM4
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM5_PWM || defined (CONFIG_STM32_TIM5_ADC) || defined(CONFIG_STM32_TIM5_DAC)
|
||||
#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || defined(CONFIG_STM32_TIM5_DAC)
|
||||
# undef CONFIG_STM32_TIM5
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM6_PWM || defined (CONFIG_STM32_TIM6_ADC) || defined(CONFIG_STM32_TIM6_DAC)
|
||||
#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || defined(CONFIG_STM32_TIM6_DAC)
|
||||
# undef CONFIG_STM32_TIM6
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM7_PWM || defined (CONFIG_STM32_TIM7_ADC) || defined(CONFIG_STM32_TIM7_DAC)
|
||||
#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || defined(CONFIG_STM32_TIM7_DAC)
|
||||
# undef CONFIG_STM32_TIM7
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM8_PWM || defined (CONFIG_STM32_TIM8_ADC) || defined(CONFIG_STM32_TIM8_DAC)
|
||||
#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || defined(CONFIG_STM32_TIM8_DAC)
|
||||
# undef CONFIG_STM32_TIM8
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM9_PWM || defined (CONFIG_STM32_TIM9_ADC) || defined(CONFIG_STM32_TIM9_DAC)
|
||||
#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || defined(CONFIG_STM32_TIM9_DAC)
|
||||
# undef CONFIG_STM32_TIM9
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM10_PWM || defined (CONFIG_STM32_TIM10_ADC) || defined(CONFIG_STM32_TIM10_DAC)
|
||||
#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || defined(CONFIG_STM32_TIM10_DAC)
|
||||
# undef CONFIG_STM32_TIM10
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM11_PWM || defined (CONFIG_STM32_TIM11_ADC) || defined(CONFIG_STM32_TIM11_DAC)
|
||||
#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || defined(CONFIG_STM32_TIM11_DAC)
|
||||
# undef CONFIG_STM32_TIM11
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM12_PWM || defined (CONFIG_STM32_TIM12_ADC) || defined(CONFIG_STM32_TIM12_DAC)
|
||||
#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || defined(CONFIG_STM32_TIM12_DAC)
|
||||
# undef CONFIG_STM32_TIM12
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM13_PWM || defined (CONFIG_STM32_TIM13_ADC) || defined(CONFIG_STM32_TIM13_DAC)
|
||||
#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || defined(CONFIG_STM32_TIM13_DAC)
|
||||
# undef CONFIG_STM32_TIM13
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM14_PWM || defined (CONFIG_STM32_TIM14_ADC) || defined(CONFIG_STM32_TIM14_DAC)
|
||||
#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || defined(CONFIG_STM32_TIM14_DAC)
|
||||
# undef CONFIG_STM32_TIM14
|
||||
#endif
|
||||
|
||||
@ -147,19 +147,16 @@ struct stm32_tim_priv_s {
|
||||
uint32_t base; /** TIMn base address */
|
||||
};
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
/** Get register value by offset */
|
||||
static inline uint16_t stm32_tim_getreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset)
|
||||
{
|
||||
return getreg16( ((struct stm32_tim_priv_s *)dev)->base + offset);
|
||||
}
|
||||
|
||||
|
||||
/** Put register value by offset */
|
||||
static inline void stm32_tim_putreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value)
|
||||
{
|
||||
@ -167,14 +164,12 @@ static inline void stm32_tim_putreg(FAR struct stm32_tim_dev_s *dev, uint8_t off
|
||||
putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
|
||||
}
|
||||
|
||||
|
||||
/** Modify register value by offset */
|
||||
static inline void stm32_tim_modifyreg(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits)
|
||||
{
|
||||
modifyreg16( ((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits);
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
|
||||
{
|
||||
uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_EGR_OFFSET);
|
||||
@ -182,7 +177,6 @@ static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
|
||||
stm32_tim_putreg(dev, STM32_BTIM_EGR_OFFSET, val);
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
|
||||
{
|
||||
uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_CR1_OFFSET);
|
||||
@ -191,7 +185,6 @@ static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
|
||||
stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val);
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
|
||||
{
|
||||
uint16_t val = stm32_tim_getreg(dev, STM32_BTIM_CR1_OFFSET);
|
||||
@ -199,7 +192,6 @@ static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
|
||||
stm32_tim_putreg(dev, STM32_BTIM_CR1_OFFSET, val);
|
||||
}
|
||||
|
||||
|
||||
/** Reset timer into system default state, but do not affect output/input pins */
|
||||
static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
|
||||
{
|
||||
@ -207,7 +199,6 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
|
||||
stm32_tim_disable(dev);
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
|
||||
{
|
||||
/** \todo Added support for input capture and bipolar dual outputs for TIM8 */
|
||||
@ -220,7 +211,6 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Basic Functions
|
||||
************************************************************************************/
|
||||
@ -257,14 +247,12 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
|
||||
return prescaler;
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint16_t period)
|
||||
{
|
||||
ASSERT(dev);
|
||||
stm32_tim_putreg(dev, STM32_BTIM_ARR_OFFSET, period);
|
||||
}
|
||||
|
||||
|
||||
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source)
|
||||
{
|
||||
int vectorno;
|
||||
@ -323,28 +311,23 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
|
||||
{
|
||||
ASSERT(dev);
|
||||
stm32_tim_modifyreg(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE);
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
|
||||
{
|
||||
ASSERT(dev);
|
||||
stm32_tim_modifyreg(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
|
||||
}
|
||||
|
||||
|
||||
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
|
||||
{
|
||||
stm32_tim_putreg(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* General Functions
|
||||
************************************************************************************/
|
||||
@ -410,7 +393,6 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode)
|
||||
{
|
||||
uint16_t ccmr_val = 0;
|
||||
@ -542,7 +524,6 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint16_t compare)
|
||||
{
|
||||
ASSERT(dev);
|
||||
@ -557,7 +538,6 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel)
|
||||
{
|
||||
ASSERT(dev);
|
||||
@ -571,7 +551,6 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Advanced Functions
|
||||
************************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user