Fixes for STM32 F3 GPIO, pinmap, DMA, and heap allocation
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5621 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
fd9eac63a9
commit
d9f7cf377f
@ -39,8 +39,8 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* 7 DMA Channels */
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/* These definitions apply to both the STM32 F1 and F3 families */
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/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
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#define DMA1 0
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#define DMA2 1
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@ -55,11 +55,19 @@
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
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#define STM32_DMACHAN_CCR_OFFSET 0x0008
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#define STM32_DMACHAN_CNDTR_OFFSET 0x000c
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#define STM32_DMACHAN_CPAR_OFFSET 0x0010
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#define STM32_DMACHAN_CMAR_OFFSET 0x0014
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#define STM32_DMACHAN_OFFSET(n) (0x0008 + 0x0014*(n))
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#define STM32_DMACHAN1_OFFSET 0x0008
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#define STM32_DMACHAN2_OFFSET 0x001c
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#define STM32_DMACHAN3_OFFSET 0x0030
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#define STM32_DMACHAN4_OFFSET 0x0044
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#define STM32_DMACHAN5_OFFSET 0x0058
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#define STM32_DMACHAN6_OFFSET 0x006c
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#define STM32_DMACHAN7_OFFSET 0x0080
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#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
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#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
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#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
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#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */
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#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
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332
arch/arm/src/stm32/chip/stm32f30xxx_gpio.h
Normal file
332
arch/arm/src/stm32/chip/stm32f30xxx_gpio.h
Normal file
@ -0,0 +1,332 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f30xxx_gpio.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_GPIO_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_GPIO_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Alther the number of GPIO pins varies from 37 to 87, there are always 6 GPIO
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* ports in the STM32 F302/F303 parts.
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*/
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#define STM32_NGPIO_PORTS (6)
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/* Register Offsets *****************************************************************/
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#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
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#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
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#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
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#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
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#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
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#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
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#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
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#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
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#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
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#define STM32_GPIO_ARFH_OFFSET 0x0024 /* GPIO alternate function high register */
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#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
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/* Register Addresses ***************************************************************/
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#define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET)
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#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET)
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#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET)
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#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET)
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#define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
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#define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
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#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
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#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
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#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET)
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#define STM32_GPIOA_ARFH (STM32_GPIOA_BASE+STM32_GPIO_ARFH_OFFSET)
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#define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
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#define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET)
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#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET)
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#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET)
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#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET)
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#define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
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#define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
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#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
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#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
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#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET)
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#define STM32_GPIOB_ARFH (STM32_GPIOB_BASE+STM32_GPIO_ARFH_OFFSET)
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#define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
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#define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET)
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#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET)
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#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET)
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#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET)
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#define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
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#define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
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#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
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#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
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#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET)
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#define STM32_GPIOC_ARFH (STM32_GPIOC_BASE+STM32_GPIO_ARFH_OFFSET)
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#define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
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#define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET)
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#define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET)
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#define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET)
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#define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET)
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#define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
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#define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
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#define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
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#define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
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#define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET)
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#define STM32_GPIOD_ARFH (STM32_GPIOD_BASE+STM32_GPIO_ARFH_OFFSET)
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#define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
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#define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET)
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#define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET)
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#define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET)
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#define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET)
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#define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
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#define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
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#define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
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#define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
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#define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET)
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#define STM32_GPIOE_ARFH (STM32_GPIOE_BASE+STM32_GPIO_ARFH_OFFSET)
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#define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
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#define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET)
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#define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET)
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#define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET)
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#define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET)
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#define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
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#define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
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#define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
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#define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
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#define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET)
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#define STM32_GPIOF_ARFH (STM32_GPIOF_BASE+STM32_GPIO_ARFH_OFFSET)
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#define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* GPIO port mode register */
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#define GPIO_MODER_INPUT (0) /* Input */
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#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
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#define GPIO_MODER_ALT (2) /* Alternate mode */
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#define GPIO_MODER_ANALOG (3) /* Analog mode */
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#define GPIO_MODER_SHIFT(n) ((n) << 1)
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#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
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#define GPIO_MODER0_SHIFT (0)
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#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
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#define GPIO_MODER1_SHIFT (2)
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#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
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#define GPIO_MODER2_SHIFT (4)
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#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
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#define GPIO_MODER3_SHIFT (6)
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#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
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#define GPIO_MODER4_SHIFT (8)
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#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
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#define GPIO_MODER5_SHIFT (10)
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#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
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#define GPIO_MODER6_SHIFT (12)
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#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
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#define GPIO_MODER7_SHIFT (14)
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#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
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#define GPIO_MODER8_SHIFT (16)
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#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
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#define GPIO_MODER9_SHIFT (18)
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#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
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#define GPIO_MODER10_SHIFT (20)
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#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
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#define GPIO_MODER11_SHIFT (22)
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#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
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#define GPIO_MODER12_SHIFT (24)
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#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
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#define GPIO_MODER13_SHIFT (26)
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#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
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#define GPIO_MODER14_SHIFT (28)
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#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
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#define GPIO_MODER15_SHIFT (30)
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#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
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/* GPIO port output type register */
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#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
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#define GPIO_OTYPER_PP(n) (0) /* 0=OuTput push-pull */
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/* GPIO port output speed register */
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#define GPIO_OSPEED_2MHz (0) /* 2 MHz Low speed */
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#define GPIO_OSPEED_25MHz (1) /* 25 MHz Medium speed */
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#define GPIO_OSPEED_50MHz (3) /* 50 MHz High speed */
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#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
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#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
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#define GPIO_OSPEED0_SHIFT (0)
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#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
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#define GPIO_OSPEED1_SHIFT (2)
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#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
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#define GPIO_OSPEED2_SHIFT (4)
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#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
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#define GPIO_OSPEED3_SHIFT (6)
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#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
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#define GPIO_OSPEED4_SHIFT (8)
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#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
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#define GPIO_OSPEED5_SHIFT (10)
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#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
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#define GPIO_OSPEED6_SHIFT (12)
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#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
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#define GPIO_OSPEED7_SHIFT (14)
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#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
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#define GPIO_OSPEED8_SHIFT (16)
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#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
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#define GPIO_OSPEED9_SHIFT (18)
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#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
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#define GPIO_OSPEED10_SHIFT (20)
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#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
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#define GPIO_OSPEED11_SHIFT (22)
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#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
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#define GPIO_OSPEED12_SHIFT (24)
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#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
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#define GPIO_OSPEED13_SHIFT (26)
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#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
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#define GPIO_OSPEED14_SHIFT (28)
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#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
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#define GPIO_OSPEED15_SHIFT (30)
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#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
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/* GPIO port pull-up/pull-down register */
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#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
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#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
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#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
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#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
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#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
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#define GPIO_PUPDR0_SHIFT (0)
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#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
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#define GPIO_PUPDR1_SHIFT (2)
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#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
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#define GPIO_PUPDR2_SHIFT (4)
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#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
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#define GPIO_PUPDR3_SHIFT (6)
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#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
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#define GPIO_PUPDR4_SHIFT (8)
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#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
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#define GPIO_PUPDR5_SHIFT (10)
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#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
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#define GPIO_PUPDR6_SHIFT (12)
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#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
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#define GPIO_PUPDR7_SHIFT (14)
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#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
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#define GPIO_PUPDR8_SHIFT (16)
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#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
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#define GPIO_PUPDR9_SHIFT (18)
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#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
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#define GPIO_PUPDR10_SHIFT (20)
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#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
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#define GPIO_PUPDR11_SHIFT (22)
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#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
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#define GPIO_PUPDR12_SHIFT (24)
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#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
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#define GPIO_PUPDR13_SHIFT (26)
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#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
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#define GPIO_PUPDR14_SHIFT (28)
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#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
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#define GPIO_PUPDR15_SHIFT (30)
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#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
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/* GPIO port input data register */
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|
||||
#define GPIO_IDR(n) (1 << (n))
|
||||
|
||||
/* GPIO port output data register */
|
||||
|
||||
#define GPIO_ODR(n) (1 << (n))
|
||||
|
||||
/* GPIO port bit set/reset register */
|
||||
|
||||
#define GPIO_BSRR_SET(n) (1 << (n))
|
||||
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
|
||||
|
||||
/* GPIO port configuration lock register */
|
||||
|
||||
#define GPIO_LCKR(n) (1 << (n))
|
||||
#define GPIO_LCKK (1 << 16) /* Lock key */
|
||||
|
||||
/* GPIO alternate function low/high register */
|
||||
|
||||
#define GPIO_AFR_SHIFT(n) ((n) << 2)
|
||||
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
|
||||
|
||||
#define GPIO_AFRL0_SHIFT (0)
|
||||
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
|
||||
#define GPIO_AFRL1_SHIFT (4)
|
||||
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
|
||||
#define GPIO_AFRL2_SHIFT (8)
|
||||
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
|
||||
#define GPIO_AFRL3_SHIFT (12)
|
||||
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
|
||||
#define GPIO_AFRL4_SHIFT (16)
|
||||
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
|
||||
#define GPIO_AFRL5_SHIFT (20)
|
||||
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
|
||||
#define GPIO_AFRL6_SHIFT (24)
|
||||
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
|
||||
#define GPIO_AFRL7_SHIFT (28)
|
||||
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
|
||||
|
||||
#define GPIO_AFRH8_SHIFT (0)
|
||||
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
|
||||
#define GPIO_AFRH9_SHIFT (4)
|
||||
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
|
||||
#define GPIO_AFRH10_SHIFT (8)
|
||||
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
|
||||
#define GPIO_AFRH11_SHIFT (12)
|
||||
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
|
||||
#define GPIO_AFRH12_SHIFT (16)
|
||||
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
|
||||
#define GPIO_AFRH13_SHIFT (20)
|
||||
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
|
||||
#define GPIO_AFRH14_SHIFT (24)
|
||||
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
|
||||
#define GPIO_AFRH15_SHIFT (28)
|
||||
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
|
||||
|
||||
/* GPIO port bit reset register */
|
||||
|
||||
#define GPIO_BRR(n) (1 << (n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_GPIO_H */
|
||||
|
||||
@ -152,7 +152,7 @@
|
||||
|
||||
/* MCO */
|
||||
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
|
||||
|
||||
/* SPI */
|
||||
|
||||
@ -447,14 +447,14 @@
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_USART1_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_USART1_TX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_USART1_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_USART1_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_USART1_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_USART1_TX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5)
|
||||
@ -463,14 +463,14 @@
|
||||
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_USART2_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
|
||||
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
|
||||
@ -481,24 +481,24 @@
|
||||
#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_USART3_RTS_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_USART3_RX_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
|
||||
#define GPIO_UART4_RX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_UART4_RX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_UART5_RX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF5|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
/* USB */
|
||||
|
||||
#define GPIO_USB_DM (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF14|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USB_DP (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF14|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USB_DM (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USB_DP (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
|
||||
/* Event Outputs */
|
||||
|
||||
|
||||
@ -118,10 +118,84 @@
|
||||
# undef CONFIG_STM32_CCMEXCLUDE
|
||||
# define CONFIG_STM32_CCMEXCLUDE 1
|
||||
|
||||
/* All members of the STM32F20xxx and STM32F40xxx families have 192Kb in three banks:
|
||||
/* Members of teh STM32F30xxx family has a variable amount of SRAM from 24
|
||||
* to 40Kb plus 8KB if CCM SRAM. No external RAM is supported (the F3 family has no
|
||||
* FSMC).
|
||||
*
|
||||
* As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is enabled, CCM SRAM
|
||||
* should probably be excluded from the heap.
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
|
||||
/* Set the end of system SRAM */
|
||||
|
||||
# define SRAM1_END CONFIG_DRAM_END
|
||||
|
||||
/* Set the range of CCM SRAM as well (although we may not use it) */
|
||||
|
||||
# define SRAM2_START 0x10000000
|
||||
# define SRAM2_END 0x10002000
|
||||
|
||||
/* There is no FSMC */
|
||||
|
||||
# undef CONFIG_STM32_FSMC_SRAM
|
||||
|
||||
/* There are 2 possible SRAM configurations:
|
||||
*
|
||||
* Configuration 1. System SRAM (only)
|
||||
* CONFIG_MM_REGIONS == 1
|
||||
* CONFIG_STM32_CCMEXCLUDE defined
|
||||
* Configuration 2. System SRAM and CCM SRAM
|
||||
* CONFIG_MM_REGIONS == 2
|
||||
* CONFIG_STM32_CCMEXCLUDE NOT defined
|
||||
*/
|
||||
|
||||
# if CONFIG_MM_REGIONS < 2
|
||||
/* Only one memory region. Force Configuration 1 */
|
||||
|
||||
# ifndef CONFIG_STM32_CCMEXCLUDE
|
||||
# warning "CCM SRAM excluded from the heap"
|
||||
# define CONFIG_STM32_CCMEXCLUDE 1
|
||||
# endif
|
||||
|
||||
/* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */
|
||||
|
||||
# elif CONFIG_MM_REGIONS >= 2
|
||||
# if CONFIG_MM_REGIONS > 2
|
||||
# error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)"
|
||||
# undef CONFIG_MM_REGIONS
|
||||
# define CONFIG_MM_REGIONS 2
|
||||
# endif
|
||||
|
||||
/* Two memory regions is okay if CCM SRAM is not disabled. */
|
||||
|
||||
# ifdef CONFIG_STM32_CCMEXCLUDE
|
||||
|
||||
/* Configuration 1: CONFIG_MM_REGIONS should have been 2 */
|
||||
|
||||
# error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)"
|
||||
# undef CONFIG_MM_REGIONS
|
||||
# define CONFIG_MM_REGIONS 1
|
||||
# else
|
||||
|
||||
/* Configuration 2: DMA should be disabled */
|
||||
|
||||
# ifdef CONFIG_ARCH_DMA
|
||||
# warning "CCM SRAM is included in the heap AND DMA is enabled"
|
||||
# endif
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* All members of the STM32F20xxx and STM32F40xxx families have 128Kb in two
|
||||
* banks:
|
||||
*
|
||||
* 1) 112Kb of System SRAM beginning at address 0x2000:0000
|
||||
* 2) 16Kb of System SRAM beginning at address 0x2001:c000
|
||||
*
|
||||
* The STM32F40xxx family has an additional 64Kb of CCM SRAM for a total of
|
||||
* 192KB.
|
||||
*
|
||||
* 3) 64Kb of CCM SRAM beginning at address 0x1000:0000
|
||||
*
|
||||
* As determined by ld.script, g_heapbase lies in the 112Kb memory
|
||||
@ -129,15 +203,14 @@
|
||||
* regions are contiguous and treated as one in this logic that extends to
|
||||
* 0x2002:0000.
|
||||
*
|
||||
* As a complication, it appears that CCM SRAM cannot be used for DMA. So, if
|
||||
* STM32 DMA is enabled, CCM SRAM should probably be excluded from the heap.
|
||||
* As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is
|
||||
* enabled, CCM SRAM should probably be excluded from the heap.
|
||||
*
|
||||
* In addition, external FSMC SRAM may be available.
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
|
||||
/* The STM32 F2 has no CCM SRAM */
|
||||
|
||||
# ifdef CONFIG_STM32_STM32F20XX
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_dma.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -71,7 +71,7 @@
|
||||
* channels.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "stm32f10xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "stm32f20xxx_dma.c"
|
||||
|
||||
@ -47,7 +47,7 @@
|
||||
|
||||
/* Include the correct DMA register definitions for this STM32 family */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f10xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_dma.h"
|
||||
|
||||
@ -54,7 +54,7 @@
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32_syscfg.h"
|
||||
#endif
|
||||
|
||||
@ -401,7 +401,7 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
* Name: stm32_configgpio (for the STM2F20xxx and STM32F40xxx family)
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
int stm32_configgpio(uint32_t cfgset)
|
||||
{
|
||||
uintptr_t base;
|
||||
@ -539,9 +539,15 @@ int stm32_configgpio(uint32_t cfgset)
|
||||
setting = GPIO_OSPEED_50MHz;
|
||||
break;
|
||||
|
||||
#ifndef CONFIG_STM32_STM32F30XX
|
||||
case GPIO_SPEED_100MHz: /* 100 MHz High speed output */
|
||||
setting = GPIO_OSPEED_100MHz;
|
||||
break;
|
||||
#else
|
||||
default:
|
||||
setting = GPIO_OSPEED_50MHz;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -639,7 +645,7 @@ int stm32_unconfiggpio(uint32_t cfgset)
|
||||
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
cfgset |= GPIO_INPUT | GPIO_FLOAT;
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
@ -663,7 +669,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
|
||||
uint32_t base;
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
uint32_t offset;
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
uint32_t bit;
|
||||
#endif
|
||||
unsigned int port;
|
||||
@ -695,7 +701,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
|
||||
|
||||
putreg32((1 << pin), base + offset);
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
if (value)
|
||||
{
|
||||
|
||||
@ -57,6 +57,8 @@
|
||||
# include "chip/stm32f10xxx_gpio.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_gpio.h"
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_gpio.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_gpio.h"
|
||||
#else
|
||||
@ -196,7 +198,7 @@
|
||||
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured
|
||||
* by software in several modes:
|
||||
@ -289,7 +291,9 @@
|
||||
# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
|
||||
# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
|
||||
#ifndef CONFIG_STM32_STM32F30XX
|
||||
# define GPIO_SPEED_100MHz (3 << GPIO_SPEED_SHIFT) /* 100 MHz High speed output */
|
||||
#endif
|
||||
|
||||
/* Output/Alt function type selection:
|
||||
*
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user