Fix HSMCI command and wait logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2582 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
63d25971ca
commit
da2bc4cc04
@ -140,6 +140,9 @@
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#define HSMCI_RESPONSE_ERRORS \
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( HSMCI_INT_CSTOE | HSMCI_INT_RTOE | HSMCI_INT_RENDE | HSMCI_INT_RCRCE | \
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HSMCI_INT_RDIRE | HSMCI_INT_RINDE )
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#define HSMCI_RESPONSE_NOCRC_ERRORS \
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( HSMCI_INT_CSTOE | HSMCI_INT_RTOE | HSMCI_INT_RENDE | HSMCI_INT_RDIRE | \
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HSMCI_INT_RINDE )
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#define HSMCI_RESPONSE_TIMEOUT_ERRORS \
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( HSMCI_INT_CSTOE | HSMCI_INT_RTOE )
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@ -167,19 +170,38 @@
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#define HSMCI_DATA_DMASEND_ERRORS \
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( HSMCI_INT_UNRE | HSMCI_INT_CSTOE | HSMCI_INT_DTOE | HSMCI_INT_DCRCE )
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/* Data transfer status and interrupt mask bits */
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/* Data transfer status and interrupt mask bits.
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*
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* The XFRDONE flag in the HSMCI_SR indicates exactly when the read or
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* write sequence is finished.
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*
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* 0: A transfer is in progress.
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* 1: Command register is ready to operate and the data bus is in the idle state.
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*
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* DMADONE: DMA Transfer done
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*
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* 0: DMA buffer transfer has not completed since the last read of HSMCI_SR register.
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* 1: DMA buffer transfer has completed.
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*/
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#define HSMCI_DMARECV_INTS \
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( HSMCI_DATA_DMARECV_ERRORS | HSMCI_INT_XFRDONE | HSMCI_INT_DMADONE )
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( HSMCI_DATA_DMARECV_ERRORS | HSMCI_INT_XFRDONE /* | HSMCI_INT_DMADONE */ )
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#define HSMCI_DMASEND_INTS \
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( HSMCI_DATA_DMASEND_ERRORS | HSMCI_INT_XFRDONE | HSMCI_INT_DMADONE )
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( HSMCI_DATA_DMASEND_ERRORS | HSMCI_INT_XFRDONE /* | HSMCI_INT_DMADONE */ )
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/* Event waiting interrupt mask bits */
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/* Event waiting interrupt mask bits.
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*
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* CMDRDY (Command Ready):
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*
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* 0: A command is in progress
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* 1: The last command has been sent. The CMDRDY flag is released 8 bits
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* after the end of the card response. Cleared when writing in the HSMCI_CMDR
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*/
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#define HSMCI_CMDRESP_INTS \
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( HSMCI_RESPONSE_ERRORS | HSMCI_INT_CMDRDY )
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#define HSMCI_XFRDONE_INTS \
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( 0 )
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#define HSMCI_CMDRESP_NOCRC_INTS \
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( HSMCI_RESPONSE_NOCRC_ERRORS | HSMCI_INT_CMDRDY )
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/* Register logging support */
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@ -215,6 +237,7 @@ struct sam3u_dev_s
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sem_t waitsem; /* Implements event waiting */
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sdio_eventset_t waitevents; /* Set of events to be waited for */
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uint32_t waitmask; /* Interrupt enables for event waiting */
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uint32_t cmdrmask; /* Interrupt enables for this particular cmd/response */
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volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
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WDOG_ID waitwdog; /* Watchdog that handles event timeouts */
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@ -228,8 +251,6 @@ struct sam3u_dev_s
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/* Interrupt mode data transfer support */
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uint32_t *buffer; /* Address of current R/W buffer */
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size_t remaining; /* Number of bytes remaining in the transfer */
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uint32_t xfrmask; /* Interrupt enables for data transfer */
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/* DMA data transfer support */
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@ -302,6 +323,7 @@ static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result);
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static void sam3u_eventtimeout(int argc, uint32_t arg);
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static void sam3u_endwait(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent);
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static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupevent);
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static void sam3u_notransfer(struct sam3u_dev_s *priv);
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/* Interrupt Handling *******************************************************/
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@ -325,12 +347,10 @@ static void sam3u_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
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static int sam3u_cancel(FAR struct sdio_dev_s *dev);
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static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd);
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static int sam3u_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
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static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
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uint32_t *rshort);
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static int sam3u_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
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uint32_t rlong[4]);
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static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
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uint32_t *rshort);
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static int sam3u_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
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uint32_t *rnotimpl);
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@ -377,12 +397,12 @@ struct sam3u_dev_s g_sdiodev =
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.sendsetup = sam3u_dmasendsetup,
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.cancel = sam3u_cancel,
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.waitresponse = sam3u_waitresponse,
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.recvR1 = sam3u_recvshortcrc,
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.recvR1 = sam3u_recvshort,
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.recvR2 = sam3u_recvlong,
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.recvR3 = sam3u_recvshort,
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.recvR4 = sam3u_recvnotimpl,
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.recvR5 = sam3u_recvnotimpl,
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.recvR6 = sam3u_recvshortcrc,
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.recvR6 = sam3u_recvshort,
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.recvR7 = sam3u_recvshort,
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.waitenable = sam3u_waitenable,
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.eventwait = sam3u_eventwait,
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@ -728,15 +748,8 @@ static void sam3u_dumpsamples(struct sam3u_dev_s *priv)
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static void sam3u_dmacallback(DMA_HANDLE handle, void *arg, int result)
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{
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/* FAR struct sam3u_spidev_s *priv = (FAR struct sam3u_spidev_s *)arg; */
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/* We don't really do anything at the completion of DMA. The termination
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* of the transfer is driven by the HSMCI interrupts.
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*
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* In fact, we won't normally get the DMA callback at all! The HSMCI
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* appears to handle the End-Of-Transfer interrupt first and it will can
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* sam3u_dmastop() which will disable and clear the interrupt that performs
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* this callback.
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*/
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sam3u_sample((struct sam3u_dev_s*)arg, SAMPLENDX_DMA_CALLBACK);
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@ -779,7 +792,7 @@ static void sam3u_eventtimeout(int argc, uint32_t arg)
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/* Yes.. wake up any waiting threads */
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sam3u_endwait(priv, SDIOWAIT_TIMEOUT);
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flldbg("Timeout: remaining: %d\n", priv->remaining);
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flldbg("Timeout\n");
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}
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}
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@ -842,6 +855,10 @@ static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupeven
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sam3u_disablexfrints(priv);
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/* No data transfer */
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sam3u_notransfer(priv);
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/* DMA debug instrumentation */
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sam3u_sample(priv, SAMPLENDX_END_TRANSFER);
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@ -853,10 +870,6 @@ static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupeven
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sam3u_dmastop(priv->dma);
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/* Mark the transfer finished */
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priv->remaining = 0;
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/* Is a thread wait for these data transfer complete events? */
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if ((priv->waitevents & wkupevent) != 0)
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@ -867,6 +880,28 @@ static void sam3u_endtransfer(struct sam3u_dev_s *priv, sdio_eventset_t wkupeven
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}
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}
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/****************************************************************************
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* Name: sam3u_notransfer
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*
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* Description:
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* Setup for no transfer. This is the default setup that is overriddden
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* by sam3u_dmarecvsetup or sam3u_dmasendsetup
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*
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* Input Parameters:
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* priv - An instance of the HSMCI device interface
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void sam3u_notransfer(struct sam3u_dev_s *priv)
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{
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uint32_t regval = getreg32(SAM3U_HSMCI_MR);
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regval &= ~(HSMCI_MR_RDPROOF | HSMCI_MR_WRPROOF | HSMCI_MR_BLKLEN_MASK);
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putreg32(regval, SAM3U_HSMCI_MR);
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}
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/****************************************************************************
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* Interrrupt Handling
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****************************************************************************/
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@ -945,7 +980,7 @@ static int sam3u_interrupt(int irq, void *context)
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/* Is this a Command-Response sequence completion event? */
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if ((pending & HSMCI_CMDRESP_INTS) != 0)
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if ((pending & priv->cmdrmask) != 0)
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{
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/* Yes.. Did the Command-Response sequence end with an error? */
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@ -954,7 +989,7 @@ static int sam3u_interrupt(int irq, void *context)
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/* Yes.. Was the error some kind of timeout? */
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fllvdbg("ERROR:events: %08x SR: %08x\n",
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HSMCI_CMDRESP_INTS, enabled);
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priv->cmdrmask, enabled);
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if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
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{
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@ -1055,6 +1090,10 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
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putreg32(HSMCI_CFG_FIFOMODE, SAM3U_HSMCI_CFG);
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/* No data transfer */
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sam3u_notransfer(priv);
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/* Disable the MCI peripheral clock */
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putreg32((1 << SAM3U_PID_HSMCI), SAM3U_PMC_PCDR);
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@ -1068,8 +1107,6 @@ static void sam3u_reset(FAR struct sdio_dev_s *dev)
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/* Interrupt mode data transfer support */
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priv->buffer = 0; /* Address of current R/W buffer */
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priv->remaining = 0; /* Number of bytes remaining in the transfer */
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priv->xfrmask = 0; /* Interrupt enables for data transfer */
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/* DMA data transfer support */
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@ -1265,51 +1302,114 @@ static int sam3u_attach(FAR struct sdio_dev_s *dev)
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static void sam3u_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
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{
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struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
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uint32_t regval;
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uint32_t cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
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uint32_t cmdidx;
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/* Set the HSMCI Argument value */
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putreg32(arg, SAM3U_HSMCI_ARGR);
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/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */
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/* Construct the command valid, starting with the command index */
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regval = getreg32(SAM3U_HSMCI_CMDR);
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regval &= ~(HSMCI_CMDR_CMDINDEX_MASK|HSMCI_CMDR_WAITRESP_MASK|
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HSMCI_CMDR_WAITINT|HSMCI_CMDR_WAITPEND|HSMCI_CMDR_CPSMEN);
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cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
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regval = cmdidx << HSMCI_CMDR_CMDNB_SHIFT;
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/* Set WAITRESP bits */
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/* 'OR' in response related bits */
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switch (cmd & MMCSD_RESPONSE_MASK)
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{
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/* No response */
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case MMCSD_NO_RESPONSE:
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regval |= HSMCI_CMDR_NORESPONSE;
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priv->cmdrmask = HSMCI_CMDRESP_INTS;
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regval |= HSMCI_CMDR_RSPTYP_NONE;
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break;
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/* 48-bit response with CRC */
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case MMCSD_R1_RESPONSE:
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case MMCSD_R1B_RESPONSE:
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case MMCSD_R3_RESPONSE:
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case MMCSD_R4_RESPONSE:
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case MMCSD_R5_RESPONSE:
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case MMCSD_R6_RESPONSE:
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case MMCSD_R7_RESPONSE:
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regval |= HSMCI_CMDR_SHORTRESPONSE;
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priv->cmdrmask = HSMCI_CMDRESP_INTS;
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regval |= HSMCI_CMDR_RSPTYP_48BIT;
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break;
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case MMCSD_R1B_RESPONSE:
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priv->cmdrmask = HSMCI_CMDRESP_INTS;
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regval |= HSMCI_CMDR_RSPTYP_R1B;
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break;
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/* 48-bit response without CRC */
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case MMCSD_R3_RESPONSE:
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case MMCSD_R7_RESPONSE:
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priv->cmdrmask = HSMCI_CMDRESP_NOCRC_INTS;
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regval |= HSMCI_CMDR_RSPTYP_48BIT;
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break;
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/* 136-bit response with CRC */
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case MMCSD_R2_RESPONSE:
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regval |= HSMCI_CMDR_LONGRESPONSE;
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priv->cmdrmask = HSMCI_CMDRESP_INTS;
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regval |= HSMCI_CMDR_RSPTYP_136BIT;
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break;
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}
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/* Set CPSMEN and the command index */
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/* 'OR' in data transer related bits */
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switch (cmd & MMCSD_DATAXFR_MASK)
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{
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#if 0 /* No MMC support */
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case MMCSD_RDSTREAM: /* MMC Read stream */
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regval |= (HSMCI_CMDR_TRCMD_START | HSMCI_CMDR_TRTYP_STREAM | HSMCI_CMDR_TRDIR_READ);
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break;
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case MMCSD_WRSTREAM: /* MMC Write stream */
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regval |= (HSMCI_CMDR_TRCMD_START | HSMCI_CMDR_TRTYP_STREAM | HSMCI_CMDR_TRDIR_WRITE);
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break;
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#endif
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case MMCSD_RDDATAXFR: /* Read block transfer */
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regval |= (HSMCI_CMDR_TRCMD_START | HSMCI_CMDR_TRDIR_READ);
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regval |= (cmd & MMCSD_MULTIBLOCK) ? HSMCI_CMDR_TRTYP_MULTI : HSMCI_CMDR_TRTYP_SINGLE;
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break;
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case MMCSD_WRDATAXFR: /* Write block transfer */
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regval |= (HSMCI_CMDR_TRCMD_START | HSMCI_CMDR_TRDIR_WRITE);
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regval |= (cmd & MMCSD_MULTIBLOCK) ? HSMCI_CMDR_TRTYP_MULTI : HSMCI_CMDR_TRTYP_SINGLE;
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break;
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case MMCSD_NODATAXFR:
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default:
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if ((cmd & MMCSD_STOPXFR) != 0)
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{
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regval |= HSMCI_CMDR_TRCMD_STOP;
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}
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break;
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}
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/* 'OR' in Open Drain option */
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#if 0 /* No MMC support */
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if ((cmd & MMCSD_OPENDRAN) != 0)
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{
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regval |= HSMCI_CMDR_OPDCMD;
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}
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#endif
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/* Special case a couple of commands */
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if (cmdidx > MMC_CMDIDX3 && cmdidx != MMCSD_CMDIDX15 && cmd != MMCSD_CMDIDX27)
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{
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regval |= HSMCI_CMDR_MAXLAT; /* Max Latency for Command to Response */
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}
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/* Write the fully decorated command to CMDR */
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cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
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regval |= cmdidx | HSMCI_CMDR_CPSMEN;
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fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
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/* Write the SDIO CMD */
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putreg32(regval, SAM3U_HSMCI_CMDR);
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}
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@ -1339,6 +1439,10 @@ static int sam3u_cancel(FAR struct sdio_dev_s *dev)
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sam3u_disablexfrints(priv);
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sam3u_disablewaitints(priv, 0);
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/* No data transfer */
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sam3u_notransfer(priv);
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/* Clearing (most) pending interrupt status by reading the status register */
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(void)getreg32(SAM3U_HSMCI_SR);
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@ -1353,10 +1457,6 @@ static int sam3u_cancel(FAR struct sdio_dev_s *dev)
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*/
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sam3u_dmastop(priv->dma);
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/* Mark no transfer in progress */
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priv->remaining = 0;
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return OK;
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}
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@ -1377,6 +1477,7 @@ static int sam3u_cancel(FAR struct sdio_dev_s *dev)
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static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
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{
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struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
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uint32_t sr;
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int32_t timeout;
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@ -1410,7 +1511,7 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
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/* Did a Command-Response sequence termination evernt occur? */
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sr = getreg32(SAM3U_HSMCI_SR);
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if ((sr & HSMCI_CMDRESP_INTS) != 0)
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if ((sr & priv->cmdrmask) != 0)
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{
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/* Yes.. Did the Command-Response sequence end with an error? */
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@ -1419,18 +1520,20 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
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/* Yes.. Was the error some kind of timeout? */
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fdbg("ERROR: cmd: %08x events: %08x SR: %08x\n",
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cmd, HSMCI_CMDRESP_INTS, sr);
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cmd, priv->cmdrmask, sr);
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if ((sr & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0)
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{
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/* Yes.. return a timeout error */
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priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_TIMEOUT;
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return -ETIMEDOUT;
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}
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else
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{
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/* No.. return some generic I/O error */
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||||
|
||||
priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE|SDIOWAIT_ERROR;
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
@ -1438,14 +1541,16 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
|
||||
{
|
||||
/* The Command-Response sequence ended with no error */
|
||||
|
||||
priv->wkupevent = SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE;
|
||||
return OK;
|
||||
}
|
||||
}
|
||||
else if (--timeout <= 0)
|
||||
{
|
||||
fdbg("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n",
|
||||
cmd, HSMCI_CMDRESP_INTS, sr);
|
||||
cmd, priv->cmdrmask, sr);
|
||||
|
||||
priv->wkupevent = SDIOWAIT_TIMEOUT;
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
@ -1473,11 +1578,14 @@ static int sam3u_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int sam3u_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
|
||||
static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
|
||||
{
|
||||
struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
|
||||
int ret = OK;
|
||||
|
||||
/* R1 Command response (48-bit)
|
||||
/* These responses could have CRC errors:
|
||||
*
|
||||
* R1 Command response (48-bit)
|
||||
* 47 0 Start bit
|
||||
* 46 0 Transmission bit (0=from card)
|
||||
* 45:40 bit5 - bit0 Command index (0-63)
|
||||
@ -1497,9 +1605,19 @@ static int sam3u_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
|
||||
* [15:0] Card status bits {23,22,19,12:0}
|
||||
* 7:1 bit6 - bit0 CRC7
|
||||
* 0 1 End bit
|
||||
*
|
||||
* But there is no parity on the R3 response and parity errors should
|
||||
* be ignored.
|
||||
*
|
||||
* R3 OCR (48-bit)
|
||||
* 47 0 Start bit
|
||||
* 46 0 Transmission bit (0=from card)
|
||||
* 45:40 bit5 - bit0 Reserved
|
||||
* 39:8 bit31 - bit0 32-bit OCR register
|
||||
* 7:1 bit6 - bit0 Reserved
|
||||
* 0 1 End bit
|
||||
*/
|
||||
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
if (!rshort)
|
||||
{
|
||||
@ -1511,21 +1629,44 @@ static int sam3u_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
|
||||
|
||||
else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE &&
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE &&
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
|
||||
{
|
||||
fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
/* Check for timeout errors */
|
||||
|
||||
if ((priv->wkupevent & SDIOWAIT_TIMEOUT) != 0)
|
||||
{
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
/* Check for other errors */
|
||||
|
||||
else if ((priv->wkupevent & SDIOWAIT_ERROR) != 0)
|
||||
{
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
/* Return the R1/R6 response */
|
||||
|
||||
*rshort = getreg32(SAM3U_HSMCI_RSPR0);
|
||||
else if (rshort)
|
||||
{
|
||||
*rshort = getreg32(SAM3U_HSMCI_RSPR0);
|
||||
}
|
||||
|
||||
priv->wkupevent = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sam3u_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4])
|
||||
{
|
||||
struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
|
||||
int ret = OK;
|
||||
|
||||
/* R2 CID, CSD register (136-bit)
|
||||
@ -1545,50 +1686,34 @@ static int sam3u_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
|
||||
fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
/* Check for timeout errors */
|
||||
|
||||
if ((priv->wkupevent & SDIOWAIT_TIMEOUT) != 0)
|
||||
{
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
/* Check for other errors */
|
||||
|
||||
else if ((priv->wkupevent & SDIOWAIT_ERROR) != 0)
|
||||
{
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
/* Return the long response */
|
||||
|
||||
if (rlong)
|
||||
else if (rlong)
|
||||
{
|
||||
rlong[0] = getreg32(SAM3U_HSMCI_RSPR0);
|
||||
rlong[1] = getreg32(SAM3U_HSMCI_RSPR1);
|
||||
rlong[2] = getreg32(SAM3U_HSMCI_RSPR2);
|
||||
rlong[3] = getreg32(SAM3U_HSMCI_RSPR3);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
|
||||
{
|
||||
int ret = OK;
|
||||
|
||||
/* R3 OCR (48-bit)
|
||||
* 47 0 Start bit
|
||||
* 46 0 Transmission bit (0=from card)
|
||||
* 45:40 bit5 - bit0 Reserved
|
||||
* 39:8 bit31 - bit0 32-bit OCR register
|
||||
* 7:1 bit6 - bit0 Reserved
|
||||
* 0 1 End bit
|
||||
*/
|
||||
|
||||
/* Check that this is the correct response to this command */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
|
||||
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
|
||||
{
|
||||
fdbg("ERROR: Wrong response CMD=%08x\n", cmd);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Return the short response */
|
||||
|
||||
if (rshort)
|
||||
{
|
||||
*rshort = getreg32(SAM3U_HSMCI_RSPR0);
|
||||
}
|
||||
priv->wkupevent = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1596,6 +1721,8 @@ static int sam3u_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
|
||||
|
||||
static int sam3u_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl)
|
||||
{
|
||||
struct sam3u_dev_s *priv = (struct sam3u_dev_s*)dev;
|
||||
priv->wkupevent = 0;
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
@ -1642,12 +1769,7 @@ static void sam3u_waitenable(FAR struct sdio_dev_s *dev,
|
||||
waitmask = 0;
|
||||
if ((eventset & (SDIOWAIT_CMDDONE|SDIOWAIT_RESPONSEDONE)) != 0)
|
||||
{
|
||||
waitmask |= HSMCI_CMDRESP_INTS;
|
||||
}
|
||||
|
||||
if ((eventset & SDIOWAIT_TRANSFERDONE) != 0)
|
||||
{
|
||||
waitmask |= HSMCI_XFRDONE_INTS;
|
||||
waitmask |= priv->cmdrmask;
|
||||
}
|
||||
|
||||
/* Enable event-related interrupts */
|
||||
@ -1734,6 +1856,8 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
|
||||
|
||||
/* Check if the event has occurred. When the event has occurred, then
|
||||
* evenset will be set to 0 and wkupevent will be set to a nonzero value.
|
||||
* When wkupevent becomes non-zero, further interrupts will have already
|
||||
* been disabled.
|
||||
*/
|
||||
|
||||
if (wkupevent != 0)
|
||||
@ -1744,9 +1868,6 @@ static sdio_eventset_t sam3u_eventwait(FAR struct sdio_dev_s *dev,
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable event-related interrupts */
|
||||
|
||||
sam3u_disablewaitints(priv, 0);
|
||||
sam3u_dumpsamples(priv);
|
||||
return wkupevent;
|
||||
}
|
||||
@ -1883,11 +2004,6 @@ static int sam3u_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
sam3u_sampleinit();
|
||||
sam3u_sample(priv, SAMPLENDX_BEFORE_SETUP);
|
||||
|
||||
/* Save the destination buffer information for use by the interrupt handler */
|
||||
|
||||
priv->buffer = (uint32_t*)buffer;
|
||||
priv->remaining = buflen;
|
||||
|
||||
/* Then set up the HSMCI data path */
|
||||
|
||||
//TO BE PROVIDED
|
||||
@ -1946,11 +2062,6 @@ static int sam3u_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
sam3u_sampleinit();
|
||||
sam3u_sample(priv, SAMPLENDX_BEFORE_SETUP);
|
||||
|
||||
/* Save the source buffer information for use by the interrupt handler */
|
||||
|
||||
priv->buffer = (uint32_t*)buffer;
|
||||
priv->remaining = buflen;
|
||||
|
||||
/* Then set up the HSMCI data path */
|
||||
|
||||
//TO BE PROVIDED
|
||||
|
||||
@ -185,6 +185,8 @@
|
||||
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
|
||||
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
|
||||
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
|
||||
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
|
||||
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
|
||||
#define HSMCI_CMDR_TRTYP_SHIFT (19) /* Bits 19-21: Transfer Type */
|
||||
#define HSMCI_CMDR_TRTYP_MASK (7 << HSMCI_CMDR_TRTYP_SHIFT)
|
||||
# define HSMCI_CMDR_TRTYP_SINGLE (0 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC/SDCard Single Block */
|
||||
|
||||
@ -634,6 +634,61 @@ EXTERN void sam3u_dmadump(DMA_HANDLE handle, const struct sam3u_dmaregs_s *regs,
|
||||
# define sam3u_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct sdio_dev_s; /* See include/nuttx/sdio.h */
|
||||
EXTERN FAR struct sdio_dev_s *sdio_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- posssible from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* cardinslot - true is a card has been detected in the slot; false if a
|
||||
* card has been removed from the slot. Only transitions
|
||||
* (inserted->removed or removed->inserted should be reported)
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
|
||||
@ -1496,7 +1496,7 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
|
||||
static void stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
|
||||
uint32_t cmdidx;
|
||||
|
||||
/* Set the SDIO Argument value */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user