Updated F7 I2C to support 4 devices and proper timing and configurations
This commit is contained in:
David Sidrane
parent
8289e3eb7c
commit
da51b4ecc0
@ -1163,6 +1163,11 @@ config STM32F7_I2C3
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default n
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select STM32F7_I2C
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config STM32F7_I2C4
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bool "I2C4"
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default n
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select STM32F7_I2C
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config STM32F7_LPTIM1
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bool "Low-power timer 1"
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default n
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@ -1666,6 +1671,46 @@ config STM32F7_SPI_DMA
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endmenu # "SPI Configuration"
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menu "I2C Configuration"
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depends on STM32F7_I2C
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config STM32F7_I2C_DYNTIMEO
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bool "Use dynamic timeouts"
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default n
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depends on STM32F7_I2C
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config STM32F7_I2C_DYNTIMEO_USECPERBYTE
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int "Timeout Microseconds per Byte"
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default 500
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depends on STM32F7_I2C_DYNTIMEO
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config STM32F7_I2C_DYNTIMEO_STARTSTOP
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int "Timeout for Start/Stop (Milliseconds)"
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default 1000
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depends on STM32F7_I2C_DYNTIMEO
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config STM32F7_I2CTIMEOSEC
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int "Timeout seconds"
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default 0
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depends on STM32F7_I2C
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config STM32F7_I2CTIMEOMS
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int "Timeout Milliseconds"
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default 500
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depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO
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config STM32F7_I2CTIMEOTICKS
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int "Timeout for Done and Stop (ticks)"
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default 500
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depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO
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config STM32F7_I2C_DUTY16_9
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bool "Frequency with Tlow/Thigh = 16/9 "
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default n
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depends on STM32F7_I2C
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endmenu # "I2C Configuration"
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config STM32F7_CUSTOM_CLOCKCONFIG
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bool "Custom clock configuration"
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default n
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@ -134,7 +134,6 @@
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#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
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#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
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#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
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#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
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#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
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#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
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#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
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@ -195,15 +194,15 @@
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
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#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
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#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT)
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# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
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#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
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#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
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#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
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# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
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#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
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#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
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#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT)
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# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
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/* Timeout register */
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@ -52,17 +52,22 @@
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* STM32 F7 I2C Driver
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*
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* Supports:
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* - Master operation at up to 400Khz (Fast Mode)
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* - Master operation:
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* Standard-mode (up to 100 kHz)
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* Fast-mode (up to 400 kHz)
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* Fast-mode Plus (up to 1 MHz)
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* fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC
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* being set to HSI and the calulations are based on STM32_HSI_FREQUENCY
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* of 16mHz
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*
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* - Multiple instances (shared bus)
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* - Interrupt based operation
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* - RELOAD support
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*
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* Unsupported, possible future work:
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* - More effective error reporting to higher layers
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* - Fast mode plus (1Mhz)
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* - Slave operation
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* - Peripheral clock source selection (SYSCLK vs HSI)
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* - Support of SYSCLK frequencies other than 8Mhz
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* - Support of fI2CCLK frequencies other than 16Mhz
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* - Polled operation (code present but untested)
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* - SMBus support
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* - Multi-master support
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@ -70,8 +75,7 @@
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*
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* Test Environment:
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*
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* - STM32F303VC on ST F3 Discovery Board (ST Part STM32F3DISCOVERY)
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* 256K Flash, 40K SRAM available for all operations, 8K SRAM CCM
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* - STM32F7676ZI on ST Nucleo-144 Board (ST Part STM32F429ZIT6)
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*
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* Operational Status:
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*
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@ -83,18 +87,18 @@
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* payloads has not been tested as the author lacked access to a real
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* device supporting these types of transfers.
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*
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* Performance Benchmarks:
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* Performance Benchmarks: TBD
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*
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* Time to transfer two messages, each a byte in length, in addition to the
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* START condition, in interrupt mode:
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*
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* DEBUG enabled (development): 80ms
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* DEBUG enabled (development): TBDms
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* Excessive delay here is caused by printing to the console and
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* is of no concern.
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*
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* DEBUG disabled (production): 120us
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* Between Messages: 38us
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* Between Bytes: 7us
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* DEBUG disabled (production): TBSus
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* Between Messages: TBDus
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* Between Bytes: TBDus
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*
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* Implementation:
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*
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@ -153,48 +157,55 @@
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*
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* To use this driver, enable the following configuration variable:
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*
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* CONFIG_STM32F7_STM32F30XX
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* One of:
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*
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* CONFIG_STM32F7_STM32F74XX
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* CONFIG_STM32F7_STM32F75XX
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* CONFIG_STM32F7_STM32F76XX
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* CONFIG_STM32F7_STM32F77XX
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*
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*
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* and one or more interfaces:
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*
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* CONFIG_STM32F7_I2C1
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* CONFIG_STM32F7_I2C2
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* CONFIG_STM32F7_I2C3
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* CONFIG_STM32F7_I2C4
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*
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* To configure the ISR timeout using fixed values (STM32_I2C_DYNTIMEO=n):
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* To configure the ISR timeout using fixed values (CONFIG_STM32F7_I2C_DYNTIMEO=n):
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*
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* CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds)
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* CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds)
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* CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds)
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* CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks)
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*
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* To configure the ISR timeout using dynamic values (STM32_I2C_DYNTIMEO=y):
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* To configure the ISR timeout using dynamic values (CONFIG_STM32F7_I2C_DYNTIMEO=y):
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*
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* STM32_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte)
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* STM32_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds)
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* CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte)
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* CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds)
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*
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* Debugging output enabled with:
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*
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* CONFIG_DEBUG_I2C_INFO
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* CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO}
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*
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* ISR Debugging output may be enabled with:
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*
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* CONFIG_DEBUG_VERBOSE
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* CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO
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*
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* ------------------------------------------------------------------------------
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*
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* References:
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*
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* RM0316:
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* ST STM32F303xB/C/D/E, etc. Reference Manual
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* Document ID: DM00043574, Revision 6, August 2015.
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* ST STM32F76xxx and STM32F77xxx Reference Manual
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* Document ID: DocID028270 Revision 2, April 2016.
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*
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* DATASHEET:
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* ST STM32F303xB/STM32F303xC Datasheet
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* Document ID: DM00058181, Revision 12, December 2015.
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* ST STM32F777xx/STM32F778Ax/STM32F779x Datasheet
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* Document ID: DocID028294, Revision 3, May 2016.
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*
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* 303ZYERRATA:
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* STM32F303xB/C Rev Z and Y device limitations
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* Document ID: DM00063985, Revision 7, September 2015.
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* ERRATA:
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* STM32F76xxx/STM32F77xxx Errata sheet Rev A device limitations
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* Document ID: DocID028806, Revision 2, April 2016.
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*
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* I2CSPEC:
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* I2C Bus Specification and User Manual
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@ -235,14 +246,40 @@
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/* At least one I2C peripheral must be enabled */
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#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || defined(CONFIG_STM32F7_I2C3)
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/* This implementation is for the STM32 F1, F2, and F4 only */
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#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \
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defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4)
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#undef INVALID_CLOCK_SOURCE
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#ifdef CONFIG_STM32F7_I2C1
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# if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI
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# warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI"
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# define INVALID_CLOCK_SOURCE
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# endif
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#endif
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#ifdef CONFIG_STM32F7_I2C1
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# if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI
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# warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI"
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# define INVALID_CLOCK_SOURCE
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# endif
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#endif
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#ifdef CONFIG_STM32F7_I2C3
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# if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI
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# warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI"
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# define INVALID_CLOCK_SOURCE
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# endif
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#endif
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#ifdef CONFIG_STM32F7_I2C4
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# if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI
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# warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI"
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# define INVALID_CLOCK_SOURCE
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# endif
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#endif
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/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead,
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* CPU-intensive polling will be used.
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*/
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@ -252,6 +289,7 @@
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#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS)
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# define CONFIG_STM32F7_I2CTIMEOSEC 0
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# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */
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# warning "Using Defualt 500 Ms Timeout"
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#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC)
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# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */
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#elif !defined(CONFIG_STM32F7_I2CTIMEOMS)
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@ -276,12 +314,8 @@
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#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
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/* Register setting unique to the STM32F30xx */
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#define I2C_CR1_TXRX \
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(I2C_CR1_RXIE | I2C_CR1_TXIE)
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#define I2C_CR1_ALLINTS \
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(I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
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#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE)
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#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
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/* I2C event tracing
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*
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@ -451,15 +485,18 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
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static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
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static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv);
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#ifndef CONFIG_I2C_POLLED
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#ifdef CONFIG_STM32F7_I2C1
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# ifdef CONFIG_STM32F7_I2C1
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static int stm32_i2c1_isr(int irq, void *context);
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#endif
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#ifdef CONFIG_STM32F7_I2C2
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# endif
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# ifdef CONFIG_STM32F7_I2C2
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static int stm32_i2c2_isr(int irq, void *context);
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#endif
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#ifdef CONFIG_STM32F7_I2C3
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# endif
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# ifdef CONFIG_STM32F7_I2C3
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static int stm32_i2c3_isr(int irq, void *context);
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#endif
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# endif
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# ifdef CONFIG_STM32F7_I2C4
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static int stm32_i2c4_isr(int irq, void *context);
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# endif
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#endif
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static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
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static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
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@ -566,6 +603,36 @@ struct stm32_i2c_priv_s stm32_i2c3_priv =
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};
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#endif
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#ifdef CONFIG_STM32F7_I2C4
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static const struct stm32_i2c_config_s stm32_i2c4_config =
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{
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.base = STM32_I2C4_BASE,
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.clk_bit = RCC_APB1ENR_I2C4EN,
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.reset_bit = RCC_APB1RSTR_I2C4RST,
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.scl_pin = GPIO_I2C4_SCL,
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.sda_pin = GPIO_I2C4_SDA,
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#ifndef CONFIG_I2C_POLLED
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.isr = stm32_i2c4_isr,
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.ev_irq = STM32_IRQ_I2C4EV,
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.er_irq = STM32_IRQ_I2C4ER
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#endif
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};
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struct stm32_i2c_priv_s stm32_i2c4_priv =
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{
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.config = &stm32_i2c4_config,
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.refs = 0,
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.intstate = INTSTATE_IDLE,
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.msgc = 0,
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.msgv = NULL,
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.ptr = NULL,
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.frequency = 0,
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.dcnt = 0,
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.flags = 0,
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.status = 0
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};
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#endif
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/* Device Structures, Instantiation */
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struct i2c_ops_s stm32_i2c_ops =
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@ -1167,10 +1234,10 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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*
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* This function supports bus clock frequencies of:
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*
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* 500Khz
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* 400Khz
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* 100Khz
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* 10Khz
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* 1000Khz (Fast Mode+)
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* 400Khz (Fast Mode)
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* 100Khz (Standard Mode)
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* 10Khz (Standard Mode)
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*
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* Attempts to set a different frequency will quietly provision the default
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* of 10Khz.
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@ -1186,15 +1253,15 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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*
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* Clock Selection:
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*
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* The I2C peripheral clock can be provided by either SYSCLK or the HSI.
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* The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the HSI.
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*
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* SYSCLK >------|\ I2CCLK
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* | |--------->
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* PCLK1 >------|\ I2CCLK
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* SYSCLK >------| |--------->
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* HSI >------|/
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*
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* HSI is the default and is always 8Mhz.
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* HSI is the default and is always 16Mhz.
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*
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* SYSCLK can, in turn, be derived from the HSI, PLL or HSE.
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* SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK.
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*
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* HSI >------|\
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* | | SYSCLK
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@ -1202,19 +1269,10 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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* | |
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* HSE >------|/
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*
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* The ability to select the I2C peripheral clock source is not yet supported
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* so all of this really only works at 8Mhz. The values provided are copied
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* directly from the 8Mhz example table in RM0316 (See References).
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*
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* TODO:
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*
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* - Add support for peripheral clock source selection (SYSCLK vs HSI).
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* - Calculate values for a given SYSCLK frequency.
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* - Add support for Fast Mode Plus (up to 1Mhz)
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*
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* References:
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*
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* RM0316: Section: 28.4.9: I2C_TIMINGR register configuration examples
|
||||
* App Note AN4235 and the associated software STSW-STM32126.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
@ -1237,33 +1295,46 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
|
||||
stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
|
||||
}
|
||||
|
||||
/* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
|
||||
digital off from STM32F0-F3_AN4235_V1.0.1 */
|
||||
/* The Sppeed and timing calculation are based on the following
|
||||
* fI2CCLK = HSI and is 16Mhz
|
||||
* Analog filter is on,
|
||||
* Digital filter off
|
||||
* Rise Time is 120 ns and fall is 10ns
|
||||
* Mode is FastMode
|
||||
*/
|
||||
|
||||
if (frequency == 100000)
|
||||
{
|
||||
presc = 0x06;
|
||||
scl_delay = 0x02;
|
||||
sda_delay = 0x00;
|
||||
scl_h_period = 0x1e;
|
||||
scl_l_period = 0x2b;
|
||||
presc = 0;
|
||||
scl_delay = 3;
|
||||
sda_delay = 0;
|
||||
scl_h_period = 30;
|
||||
scl_l_period = 120;
|
||||
|
||||
}
|
||||
else if (frequency == 400000)
|
||||
{
|
||||
presc = 0x00;
|
||||
scl_delay = 0x0A;
|
||||
sda_delay = 0x00;
|
||||
scl_h_period = 0x1b;
|
||||
scl_l_period = 0x5b;
|
||||
}
|
||||
else if (frequency == 400000)
|
||||
{
|
||||
presc = 0;
|
||||
scl_delay = 3;
|
||||
sda_delay = 9;
|
||||
scl_h_period = 6;
|
||||
scl_l_period = 24;
|
||||
}
|
||||
else if (frequency == 1000000)
|
||||
{
|
||||
presc = 0;
|
||||
scl_delay = 2;
|
||||
sda_delay = 0;
|
||||
scl_h_period = 1;
|
||||
scl_l_period = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
presc = 0x00;
|
||||
scl_delay = 0x08;
|
||||
sda_delay = 0x00;
|
||||
scl_h_period = 0x09;
|
||||
scl_l_period = 0x1c;
|
||||
presc = 7;
|
||||
scl_delay = 0;
|
||||
sda_delay = 0;
|
||||
scl_h_period = 35;
|
||||
scl_l_period = 162;
|
||||
}
|
||||
|
||||
uint32_t timingr =
|
||||
@ -2069,12 +2140,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
#ifdef CONFIG_STM32F7_I2C1
|
||||
# ifdef CONFIG_STM32F7_I2C1
|
||||
static int stm32_i2c1_isr(int irq, void *context)
|
||||
{
|
||||
return stm32_i2c_isr(&stm32_i2c1_priv);
|
||||
}
|
||||
#endif
|
||||
# endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_i2c2_isr
|
||||
@ -2084,12 +2155,12 @@ static int stm32_i2c1_isr(int irq, void *context)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C2
|
||||
# ifdef CONFIG_STM32F7_I2C2
|
||||
static int stm32_i2c2_isr(int irq, void *context)
|
||||
{
|
||||
return stm32_i2c_isr(&stm32_i2c2_priv);
|
||||
}
|
||||
#endif
|
||||
# endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_i2c3_isr
|
||||
@ -2099,12 +2170,27 @@ static int stm32_i2c2_isr(int irq, void *context)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C3
|
||||
# ifdef CONFIG_STM32F7_I2C3
|
||||
static int stm32_i2c3_isr(int irq, void *context)
|
||||
{
|
||||
return stm32_i2c_isr(&stm32_i2c3_priv);
|
||||
}
|
||||
#endif
|
||||
# endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_i2c4_isr
|
||||
*
|
||||
* Description:
|
||||
* I2C2 interrupt service routine
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
# ifdef CONFIG_STM32F7_I2C4
|
||||
static int stm32_i2c4_isr(int irq, void *context)
|
||||
{
|
||||
return stm32_i2c_isr(&stm32_i2c4_priv);
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@ -2465,13 +2551,9 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
|
||||
struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */
|
||||
int irqs;
|
||||
|
||||
#if STM32_PCLK1_FREQUENCY < 4000000
|
||||
# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
|
||||
#endif
|
||||
|
||||
#if STM32_PCLK1_FREQUENCY < 2000000
|
||||
# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
|
||||
return NULL;
|
||||
#if STM32_HSI_FREQUENCY != 16000000 || defined(INVALID_CLOCK_SOURCE)
|
||||
# warning STM32_I2C_INIT: Peripheral clock is HSI and it must be 16mHz or the speed/timing calculations need to be redone.
|
||||
return NULL;
|
||||
#endif
|
||||
|
||||
/* Get I2C private structure */
|
||||
@ -2492,6 +2574,11 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
|
||||
case 3:
|
||||
priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32F7_I2C4
|
||||
case 4:
|
||||
priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return NULL;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user