Completes USB definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3036 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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aac576aa71
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@ -661,16 +661,16 @@
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/* Endpoint Status Clear Register Bit-field Definitions */
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/* Endpoint Status Set Register Bit-field Definitions (common fields) */
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#define USBB_UESTA_SHORTPACKET (1 << 7) /* Bit 7: Short Packet Interrupt */
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#define USBB_UESTA_STALLEDI (1 << 6) /* Bit 6: STALLed Interrupt */
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#define USBB_UESTA_CRCERRI (1 << 6) /* Bit 6: CRC Error Interrupt */
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#define USBB_UESTA_OVERFI (1 << 5) /* Bit 5: Overflow Interrupt */
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#define USBB_UESTA_NAKINI (1 << 4) /* Bit 4: NAKed IN Interrupt */
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#define USBB_UESTA_NAKOUTI (1 << 3) /* Bit 3: NAKed OUT Interrupt */
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#define USBB_UESTA_TXINI (1 << 0) /* Bit 0: Transmitted IN Data Interrupt */
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#define USBB_UESTA_RXOUTI (1 << 1) /* Bit 1: Received OUT Data Interrupt */
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#define USBB_UESTA_UNDERFI (1 << 2) /* Bit 2: Underflow Interrupt */
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#define USBB_UESTA_RXSTPI (1 << 2) /* Bit 2: Received SETUP Interrupt */
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#define USBB_UESTA_RXOUTI (1 << 1) /* Bit 1: Received OUT Data Interrupt */
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#define USBB_UESTA_TXINI (1 << 0) /* Bit 0: Transmitted IN Data Interrupt */
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#define USBB_UESTA_NAKOUTI (1 << 3) /* Bit 3: NAKed OUT Interrupt */
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#define USBB_UESTA_NAKINI (1 << 4) /* Bit 4: NAKed IN Interrupt */
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#define USBB_UESTA_OVERFI (1 << 5) /* Bit 5: Overflow Interrupt */
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#define USBB_UESTA_STALLEDI (1 << 6) /* Bit 6: STALLed Interrupt */
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#define USBB_UESTA_CRCERRI (1 << 6) /* Bit 6: CRC Error Interrupt */
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#define USBB_UESTA_SHORTPACKET (1 << 7) /* Bit 7: Short Packet Interrupt */
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/* Endpoint Status Register Bit-field Definitions (only in UESTA) */
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@ -754,83 +754,196 @@
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/* Host General Control Register Bit-field Definitions */
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#define USBB_UHCON_
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#define USBB_UHCON_SOFE (1 << 8) /* Bit 8: Start of Frame Generation Enable */
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#define USBB_UHCON_RESET (1 << 9) /* Bit 9: Send USB Reset */
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#define USBB_UHCON_RESUME (1 << 10) /* Bit 10: Send USB Resume */
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/* Host Global Interrupt Register Bit-field Definitions */
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#define USBB_UHINT_
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/* Host Global Interrupt Clear Register Bit-field Definitions */
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#define USBB_UHINTCLR_
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/* Host Global Interrupt Set Register Bit-field Definitions */
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#define USBB_UHINTSET_
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/* Host Global Interrupt Clear Register Bit-field Definitions (Except as noted 1) */
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/* Host Global Interrupt Set Register Bit-field Definitions (Except as noted 2) */
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/* Host Global Interrupt Enable Register Bit-field Definitions */
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#define USBB_UHINTE_
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/* Host Global Interrupt Enable Clear Register Bit-field Definitions */
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#define USBB_UHINTECLR_
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/* Host Global Interrupt Enable Set Register Bit-field Definitions */
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#define USBB_UHINTESET_
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#define USBB_UHINT_DCONNI (1 << 0) /* Bit 0: Device Connection Interrupt (1) */
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#define USBB_UHINT_DDISCI (1 << 1) /* Bit 1: Device Disconnection Interrupt (1) */
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#define USBB_UHINT_RSTI (1 << 2) /* Bit 2: USB Reset Sent Interrupt (1) */
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#define USBB_UHINT_RSMEDI (1 << 3) /* Bit 3: Downstream Resume Sent Interrupt (1) */
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#define USBB_UHINT_RXRSMI (1 << 4) /* Bit 4: Upstream Resume Received Interrupt (1) */
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#define USBB_UHINT_HSOFI (1 << 5) /* Bit 5: Host Start of Frame Interrupt (1) */
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#define USBB_UHINT_HWUPI (1 << 6) /* Bit 6: Host Wake-Up Interrupt (1) */
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#define USBB_UHINT_PINT(n) (1 << ((n)+8))
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#define USBB_UHINT_P0INT (1 << 8) /* Bit 8: Pipe 0 Interrupt (1,2) */
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#define USBB_UHINT_P1INT (1 << 9) /* Bit 9: Pipe 1 Interrupt (1,2) */
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#define USBB_UHINT_P2INT (1 << 10) /* Bit 10: Pipe 2 Interrupt (1,2) */
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#define USBB_UHINT_P3INT (1 << 11) /* Bit 11: Pipe 3 Interrupt (1,2) */
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#define USBB_UHINT_P4INT (1 << 12) /* Bit 12: Pipe 4 Interrupt (1,2) */
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#define USBB_UHINT_P5INT (1 << 13) /* Bit 13: Pipe 5 Interrupt (1,2) */
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#define USBB_UHINT_P6INT (1 << 14) /* Bit 14: Pipe 6 Interrupt (1,2) */
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#define USBB_UHINT_DMAINT(n) (1 << ((n)+24))
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#define USBB_UHINT_DMAINT1 (1 << 25) /* Bit 25: DMA Channel 1 Interrupt */
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#define USBB_UHINT_DMAINT2 (1 << 26) /* Bit 26: DMA Channel 2 Interrupt */
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#define USBB_UHINT_DMAINT3 (1 << 27) /* Bit 27: DMA Channel 3 Interrupt */
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#define USBB_UHINT_DMAINT4 (1 << 28) /* Bit 28: DMA Channel 4 Interrupt */
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#define USBB_UHINT_DMAINT5 (1 << 29) /* Bit 29: DMA Channel 5 Interrupt */
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#define USBB_UHINT_DMAINT6 (1 << 30) /* Bit 30: DMA Channel 6 Interrupt */
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/* Pipe Enable/Reset Register Bit-field Definitions */
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#define USBB_UPRST_
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#define USBB_UPRST_PEN(n) (1 << (n))
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#define USBB_UPRST_PEN0 (1 << 0) /* Bit 0: Pipe 0 Enable */
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#define USBB_UPRST_PEN1 (1 << 1) /* Bit 1: Pipe 1 Enable */
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#define USBB_UPRST_PEN2 (1 << 2) /* Bit 2: Pipe 2 Enable */
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#define USBB_UPRST_PEN3 (1 << 3) /* Bit 3: Pipe 3 Enable */
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#define USBB_UPRST_PEN4 (1 << 4) /* Bit 4: Pipe 4 Enable */
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#define USBB_UPRST_PEN5 (1 << 5) /* Bit 5: Pipe 5 Enable */
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#define USBB_UPRST_PEN6 (1 << 6) /* Bit 6: Pipe 6 Enable */
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#define USBB_UPRST_PRST(n) (1 << ((n)+16))
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#define USBB_UPRST_PRST0 (1 << 16) /* Bit 16: Pipe 0 Reset */
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#define USBB_UPRST_PRST1 (1 << 17) /* Bit 17: Pipe 1 Reset */
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#define USBB_UPRST_PRST2 (1 << 18) /* Bit 18: Pipe 2 Reset */
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#define USBB_UPRST_PRST3 (1 << 19) /* Bit 19: Pipe 3 Reset */
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#define USBB_UPRST_PRST4 (1 << 20) /* Bit 20: Pipe 4 Reset */
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#define USBB_UPRST_PRST5 (1 << 21) /* Bit 21: Pipe 5 Reset */
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#define USBB_UPRST_PRST6 (1 << 22) /* Bit 22: Pipe 6 Reset */
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/* Host Frame Number Register Bit-field Definitions */
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#define USBB_UHFNUM_
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#define USBB_UHFNUM_FNUM_SHIFT (3) /* Bits 3-13: Frame Number */
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#define USBB_UHFNUM_FNUM_MASK (0x7ff << USBB_UHFNUM_FNUM_SHIFT)
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#define USBB_UHFNUM_FLENHIGH_SHIFT (16) /* Bits 16-23: Frame Length */
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#define USBB_UHFNUM_FLENHIGH_MASK (0xff << USBB_UHFNUM_FLENHIGH_SHIFT)
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/* Host Address 1 Register Bit-field Definitions */
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#define USBB_UHADDR1_
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#define USBB_UHADDR1_UHADDRP0_SHIFT (0) /* Bits 0-6: USB Host Address (Pipe 0) */
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#define USBB_UHADDR1_UHADDRP0_MASK (0x7f << USBB_UHADDR1_UHADDRP0_SHIFT)
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#define USBB_UHADDR1_UHADDRP1_SHIFT (8) /* Bits 8-14: USB Host Address (Pipe 1) */
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#define USBB_UHADDR1_UHADDRP1_MASK (0x7f << USBB_UHADDR1_UHADDRP1_SHIFT)
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#define USBB_UHADDR1_UHADDRP2_SHIFT (16) /* Bits 16-22: USB Host Address (Pipe 2) */
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#define USBB_UHADDR1_UHADDRP2_MASK (0x7f << USBB_UHADDR1_UHADDRP2_SHIFT)
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#define USBB_UHADDR1_UHADDRP3_SHIFT (24) /* Bits 24-30: USB Host Address (Pipe 3) */
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#define USBB_UHADDR1_UHADDRP3_MASK (0x7f << USBB_UHADDR1_UHADDRP3_SHIFT)
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/* Host Address 2 Register Bit-field Definitions */
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#define USBB_UHADDR2_
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#define USBB_UHADDR2_UHADDRP4_SHIFT (0) /* Bits 0-6: USB Host Address (Pipe 4) */
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#define USBB_UHADDR2_UHADDRP4_MASK (0x7f << USBB_UHADDR1_UHADDRP4_SHIFT)
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#define USBB_UHADDR2_UHADDRP5_SHIFT (8) /* Bits 8-14: USB Host Address (Pipe 5) */
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#define USBB_UHADDR2_UHADDRP5_MASK (0x7f << USBB_UHADDR1_UHADDRP5_SHIFT)
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#define USBB_UHADDR2_UHADDRP6_SHIFT (16) /* Bits 16-22: USB Host Address (Pipe 6) */
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#define USBB_UHADDR2_UHADDRP6_MASK (0x7f << USBB_UHADDR1_UHADDRP6_SHIFT)
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#
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/* Pipe Configuration Register Bit-field Definitions */
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#define USBB_UPCFG_
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#define USBB_UPCFG_ALLOC (1 << 1) /* Bit 1: Pipe Memory Allocate */
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#define USBB_UPCFG_PBK_SHIFT (2) /* Bits 2-3: Pipe Banks */
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#define USBB_UPCFG_PBK_MASK (3 << USBB_UPCFG_PBK_SHIFT)
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# define USBB_UPCFG_PBK_1 (0 << USBB_UPCFG_PBK_SHIFT) /* 1 (single-bank pipe) */
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# define USBB_UPCFG_PBK_2 (1 << USBB_UPCFG_PBK_SHIFT) /* 2 (double-bank pipe) */
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# define USBB_UPCFG_PBK_3 (2 << USBB_UPCFG_PBK_SHIFT) /* 3 (triple-bank pipe) */
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#define USBB_UPCFG_PSIZE_SHIFT (4) /* Bits 4-6: Pipe Size */
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#define USBB_UPCFG_PSIZE_MASK (7 << USBB_UPCFG_PSIZE_SHIFT)
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# define USBB_UPCFG_PSIZE_8 (0 << USBB_UPCFG_PSIZE_SHIFT) /* 8 bytes */
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# define USBB_UPCFG_PSIZE_16 (1 << USBB_UPCFG_PSIZE_SHIFT) /* 16 bytes */
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# define USBB_UPCFG_PSIZE_32 (2 << USBB_UPCFG_PSIZE_SHIFT) /* 32 bytes */
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# define USBB_UPCFG_PSIZE_64 (3 << USBB_UPCFG_PSIZE_SHIFT) /* 64 bytes */
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# define USBB_UPCFG_PSIZE_128 (4 << USBB_UPCFG_PSIZE_SHIFT) /* 128 bytes */
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# define USBB_UPCFG_PSIZE_256 (5 << USBB_UPCFG_PSIZE_SHIFT) /* 256 bytes */
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# define USBB_UPCFG_PSIZE_512 (6 << USBB_UPCFG_PSIZE_SHIFT) /* 512 bytes */
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# define USBB_UPCFG_PSIZE_1024 (7 << USBB_UPCFG_PSIZE_SHIFT) /* 1024 bytes */
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#define USBB_UPCFG_PTOKEN_SHIFT (8) /* Bits 8-9: Pipe Token */
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#define USBB_UPCFG_PTOKEN_MASK (3 << USBB_UPCFG_PTOKEN_SHIFT)
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# define USBB_UPCFG_PTOKEN_SETUP (0 << USBB_UPCFG_PTOKEN_SHIFT) /* SETUP */
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# define USBB_UPCFG_PTOKEN_IN (1 << USBB_UPCFG_PTOKEN_SHIFT) /* IN */
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# define USBB_UPCFG_PTOKEN_OUT (2 << USBB_UPCFG_PTOKEN_SHIFT) /* OUT */
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#define USBB_UPCFG_AUTOSW (1 << 10) /* Bit 10: Automatic Switch */
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#define USBB_UPCFG_PTYPE_SHIFT (11) /* Bits 11-12: Pipe Type */
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#define USBB_UPCFG_PTYPE_MASK (3 << USBB_UPCFG_PTYPE_SHIFT)
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# define USBB_UPCFG_PTYPE_CTRL (0 << USBB_UPCFG_PTYPE_SHIFT) /* Control */
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# define USBB_UPCFG_PTYPE_ISOC (1 << USBB_UPCFG_PTYPE_SHIFT) /* Isochronous */
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# define USBB_UPCFG_PTYPE_BULK (2 << USBB_UPCFG_PTYPE_SHIFT) /* Bulk */
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# define USBB_UPCFG_PTYPE_INTR (3 << USBB_UPCFG_PTYPE_SHIFT) /* Interrupt */
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#define USBB_UPCFG_PEPNUM_SHIFT (16) /* Bits 16-19: Pipe Endpoint Number */
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#define USBB_UPCFG_PEPNUM_MASK (15 << USBB_UPCFG_PEPNUM_SHIFT)
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#define USBB_UPCFG_INTFRQ_SHIFT (24) /* Bits 24-31: Pipe Interrupt Request Frequency */
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#define USBB_UPCFG_INTFRQ_MASK (0xff << USBB_UPCFG_INTFRQ_SHIFT)
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/* Pipe Status Register Bit-field Definitions */
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/* Pipe Status Register Bit-field Definitions (common) */
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/* Pipe Status Clear Register Bit-field Definitions (common) */
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/* Pipe Status Set Register Bit-field Definitions (common) */
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#define USBB_UPSTA_
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#define USBB_UPSTA_RXINI (1 << 0) /* Bit 0: Received IN Data Interrupt */
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#define USBB_UPSTA_TXOUTI (1 << 1) /* Bit 1: Transmitted OUT Data Interrupt */
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#define USBB_UPSTA_TXSTPI (1 << 2) /* Bit 2: Transmitted SETUP Interrupt */
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#define USBB_UPSTA_UNDERFI (1 << 2) /* Bit 2: Underflow Interrupt */
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#define USBB_UPSTA_PERRI (1 << 3) /* Bit 3: Pipe Error Interrupt */
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#define USBB_UPSTA_NAKEDI (1 << 4) /* Bit 4: NAKed Interrupt */
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#define USBB_UPSTA_OVERFI (1 << 5) /* Bit 5: Overflow Interrupt */
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#define USBB_UPSTA_RXSTALLDI (1 << 6) /* Bit 6: Received STALLed Interrupt */
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#define USBB_UPSTA_CRCERRI (1 << 6) /* Bit 6: CRC Error Interrupt */
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#define USBB_UPSTA_SHORTPACKET (1 << 7) /* Bit 7: Short Packet Interrupt */
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/* Pipe Status Clear Register Bit-field Definitions */
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/* Pipe Status Register Bit-field Definitions (only in UPSTA) */
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#define USBB_UPSTACLR_
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#define USBB_UPSTA_DTSEQ_SHIFT (8) /* Bits 8-9: Data Toggle Sequence */
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#define USBB_UPSTA_DTSEQ_MASK (3 << USBB_UPSTA_DTSEQ_SHIFT)
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# define USBB_UPSTA_DTSEQ_DATA0 (0 << USBB_UPSTA_DTSEQ_SHIFT) /* Data0 */
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# define USBB_UPSTA_DTSEQ_DATA1 (1 << USBB_UPSTA_DTSEQ_SHIFT) /* Data1 */
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#define USBB_UPSTA_NBUSYBK_SHIFT (12) /* Bits 12-13: Number of Busy Banks */
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#define USBB_UPSTA_NBUSYBK_MASK (3 << USBB_UPSTA_NBUSYBK_SHIFT)
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# define USBB_UPSTA_NBUSYBK_NONE (0 << USBB_UPSTA_NBUSYBK_SHIFT) /* 0 (all banks free) */
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# define USBB_UPSTA_NBUSYBK_1BANK (1 << USBB_UPSTA_NBUSYBK_SHIFT) /* 1 */
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# define USBB_UPSTA_NBUSYBK_2BANKS (2 << USBB_UPSTA_NBUSYBK_SHIFT) /* 2 */
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#define USBB_UPSTA_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */
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#define USBB_UPSTA_CURRBK_MASK (3 << USBB_UPSTA_CURRBK_SHIFT)
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# define USBB_UPSTA_CURRBK_BANK0 (0 << USBB_UPSTA_CURRBK_SHIFT) /* Bank0 */
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# define USBB_UPSTA_CURRBK_BANK1 (1 << USBB_UPSTA_CURRBK_SHIFT) /* Bank1 */
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# define USBB_UPSTA_CURRBK_BANK2 (2 << USBB_UPSTA_CURRBK_SHIFT) /* Bank2 */
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#define USBB_UPSTA_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */
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#define USBB_UPSTA_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */
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#define USBB_UPSTA_PBYCT_SHIFT (20) /* Bits 20-30: Pipe Byte Count */
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#define USBB_UPSTA_PBYCT_MASK (0x7ff << USBB_UPSTA_BYCT_SHIFT)
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/* Pipe Status Set Register Bit-field Definitions */
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/* Pipe Status Set Register Bit-field Definitions (only in UPSTASET) */
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#define USBB_UPSTASET_
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#define USBB_UPSTASET_NBUSYBKS (1 << 12) /* Bit 12 */
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/* Pipe Control Register Bit-field Definitions */
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/* Pipe Control Clear Register Bit-field Definitions (except as noted 1) */
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/* Pipe Control Set Register Bit-field Definitions (except as noted 2) */
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#define USBB_UPCON_
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/* Pipe Control Set Register Bit-field Definitions */
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#define USBB_UPCONSET_
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/* Pipe Control Clear Register Bit-field Definitions */
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#define USBB_UPCONCLR_
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#define USBB_UPCON_RXINE (1 << 0) /* Bit 0: Received IN Data Interrupt Enable */
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#define USBB_UPCON_TXOUTE (1 << 1) /* Bit 1: Transmitted OUT Data Interrupt Enable */
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#define USBB_UPCON_TXSTPE (1 << 2) /* Bit 2: Transmitted SETUP Interrupt Enable */
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#define USBB_UPCON_UNDERFIE (1 << 2) /* Bit 2: Underflow Interrupt Enable */
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#define USBB_UPCON_PERRE (1 << 3) /* Bit 3: Pipe Error Interrupt Enable */
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#define USBB_UPCON_NAKEDE (1 << 4) /* Bit 4: NAKed Interrupt Enable */
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#define USBB_UPCON_OVERFIE (1 << 5) /* Bit 5: Overflow Interrupt Enable */
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#define USBB_UPCON_RXSTALLDE (1 << 6) /* Bit 6: Received STALLed Interrupt Enable */
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#define USBB_UPCON_CRCERRE (1 << 6) /* Bit 6: CRC Error Interrupt Enable */
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#define USBB_UPCON_SHORTPACKETIE (1 << 7) /* Bit 7: Short Packet Interrupt Enable */
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#define USBB_UPCON_NBUSYBKE (1 << 12) /* Bit 12: Number of Busy Banks Interrupt Enable */
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#define USBB_UPCON_FIFOCON (1 << 14) /* Bit 14: FIFO Control (2) */
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#define USBB_UPCON_PDISHDMA (1 << 16) /* Bit 16: Pipe Interrupts Disable HDMA Request Enable */
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#define USBB_UPCON_PFREEZE (1 << 17) /* Bit 17: Pipe Freeze */
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#define USBB_UPCON_RSTDT (1 << 18) /* Bit 18: Reset Data Toggle (1) */
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/* Pipe IN Request Register Bit-field Definitions */
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#define USBB_UPINRQ_
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#define USBB_UPINRQ_INRQ_SHIFT (0) /* Bits 0-7: IN Request Number before Freeze */
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#define USBB_UPINRQ_INRQ_MASK (0xff << USBB_UPINRQ_INRQ_SHIFT)
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#define USBB_UPINRQ_INMODE (1 << 8) /* Bit 8: IN Request Mode */
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/* Pipe Error Register Bit-field Definitions */
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#define USBB_UPERR_
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#define USBB_UPERR_DATATGL (1 << 0) /* Bit 0: Data Toggle Error */
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#define USBB_UPERR_DATAPID (1 << 1) /* Bit 1: Data PID Error */
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#define USBB_UPERR_PID (1 << 2) /* Bit 2: PID Error */
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#define USBB_UPERR_TIMEOUT (1 << 3) /* Bit 3: Time-Out Error */
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#define USBB_UPERR_CRC16 (1 << 4) /* Bit 4: CRC16 Error */
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#define USBB_UPERR_COUNTER_SHIFT (5) /* Bits 5-6: Error Counter */
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#define USBB_UPERR_COUNTER_MASK (3 << USBB_UPERR_COUNTER_SHIFT)
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/* Host DMA Channel Next Descriptor Address Register Bit-field Definitions */
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@ -959,10 +1072,6 @@
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# define USBB_USBFSM_B_HOST (14)
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# define USBB_USBFSM_B_SRPINIT (15)
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(1 << xxx) /* Bit xxx:
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_SHIFT (xxx) /* Bits xxx-xxx:
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_MASK (xxx << xxx)
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/* USB HSB Memory Map ***************************************************************/
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#define USB_FIFO0_DATA_OFFSET 0x00000 /* Pipe/Endpoint 0 FIFO Data Register */
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