Basic clocking and UART works
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1786 42af7a65-404d-4744-a932-0658087f49c3
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@ -183,7 +183,7 @@
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#define GPIO_PWM4_CCP (GPIO_FUNC_PFIO | GPIO_PORTC | 7) /* PC7: Capture/Compare/PWM4 (CCP4) */
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#define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
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#define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
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#define GPIO_SSI1_CLK (GPIO_FUNC_PFIO1 | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */
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#define GPIO_SSI1_CLK (GPIO_FUNC_PFIO | GPIO_PORTE | 0) /* PE0: SSI1 clock (SSI1Clk) */
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#define GPIO_SSI1_FSS (GPIO_FUNC_PFIO | GPIO_PORTE | 1) /* PE1: SSI1 frame (SSI1Fss) */
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#define GPIO_SSI1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: SSI1 receive (SSI1Rx) */
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#define GPIO_SSI1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 3) /* PE3: SSI1 transmit (SSI1Tx) */
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@ -220,47 +220,61 @@ void up_lowputc(char ch)
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void up_lowsetup(void)
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{
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uint32 regval;
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#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
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uint32 ctl;
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/* Enable the selected console device */
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/* 1. Disable the UART by clearing the UARTEN bit in the UART CTL register */
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ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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ctl &= ~UART_CTL_UARTEN;
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putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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/* 2. Write the integer portion of the BRD to the UART IBRD register */
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putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
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/* 3. Write the fractional portion of the BRD to the UART FBRD register */
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putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
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/* 4. Write the desired serial parameters to the UART LCRH register */
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putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
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/* 5. Enable the UART by setting the UARTEN bit in the UART CTL register */
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ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
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putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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#endif
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/* Then configure GPIO pins to enable the selected UARTs. NOTE: The
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* serial driver later depends on this pin configuration.
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/* Enable the selected UARTs and configure GPIO pins to need by the
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* the selected UARTs. NOTE: The serial driver later depends on
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* this pin configuration -- whether or not a serial console is selected.
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*/
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#ifndef CONFIG_UART0_DISABLE
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regval = getreg32(LM3S_SYSCON_RCGC1);
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regval |= SYSCON_RCGC1_UART0;
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putreg32(regval, LM3S_SYSCON_RCGC1);
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lm3s_configgpio(GPIO_UART0_RX);
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lm3s_configgpio(GPIO_UART0_TX);
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#endif
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#ifndef CONFIG_UART1_DISABLE
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regval = getreg32(LM3S_SYSCON_RCGC1);
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regval |= SYSCON_RCGC1_UART1;
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putreg32(regval, LM3S_SYSCON_RCGC1);
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lm3s_configgpio(GPIO_UART1_RX);
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lm3s_configgpio(GPIO_UART1_TX);
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#endif
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/* Enable the selected console device */
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#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
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/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
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ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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ctl &= ~UART_CTL_UARTEN;
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putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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/* Write the integer portion of the BRD to the UART IBRD register */
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putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
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/* Write the fractional portion of the BRD to the UART FBRD register */
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putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
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/* Write the desired serial parameters to the UART LCRH register */
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putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
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/* Enable the UART by setting the UARTEN bit in the UART CTL register */
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ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
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putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
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#endif
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}
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