SAMA5: Add ADC-side of the logic to hook in timer/counter logic needed to drive periodic ADC sampling
This commit is contained in:
Gregory Nutt
parent
aab5b6b2d9
commit
da7a3d9c9a
@ -2141,7 +2141,7 @@ endchoice # TC0 channel
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choice
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prompt "TIOAx edge"
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default SAMA5_ADC_TIOA_BOTH
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depends on SAMA5_ADC_ADTRG
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depends on SAMA5_ADC_TIOATRIG
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config SAMA5_ADC_TIOA_RISING
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bool "Rising edge"
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@ -67,9 +67,14 @@
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#include "up_arch.h"
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#include "chip.h"
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#include "cache.h"
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#include "chip/sam_adc.h"
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#include "chip/sam_pmc.h"
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#include "chip/sam_pinmap.h"
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#include "sam_periphclks.h"
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#include "sam_memories.h"
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#include "sam_pio.h"
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#include "sam_dmac.h"
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#include "sam_tc.h"
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#include "sam_tsd.h"
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@ -374,7 +379,7 @@ struct sam_adc_s
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volatile bool ready; /* Worker has completed the last set of samples */
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volatile bool enabled; /* DMA data transfer is enabled */
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#endif
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struct adc_dev_s dev; /* The external via of the ADC device */
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struct adc_dev_s *dev; /* A reference to the outer, ADC device container */
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uint32_t pending; /* Pending EOC events */
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struct work_s work; /* Supports the interrupt handling "bottom half" */
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#ifdef CONFIG_SAMA5_ADC_DMA
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@ -419,7 +424,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
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static void sam_adc_dmadone(void *arg);
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static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result);
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static int sam_adc_dmasetup(struct sam_adc_s *priv, FAR uint8_t *buffer,
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size_t buflen)
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size_t buflen);
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#endif
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/* ADC interrupt handling */
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@ -440,10 +445,11 @@ static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg);
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/* Initialization/Configuration */
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#ifdef CONFIG_SAMA5_ADC_TIOATRIG
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static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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int channel, boot tioa);
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static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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int channel);
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static void sam_adc_freetimer(struct sam_adc_s *priv);
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#endif
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static void sam_adc_trigger(struct sam_adc_s *priv);
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static int sam_adc_trigger(struct sam_adc_s *priv);
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static void sam_adc_autocalibrate(struct sam_adc_s *priv);
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static void sam_adc_offset(struct sam_adc_s *priv);
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static void sam_adc_gain(struct sam_adc_s *priv);
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@ -479,7 +485,7 @@ static struct sam_adc_s g_adcpriv;
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static struct adc_dev_s g_adcdev =
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{
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.ad_ops = &g_adcops,
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.ad_priv = &g_adcpriv.dev,
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.ad_priv = &g_adcpriv,
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};
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#endif
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@ -581,7 +587,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr,
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static void sam_adc_dmadone(void *arg)
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{
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struct sam_adc_s *priv = (struct sam_adc_s *)arg;
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uint16_t *buffer;
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uint32_t *buffer;
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uint16_t sample;
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int chan;
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int i;
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@ -612,9 +618,9 @@ static void sam_adc_dmadone(void *arg)
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chan = (int)((*buffer & ADC_LCDR_CHANB_MASK) >> ADC_LCDR_CHANB_SHIFT);
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sample = (uint16_t)((*buffer & ADC_LCDR_DATA_MASK) >> ADC_LCDR_DATA_SHIFT);
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/* And give the sample data to the ADC upper half */
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/* And give the sample data to the ADC upper half */
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(void)adc_receive(&priv->dev, chan, sample);
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(void)adc_receive(priv->dev, chan, sample);
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}
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}
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@ -637,7 +643,8 @@ static void sam_adc_dmadone(void *arg)
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#ifdef CONFIG_SAMA5_ADC_DMA
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static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
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{
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struct sam_dev_s *priv = (struct sam_dev_s *)arg;
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struct sam_adc_s *priv = (struct sam_adc_s *)arg;
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int ret;
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/* Check of the bottom half is keeping up with us */
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@ -664,7 +671,7 @@ static void sam_adc_dmacallback(DMA_HANDLE handle, void *arg, int result)
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/* Restart the DMA conversion using the next buffer */
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sam_adc_dmasetup(priv->dma,
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priv->odd ? (void *)priv->oddbuf , (void *)priv->evenbuf
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priv->odd ? (void *)priv->oddbuf : (void *)priv->evenbuf,
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SAMA5_NCHANNELS);
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}
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#endif
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@ -752,7 +759,7 @@ static void sam_adc_endconversion(void *arg)
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/* Get exclusive access to the driver data structure */
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sam_adc_lock(priv->adc);
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sam_adc_lock(priv);
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/* Check for the end of conversion event on each channel */
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@ -763,23 +770,19 @@ static void sam_adc_endconversion(void *arg)
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{
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/* Read the ADC sample and pass it to the upper half */
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regval = sam_adc_getreg(priv, SAM_ADC_CDR(chan));
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ret = adc_receive(&priv->dev, chan, regval & ADC_CDR_DATA_MASK);
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regval = sam_adc_getreg(priv, SAM_ADC_CDR(chan));
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(void)adc_receive(priv->dev, chan, regval & ADC_CDR_DATA_MASK);
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pending &= ~bit;
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}
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}
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/* Exit, re-enabling ADC interrupts */
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ignored:
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/* Re-enable ADC interrupts. */
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sam_adc_putreg32(priv->adc, SAM_ADC_IER, SAMA5_CHAN_ENABLE);
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sam_adc_putreg(priv, SAM_ADC_IER, SAMA5_CHAN_ENABLE);
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/* Release our lock on the ADC structure */
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sem_adc_unlock(priv->adc);
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sam_adc_unlock(priv);
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}
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#endif /* SAMA5_ADC_HAVE_CHANNELS */
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@ -829,7 +832,7 @@ static int sam_adc_interrupt(int irq, void *context)
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* interrupts will be re-enabled after the worker thread executes.
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*/
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sam_adc_putreg32(priv->adc, SAM_ADC_IDR, ADC_INT_EOCALL);
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sam_adc_putreg(priv, SAM_ADC_IDR, ADC_INT_EOCALL);
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/* Save the set of pending interrupts for the bottom half (in case any
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* were cleared by reading the ISR).
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@ -884,7 +887,7 @@ static void sam_adc_reset(struct adc_dev_s *dev)
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/* Stop any DMA */
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dma_stop(priv->dma);
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sam_dmastop(priv->dma);
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/* Stop an release any timer */
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@ -908,15 +911,15 @@ static void sam_adc_reset(struct adc_dev_s *dev)
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/* Reset gain, offset, differential modes */
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sam_adc_putreg(priv, SAM_CGR_MR, 0);
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sam_adc_putreg(priv, SAM_COR_MR, 0);
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sam_adc_putreg(priv, SAM_ADC_CGR, 0);
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sam_adc_putreg(priv, SAM_ADC_COR, 0);
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#ifndef CONFIG_SAMA5_ADC_SWTRIG
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/* Select software trigger (i.e., basically no trigger) */
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regval = sam_adc_getreg(priv->dev, SAM_ADC_MR);
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_TRGSEL_MASK;
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sam_adc_putreg(priv->dev, SAM_ADC_MR, regval);
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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regval = sam_adc_getreg(priv, SAM_ADC_TRGR);
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regval &= ~ADC_TRGR_TRGMOD_MASK;
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@ -939,7 +942,7 @@ static void sam_adc_reset(struct adc_dev_s *dev)
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static int sam_adc_setup(struct adc_dev_s *dev)
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{
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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int ret;
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uint32_t regval;
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/* Enable channel number tag. This bit will force the channel number (CHNB)
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* to be included in the LDCR register content.
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@ -991,8 +994,7 @@ static int sam_adc_setup(struct adc_dev_s *dev)
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/* Configure trigger mode and start conversion */
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sam_adc_trigger(priv);
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return OK;
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return sam_adc_trigger(priv);
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}
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/****************************************************************************
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@ -1009,10 +1011,10 @@ static void sam_adc_shutdown(struct adc_dev_s *dev)
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struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv;
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/* Disable ADC interrupts, both at the level of the ADC device and at the
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* level of the NVIC.
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* level of the AIC.
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*/
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sam_adc_putreg32(priv, SAM_ADC_IDR, ADC_TSD_INTS);
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sam_adc_putreg(priv, SAM_ADC_IDR, ADC_INT_ALL);
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up_disable_irq(SAM_IRQ_ADC);
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/* Then detach the ADC interrupt handler. */
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@ -1044,13 +1046,13 @@ static void sam_adc_rxint(struct adc_dev_s *dev, bool enable)
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{
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/* Enable channel interrupts */
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sam_adc_putreg32(priv, SAM_ADC_IER, SAMA5_CHAN_ENABLE);
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sam_adc_putreg(priv, SAM_ADC_IER, SAMA5_CHAN_ENABLE);
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}
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else
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{
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/* Disable channel interrupts */
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sam_adc_putreg32(priv, SAM_ADC_IDR, ADC_INT_EOCALL);
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sam_adc_putreg(priv, SAM_ADC_IDR, ADC_INT_EOCALL);
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}
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#endif
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}
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@ -1090,11 +1092,13 @@ static int sam_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
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****************************************************************************/
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#ifdef CONFIG_SAMA5_ADC_TIOATRIG
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static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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int channel)
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static int sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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int channel)
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{
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uint32_t div;
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uint32_t tcclks;
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uint32_t mode;
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int ret;
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/* Configure TC for a 1Hz frequency and trigger on RC compare. */
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@ -1113,7 +1117,7 @@ static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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TC_CMR_WAVSEL_UPRC | /* UP mode w/ trigger on RC Compare */
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TC_CMR_WAVE | /* Wave mode */
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TC_CMR_ACPA_CLEAR | /* RA Compare Effect on TIOA: Clear */
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TC_CMR_ACPC_SET); /* RC effect on TIOA: Set
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TC_CMR_ACPC_SET); /* RC effect on TIOA: Set */
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/* Now allocate and configure the channel */
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@ -1132,11 +1136,12 @@ static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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/* And start the timer */
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sam_tc_start(priv->tc);
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: sam_adc_settimer
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* Name: sam_adc_freetimer
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*
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* Description:
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* Configure a timer to trigger the sampling periodically
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@ -1144,8 +1149,7 @@ static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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****************************************************************************/
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#ifdef CONFIG_SAMA5_ADC_TIOATRIG
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static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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int channel)
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static void sam_adc_freetimer(struct sam_adc_s *priv)
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{
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/* Is a timer allocated? */
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@ -1168,16 +1172,17 @@ static void sam_adc_settimer(struct sam_adc_s *priv, uint32_t frequency,
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*
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****************************************************************************/
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static void sam_adc_trigger(struct sam_adc_s *priv)
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static int sam_adc_trigger(struct sam_adc_s *priv)
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{
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uint32_t reggal;
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uint32_t regval;
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int ret = OK;
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#if defined(CONFIG_SAMA5_ADC_SWTRIG)
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/* Configure the software trigger */
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regval = sam_adc_getreg(priv->dev, SAM_ADC_MR);
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_TRGSEL_MASK;
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sam_adc_putreg(priv->dev, SAM_ADC_MR, regval);
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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/* No trigger, only software trigger can start conversions */
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@ -1189,10 +1194,10 @@ static void sam_adc_trigger(struct sam_adc_s *priv)
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#elif defined(CONFIG_SAMA5_ADC_ADTRG)
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/* Configure the trigger via the external ADTRG signal */
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regval = sam_adc_getreg(priv->dev, SAM_ADC_MR);
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_TRGSEL_MASK;
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regval |= ADC_MR_TRGSEL_ADC_ADTRIG;
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sam_adc_putreg(priv->dev, SAM_ADC_MR, regval);
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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/* External trigger edge selection */
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@ -1215,24 +1220,30 @@ static void sam_adc_trigger(struct sam_adc_s *priv)
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/* Start the timer */
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#if defined(CONFIG_SAMA5_ADC_TIOA0TRIG)
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sam_adc_settimer(priv, CONFIG_SAMA5_ADC_TIOAFREQ, TC_CHAN0);
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ret = sam_adc_settimer(priv, CONFIG_SAMA5_ADC_TIOAFREQ, TC_CHAN0);
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#elif defined(CONFIG_SAMA5_ADC_TIOA1TRIG)
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sam_adc_settimer(priv, CONFIG_SAMA5_ADC_TIOAFREQ, TC_CHAN1);
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ret = sam_adc_settimer(priv, CONFIG_SAMA5_ADC_TIOAFREQ, TC_CHAN1);
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#elif defined(CONFIG_SAMA5_ADC_TIOA2TRIG)
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sam_adc_settimer(priv, CONFIG_SAMA5_ADC_TIOAFREQ, TC_CHAN2);
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ret = sam_adc_settimer(priv, CONFIG_SAMA5_ADC_TIOAFREQ, TC_CHAN2);
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#else
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# error Timer/counter for trigger not defined
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ret = -ENOSYS;
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#endif
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if (ret < 0)
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{
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adbg("ERROR: sam_adc_settimer failed: %d\n", ret);
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return ret;
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}
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/* Configure to trigger using Timer/counter 0, channel 1, 2, or 3.
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* NOTE: This trigger option depends on having properly configuer
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* timer/counter 0 to provide this output. That is done independently
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* the the timer/counter driver.
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*/
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/* Configure to trigger using Timer/counter 0, channel 1, 2, or 3.
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* NOTE: This trigger option depends on having properly configuer
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* timer/counter 0 to provide this output. That is done independently
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* the the timer/counter driver.
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*/
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/* Set TIOAn trigger where n=0, 1, or 2 */
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regval = sam_adc_getreg(priv->dev, SAM_ADC_MR);
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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regval &= ~ADC_MR_TRGSEL_MASK;
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#if defined(CONFIG_SAMA5_ADC_TIOA0TRIG)
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@ -1245,8 +1256,7 @@ static void sam_adc_trigger(struct sam_adc_s *priv)
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# error Timer/counter for trigger not defined
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#endif
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regval |= ADC_MR_TRGSEL_ADC_TRIG1;
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sam_adc_putreg(priv->dev, SAM_ADC_MR, regval);
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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/* Timer trigger edge selection */
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@ -1268,6 +1278,8 @@ static void sam_adc_trigger(struct sam_adc_s *priv)
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#else
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# error "Undefined ADC trigger"
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#endif
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return ret;
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}
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/****************************************************************************
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@ -1488,7 +1500,7 @@ static void sam_adc_analogchange(struct sam_adc_s *priv)
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/* Enable/disable the analog change feature */
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regval = sam_adc_getreg(priv->dev, SAM_ADC_MR);
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regval = sam_adc_getreg(priv, SAM_ADC_MR);
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#ifdef CONFIG_SAMA5_ADC_ANARCH
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/* Disable analog change: No analog change on channel switching: DIFF0,
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@ -1504,7 +1516,7 @@ static void sam_adc_analogchange(struct sam_adc_s *priv)
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regval &= ~ADC_MR_ANACH;
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#endif
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sam_adc_putreg(priv->dev, SAM_ADC_MR, regval);
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sam_adc_putreg(priv, SAM_ADC_MR, regval);
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}
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/****************************************************************************
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@ -1532,6 +1544,7 @@ static void sam_adc_setseqr(int chan, uint32_t *seqr1, uint32_t *seqr2, int seq)
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static void sam_adc_sequencer(struct sam_adc_s *priv)
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{
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#ifdef CONFIG_SAMA5_ADC_SEQUENCER
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uint32_t regval;
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uint32_t seqr1;
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uint32_t seqr2;
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int seq;
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@ -1783,11 +1796,12 @@ struct sam_adc_s *sam_adc_initialize(void)
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/* Initialize the ADC device data structure */
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sem_init(&priv->exclsem, 0, 1);
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priv->dev = &g_adcdev;
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#ifdef CONFIG_SAMA5_ADC_DMA
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/* Allocate a DMA channel */
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/* Allocate a DMA channel from DMAC1 */
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priv->dma = sam_dmachannel(dmac, DMA_FLAGS);
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priv->dma = sam_dmachannel(1, DMA_FLAGS);
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DEBUGASSERT(priv->dma);
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#endif
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@ -1858,7 +1872,7 @@ struct sam_adc_s *sam_adc_initialize(void)
|
||||
|
||||
/* Return a pointer to the device structure */
|
||||
|
||||
return &g_adcpriv;
|
||||
return priv;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -61,6 +61,7 @@
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "sam_periphclks.h"
|
||||
#include "chip/sam_pinmap.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "sam_pio.h"
|
||||
#include "sam_tc.h"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user