Merged in raiden00/nuttx_pe (pull request #772)
arch/arm/src/stm32/stm32_adc.c: refactor adc_reset. It should be easier to maintain this code if it's divided into smaller functions Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
GregoryN
parent
b7fa409fc4
commit
db799e857c
@ -2323,6 +2323,375 @@ static int adc_bind(FAR struct adc_dev_s *dev,
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return OK;
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}
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/****************************************************************************
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* Name: adc_watchdog_cfg
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****************************************************************************/
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#if defined(HAVE_IP_ADC_V2)
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static void adc_watchdog_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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/* Initialize the watchdog 1 threshold register */
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adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000);
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/* Enable the analog watchdog */
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clrbits = ADC_CFGR1_AWD1CH_MASK;
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setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL |
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(priv->r_chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT);
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/* Modify CFGR configuration */
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adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
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}
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#else
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static void adc_watchdog_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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/* Initialize the watchdog high threshold register */
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adc_putreg(priv, STM32_ADC_HTR_OFFSET, 0x00000fff);
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/* Initialize the watchdog low threshold register */
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adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000);
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clrbits = ADC_CR1_AWDCH_MASK;
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setbits = ADC_CR1_AWDEN | (priv->r_chanlist[0] << ADC_CR1_AWDCH_SHIFT);
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/* Modify CR1 configuration */
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adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits);
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}
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#endif
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/****************************************************************************
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* Name: adc_calibrate
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****************************************************************************/
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#if defined(HAVE_IP_ADC_V2)
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static void adc_calibrate(FAR struct stm32_dev_s *priv)
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{
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#if 0 /* Doesn't work */
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/* Calibrate the ADC */
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adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL);
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/* Wait for the calibration to complete */
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while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0);
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#else
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UNUSED(priv);
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#endif
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}
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#else
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static void adc_calibrate(FAR struct stm32_dev_s *priv)
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{
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/* TODO: adc_calibrate for ADC IPv1*/
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UNUSED(priv);
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}
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#endif
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/****************************************************************************
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* Name: adc_mode_cfg
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****************************************************************************/
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#ifdef HAVE_IP_ADC_V2
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static void adc_mode_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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/* Disable continuous mode and set align to right */
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clrbits = ADC_CFGR1_CONT | ADC_CFGR1_ALIGN;
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/* Disable external trigger for regular channels */
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clrbits |= ADC_CFGR1_EXTEN_MASK;
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setbits |= ADC_CFGR1_EXTEN_NONE;
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/* Set CFGR configuration */
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adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
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}
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#else
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static void adc_mode_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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#ifdef HAVE_BASIC_ADC
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/* Set independent mode */
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clrbits |= ADC_CR1_DUALMOD_MASK;
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setbits |= ADC_CR1_IND;
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#endif
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#ifdef ADC_HAVE_DMA
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if (priv->hasdma)
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{
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setbits |= ADC_CR1_SCAN;
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}
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#endif
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/* Set CR1 configuration */
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adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits);
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/* REVISIT: */
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#ifdef CONFIG_STM32_STM32L15XX
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/* Select the bank of channels A */
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adc_select_ch_bank(priv, false);
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# ifdef HAVE_ADC_POWERDOWN
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/* Disables power down during the delay phase */
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adc_power_down_idle(priv, false);
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adc_power_down_delay(priv, false);
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# endif
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/* Delay until the converted data has been read */
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adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD);
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#endif
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/* Disable continuous mode and set align to right */
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clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN;
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setbits = 0;
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/* Disable external trigger for regular channels */
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clrbits |= ADC_EXTREG_EXTEN_MASK;
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setbits |= ADC_EXTREG_EXTEN_NONE;
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/* Enable software trigger for regular channels
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* REVISIT: SWSTART must be set if no EXT trigger and basic ADC IPv1
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*/
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#ifdef CONFIG_STM32_STM32F37XX
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clrbits |= ADC_CR2_EXTSEL_MASK;
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setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */
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#endif
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/* Set CR2 configuration */
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adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits);
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}
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#endif
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/****************************************************************************
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* Name: adc_voltreg_cfg
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****************************************************************************/
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#if defined(HAVE_IP_ADC_V2)
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static void adc_voltreg_cfg(FAR struct stm32_dev_s *priv)
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{
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/* Set ADC voltage regulator to intermediate state */
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adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK,
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ADC_CR_ADVREGEN_INTER);
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/* Enable the ADC voltage regulator */
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adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK,
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ADC_CR_ADVREGEN_ENABLED);
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/* Wait for the ADC voltage regulator to startup */
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up_udelay(10);
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}
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#else
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static void adc_voltreg_cfg(FAR struct stm32_dev_s *priv)
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{
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/* Nothing to do here */
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UNUSED(priv);
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}
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#endif
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/****************************************************************************
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* Name: adc_voltreg_cfg
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****************************************************************************/
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static void adc_sampletime_cfg(FAR struct adc_dev_s *dev)
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{
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FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
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/* Initialize the same sample time for each ADC.
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* During sample cycles channel selection bits must remain unchanged.
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*/
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#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
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adc_sampletime_write((FAR struct stm32_adc_dev_s *)dev);
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#else
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adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT);
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adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
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# ifdef STM32_ADC_SMPR3_OFFSET
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adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, ADC_SMPR3_DEFAULT);
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# endif
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# ifdef STM32_ADC_SMPR0_OFFSET
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adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, ADC_SMPR0_DEFAULT);
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# endif
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#endif
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}
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/****************************************************************************
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* Name: adc_common_cfg
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****************************************************************************/
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#if defined(HAVE_IP_ADC_V2)
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static void adc_common_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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/* REVISIT: */
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clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG |
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ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN |
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ADC_CCR_TSEN | ADC_CCR_VBATEN;
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setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(0) | ADC_CCR_MDMA_DISABLED |
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ADC_CCR_CKMODE_ASYNCH;
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adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits);
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}
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#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)
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static void adc_common_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE;
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setbits = ADC_CCR_ADCPRE_DIV2;
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/* REVISIT: */
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#if !defined(CONFIG_STM32_STM32L15XX)
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clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS |
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ADC_CCR_DMA_MASK | ADC_CCR_VBATEN;
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setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED;
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#endif /* !defined(CONFIG_STM32_STM32L15XX) */
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adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits);
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}
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#else
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static void adc_common_cfg(FAR struct stm32_dev_s *priv)
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{
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/* Do nothing here */
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UNUSED(priv);
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}
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#endif
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#ifdef ADC_HAVE_DMA
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/****************************************************************************
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* Name: adc_dma_cfg
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****************************************************************************/
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#ifdef HAVE_IP_ADC_V2
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static void adc_dma_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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/* Set DMA mode */
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if (priv->dmacfg == 0)
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{
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/* One Shot Mode */
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clrbits |= ADC_CFGR1_DMACFG;
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}
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else
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{
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/* Circular Mode */
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setbits |= ADC_CFGR1_DMACFG;
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}
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/* Enable DMA */
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setbits |= ADC_CFGR1_DMAEN;
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/* Modify CFGR configuration */
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adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
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}
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#else
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static void adc_dma_cfg(FAR struct stm32_dev_s *priv)
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{
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uint32_t clrbits = 0;
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uint32_t setbits = 0;
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#ifdef ADC_HAVE_DMACFG
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/* Set DMA mode */
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if (priv->dmacfg == 0)
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{
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/* One Shot Mode */
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clrbits |= ADC_CR2_DDS;
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}
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else
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{
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/* Circular Mode */
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setbits |= ADC_CR2_DDS;
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}
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#endif
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/* Enable DMA */
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setbits |= ADC_CR2_DMA;
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/* Modify CR2 configuration */
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adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits);
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}
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#endif
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/****************************************************************************
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* Name: adc_dma_start
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****************************************************************************/
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static void adc_dma_start(FAR struct adc_dev_s *dev)
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{
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FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
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/* Stop and free DMA if it was started before */
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if (priv->dma != NULL)
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{
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stm32_dmastop(priv->dma);
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stm32_dmafree(priv->dma);
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}
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priv->dma = stm32_dmachannel(priv->dmachan);
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#ifndef CONFIG_STM32_ADC_NOIRQ
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stm32_dmasetup(priv->dma,
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priv->base + STM32_ADC_DR_OFFSET,
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(uint32_t)priv->r_dmabuffer,
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priv->rnchannels,
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ADC_DMA_CONTROL_WORD);
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stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false);
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#endif
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}
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#endif /* ADC_HAVE_DMA */
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/****************************************************************************
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* Name: adc_reset
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*
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@ -2330,6 +2699,9 @@ static int adc_bind(FAR struct adc_dev_s *dev,
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* Reset the ADC device. Called early to initialize the hardware.
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* This is called, before adc_setup() and on error conditions.
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*
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* TODO: Separate the configuration logic from the reset logic!
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* REVISIT: The ADC device should be configured in adc_setup not in adc_reset.
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*
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* Input Parameters:
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*
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* Returned Value:
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@ -2340,8 +2712,6 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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{
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FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
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irqstate_t flags;
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uint32_t clrbits;
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uint32_t setbits;
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#ifdef ADC_HAVE_TIMER
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int ret;
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#endif
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@ -2355,15 +2725,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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*/
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adc_enable_hsi(true);
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#endif
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#if defined(HAVE_IP_ADC_V2)
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/* Turn off the ADC so we can write the RCC bits */
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adc_enable(priv, false);
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#endif
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/* Only if this is the first initialzied ADC instance in the ADC block */
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@ -2387,216 +2754,25 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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adccmn_lock(priv, false);
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#endif
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#if defined(HAVE_IP_ADC_V2)
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/* Configure voltage regulator if present */
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/* Set voltage regular enable to intermediate state */
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adc_voltreg_cfg(priv);
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adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK,
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ADC_CR_ADVREGEN_INTER);
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/* Calibrate ADC - doesnt work for now */
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/* Enable the ADC voltage regulator */
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adc_calibrate(priv);
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adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADVREGEN_MASK,
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ADC_CR_ADVREGEN_ENABLED);
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/* Initialize the ADC watchdog */
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/* Wait for the ADC voltage regulator to startup */
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adc_watchdog_cfg(priv);
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up_udelay(10);
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/* Initialize the ADC sample time */
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#if 0 /* Doesn't work */
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adc_sampletime_cfg(dev);
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/* Calibrate the ADC */
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/* Set ADC working mode */
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adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL);
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/* Wait for the calibration to complete */
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while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0);
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#endif
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/* Initialize the watchdog 1 threshold register */
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adc_putreg(priv, STM32_ADC_TR1_OFFSET, 0x0fff0000);
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#else /* HAVE_IP_ADC_V1 */
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/* Initialize the watchdog high threshold register */
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adc_putreg(priv, STM32_ADC_HTR_OFFSET, 0x00000fff);
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/* Initialize the watchdog low threshold register */
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adc_putreg(priv, STM32_ADC_LTR_OFFSET, 0x00000000);
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#endif
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/* Initialize the same sample time for each ADC.
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* During sample cycles channel selection bits must remain unchanged.
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*/
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#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
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adc_sampletime_write((FAR struct stm32_adc_dev_s *)dev);
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#else
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adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT);
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adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
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# ifdef STM32_ADC_SMPR3_OFFSET
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adc_putreg(priv, STM32_ADC_SMPR3_OFFSET, ADC_SMPR3_DEFAULT);
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# endif
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# ifdef STM32_ADC_SMPR0_OFFSET
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adc_putreg(priv, STM32_ADC_SMPR0_OFFSET, ADC_SMPR0_DEFAULT);
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# endif
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#endif
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#ifdef HAVE_IP_ADC_V2
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/* Enable the analog watchdog */
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clrbits = ADC_CFGR1_AWD1CH_MASK;
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setbits = ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL |
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(priv->r_chanlist[0] << ADC_CFGR1_AWD1CH_SHIFT);
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# ifdef ADC_HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
{
|
||||
/* Set DMA mode */
|
||||
|
||||
if (priv->dmacfg == 0)
|
||||
{
|
||||
/* One Shot Mode */
|
||||
|
||||
clrbits |= ADC_CFGR1_DMACFG;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Circular Mode */
|
||||
|
||||
setbits |= ADC_CFGR1_DMACFG;
|
||||
}
|
||||
|
||||
/* Enable DMA */
|
||||
|
||||
setbits |= ADC_CFGR1_DMAEN;
|
||||
}
|
||||
# endif
|
||||
|
||||
/* Disable continuous mode and set align to right */
|
||||
|
||||
clrbits |= ADC_CFGR1_CONT | ADC_CFGR1_ALIGN;
|
||||
|
||||
/* Disable external trigger for regular channels */
|
||||
|
||||
clrbits |= ADC_CFGR1_EXTEN_MASK;
|
||||
setbits |= ADC_CFGR1_EXTEN_NONE;
|
||||
|
||||
/* Set CFGR configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
|
||||
|
||||
# ifndef CONFIG_STM32_ADC_NOIRQ
|
||||
/* Enable interrupt flags, but disable overrun interrupt */
|
||||
|
||||
clrbits = ADC_IER_OVR;
|
||||
setbits = ADC_IER_ALLINTS & ~ADC_IER_OVR;
|
||||
|
||||
/* Set IER configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
|
||||
# endif
|
||||
|
||||
#else /* HAVE_IP_ADC_V1 */
|
||||
|
||||
/* Enable the analog watchdog */
|
||||
|
||||
clrbits = ADC_CR1_AWDCH_MASK;
|
||||
setbits = ADC_CR1_AWDEN | (priv->r_chanlist[0] << ADC_CR1_AWDCH_SHIFT);
|
||||
|
||||
# ifdef HAVE_BASIC_ADC
|
||||
/* Set independent mode */
|
||||
|
||||
clrbits |= ADC_CR1_DUALMOD_MASK;
|
||||
setbits |= ADC_CR1_IND;
|
||||
# endif
|
||||
|
||||
# ifdef ADC_HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
{
|
||||
setbits |= ADC_CR1_SCAN;
|
||||
}
|
||||
# endif
|
||||
|
||||
/* Set CR1 configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_CR1_OFFSET, clrbits, setbits);
|
||||
|
||||
# ifdef CONFIG_STM32_STM32L15XX /* REVISIT: */
|
||||
|
||||
/* Select the bank of channels A */
|
||||
|
||||
adc_select_ch_bank(priv, false);
|
||||
|
||||
# ifdef HAVE_ADC_POWERDOWN
|
||||
/* Disables power down during the delay phase */
|
||||
|
||||
adc_power_down_idle(priv, false);
|
||||
adc_power_down_delay(priv, false);
|
||||
# endif
|
||||
|
||||
/* Delay until the converted data has been read */
|
||||
|
||||
adc_dels_after_conversion(priv, ADC_CR2_DELS_TILLRD);
|
||||
# endif
|
||||
|
||||
/* Disable continuous mode and set align to right */
|
||||
|
||||
clrbits = ADC_CR2_CONT | ADC_CR2_ALIGN;
|
||||
setbits = 0;
|
||||
|
||||
/* Disable external trigger for regular channels */
|
||||
|
||||
clrbits |= ADC_EXTREG_EXTEN_MASK;
|
||||
setbits |= ADC_EXTREG_EXTEN_NONE;
|
||||
|
||||
/* Enable software trigger for regular channels
|
||||
* REVISIT: SWSTART must be set if no EXT trigger and basic ADC IPv1
|
||||
*/
|
||||
|
||||
# ifdef CONFIG_STM32_STM32F37XX
|
||||
clrbits |= ADC_CR2_EXTSEL_MASK;
|
||||
setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */
|
||||
# endif
|
||||
|
||||
# ifdef ADC_HAVE_DMA
|
||||
if (priv->hasdma)
|
||||
{
|
||||
# ifdef ADC_HAVE_DMACFG
|
||||
/* Set DMA mode */
|
||||
|
||||
if (priv->dmacfg == 0)
|
||||
{
|
||||
/* One Shot Mode */
|
||||
|
||||
clrbits |= ADC_CR2_DDS;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Circular Mode */
|
||||
|
||||
setbits |= ADC_CR2_DDS;
|
||||
}
|
||||
# endif
|
||||
|
||||
/* Enable DMA */
|
||||
|
||||
setbits |= ADC_CR2_DMA;
|
||||
}
|
||||
# endif
|
||||
|
||||
/* Set CR2 configuration */
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_CR2_OFFSET, clrbits, setbits);
|
||||
|
||||
#endif
|
||||
adc_mode_cfg(priv);
|
||||
|
||||
/* Configuration of the channel conversions */
|
||||
|
||||
@ -2614,59 +2790,23 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ADC CCR configuration
|
||||
* REVISIT: simplify this
|
||||
*/
|
||||
/* ADC common register configuration */
|
||||
|
||||
#if defined(HAVE_IP_ADC_V2)
|
||||
clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG |
|
||||
ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN |
|
||||
ADC_CCR_TSEN | ADC_CCR_VBATEN;
|
||||
setbits = ADC_CCR_DUAL_IND | ADC_CCR_DELAY(0) | ADC_CCR_MDMA_DISABLED |
|
||||
ADC_CCR_CKMODE_ASYNCH;
|
||||
|
||||
adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits);
|
||||
|
||||
#elif defined(HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)
|
||||
clrbits = ADC_CCR_ADCPRE_MASK | ADC_CCR_TSVREFE;
|
||||
setbits = ADC_CCR_ADCPRE_DIV2;
|
||||
|
||||
# if !defined(CONFIG_STM32_STM32L15XX)
|
||||
clrbits |= ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS |
|
||||
ADC_CCR_DMA_MASK | ADC_CCR_VBATEN;
|
||||
setbits |= ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED;
|
||||
# endif /* !defined(CONFIG_STM32_STM32L15XX) */
|
||||
|
||||
adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits);
|
||||
#endif
|
||||
adc_common_cfg(priv);
|
||||
|
||||
#ifdef ADC_HAVE_DMA
|
||||
|
||||
/* Enable DMA */
|
||||
/* Configure ADC DMA if enabled */
|
||||
|
||||
if (priv->hasdma)
|
||||
{
|
||||
/* Stop and free DMA if it was started before */
|
||||
/* Configure ADC DMA */
|
||||
|
||||
if (priv->dma != NULL)
|
||||
{
|
||||
stm32_dmastop(priv->dma);
|
||||
stm32_dmafree(priv->dma);
|
||||
}
|
||||
adc_dma_cfg(priv);
|
||||
|
||||
priv->dma = stm32_dmachannel(priv->dmachan);
|
||||
/* Start ADC DMA */
|
||||
|
||||
# ifndef CONFIG_STM32_ADC_NOIRQ
|
||||
stm32_dmasetup(priv->dma,
|
||||
priv->base + STM32_ADC_DR_OFFSET,
|
||||
(uint32_t)priv->r_dmabuffer,
|
||||
priv->rnchannels,
|
||||
ADC_DMA_CONTROL_WORD);
|
||||
|
||||
stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false);
|
||||
# endif
|
||||
adc_dma_start(dev);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_ADC_RESOLUTION
|
||||
@ -2675,12 +2815,6 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
(void)adc_resolution_set(dev, priv->resolution);
|
||||
#endif
|
||||
|
||||
/* Enable ADC */
|
||||
|
||||
adc_enable(priv, true);
|
||||
|
||||
/* REVISIT: events configuration should be before adc_enable ?? */
|
||||
|
||||
#ifdef ADC_HAVE_EXTCFG
|
||||
/* Configure external event for regular group */
|
||||
|
||||
@ -2693,6 +2827,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
adc_jextcfg_set(dev, priv->jextcfg);
|
||||
#endif
|
||||
|
||||
/* Enable ADC */
|
||||
|
||||
adc_enable(priv, true);
|
||||
|
||||
#ifdef ADC_HAVE_TIMER
|
||||
if (priv->tbase != 0)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user