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arch/arm/src/stm32f0l0/hardware: Fix some cosmetic naming problems associated with chip/ vs hardware/ sub-directories.

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This commit is contained in:
Gregory Nutt 2019-05-27 08:03:46 -06:00
parent 2c3ca9d756
commit dbb40e5fe7
38 changed files with 106 additions and 106 deletions
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6
arch/arm/src/stm32f0l0/hardware/stm32_adc.h
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@ -34,8 +34,8 @@
*
********************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H
/********************************************************************************
* Included Files
@ -268,4 +268,4 @@
# define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_ADC_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_can.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H
/************************************************************************************
* Included Files
@ -466,4 +466,4 @@
#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */
#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CAN_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_comp.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H
/************************************************************************************
* Included Files
@ -135,4 +135,4 @@
#define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */
#define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_COMP_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_crc.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H
/************************************************************************************
* Included Files
@ -87,4 +87,4 @@
# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */
#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRC_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_crs.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H
/************************************************************************************
* Pre-processor Definitions
@ -112,4 +112,4 @@
#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */
#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_CRS_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_dac.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H
/************************************************************************************
* Included Files
@ -215,4 +215,4 @@
#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */
#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DAC_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
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@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H
/************************************************************************************
* Pre-processor Definitions
@ -550,4 +550,4 @@
# error "Unknown DMA channel assignments"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMA_V1_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_dmamux.h
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@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMAMUX_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H
/************************************************************************************
* Included Files
@ -159,4 +159,4 @@
# error "Unsupported STM32 M0 sub family"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DMAMUX_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_DMAMUX_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_exti.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H
/************************************************************************************
* Included Files
@ -54,4 +54,4 @@
# error "Unrecognized STM32 M0 EXTI"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_EXTI_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_flash.h
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@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H
/************************************************************************************
* Included Files
@ -53,4 +53,4 @@
# error "Unsupported STM32 M0 FLASH"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_FLASH_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H
/************************************************************************************
* Pre-processor Definitions
@ -355,4 +355,4 @@
#define GPIO_BRR(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_GPIO_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H
/************************************************************************************
* Pre-processor Definitions
@ -235,4 +235,4 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_I2C_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H
/************************************************************************************
* Included Files
@ -55,4 +55,4 @@
# error "Unsupported STM32 M0 memory map"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_MEMORYMAP_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H
/************************************************************************************
* Included Files
@ -54,4 +54,4 @@
# error "Unsupported STM32 M0 RCC"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RCC_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_rng.h
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@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32_RNG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H
/************************************************************************************
* Included Files
@ -75,4 +75,4 @@
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
#endif /* __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32_RNG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RNG_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H
/************************************************************************************
* Pre-processor Definitions
@ -321,4 +321,4 @@
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_RTCC_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_spi.h
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@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H
/************************************************************************************
* Included Files
@ -269,4 +269,4 @@
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SPI_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
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@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H
/****************************************************************************************************
* Included Files
@ -54,4 +54,4 @@
# error "Unsupported STM32 M0 SYSCFG"
#endif
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_SYSCFG_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_tim.h
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@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H
/****************************************************************************************************
* Pre-processor Definitions
@ -49,4 +49,4 @@
/* Register Bitfield Definitions ********************************************************************/
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_TIM_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_uart.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H
/************************************************************************************
* Included Files
@ -52,4 +52,4 @@
# error "Unsupported STM32 M0 USART"
#endif
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_uart_v1.h
View File

@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V1_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V1_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V1_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V1_H
/************************************************************************************
* Included Files
@ -313,4 +313,4 @@
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_V1_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_V1_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_uart_v2.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V2_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_V2_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V2_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_UART_V2_H
/************************************************************************************
* Included Files
@ -360,4 +360,4 @@
# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_V2_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_UART_V2_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
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@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H
/************************************************************************************
* Included Files
@ -261,4 +261,4 @@
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
#endif /* CONFIG_STM32F0L0_HAVE_USBDEV */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_USBDEV_H */

6
arch/arm/src/stm32f0l0/hardware/stm32_wdt.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H
/************************************************************************************
* Included Files
@ -139,4 +139,4 @@
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_WDG_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
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@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H
/************************************************************************************
* Included Files
@ -133,4 +133,4 @@
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F05X_PINMAP_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h
View File

@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
@ -154,4 +154,4 @@
#define STM32_SCS_BASE 0xe000e000
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
View File

@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H
/************************************************************************************
* Included Files
@ -397,4 +397,4 @@
#define GPIO_USB_NOE (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F07X_PINMAP_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
View File

@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H
/************************************************************************************
* Included Files
@ -427,4 +427,4 @@
#define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_USART8_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F09X_PINMAP_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h
View File

@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H
/************************************************************************************
* Included Files
@ -128,4 +128,4 @@
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32_EXTI_MASK
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_EXTI_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H
/************************************************************************************
* Included Files
@ -105,4 +105,4 @@
#define FLASH_OBR_ /* To be provided */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_FLASH_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
View File

@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H
/************************************************************************************
* Pre-processor Definitions
@ -393,4 +393,4 @@
#define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */
#define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT)
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_RCC_H */

6
arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
View File

@ -34,8 +34,8 @@
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H
/****************************************************************************************************
* Included Files
@ -388,4 +388,4 @@
#define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
#define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_SYSCFG_H */

6
arch/arm/src/stm32f0l0/hardware/stm32g0_exti.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32G0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32G0_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H
/************************************************************************************
* Included Files
@ -100,4 +100,4 @@
/* TODO */
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32G0_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32G0_EXTI_H */

2
arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32/hardware/stm32g0_flash.h
* arch/arm/src/stm32f0l0/hardware/stm32g0_flash.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

2
arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32g0_pwr.h
* arch/arm/src/stm32f0l0/hardware/stm32g0_pwr.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

6
arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h
View File

@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H
#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H
#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H
/************************************************************************************
* Included Files
@ -126,4 +126,4 @@
#define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PR_MASK STM32_EXTI_MASK
#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H */
#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_EXTI_H */

2
arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32/hardware/stm32l0_flash.h
* arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

2
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32l0_pwr.h
* arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>