diff --git a/arch/risc-v/src/common/riscv_addrenv.c b/arch/risc-v/src/common/riscv_addrenv.c
index 7d3fc951ef..d24ffb9603 100644
--- a/arch/risc-v/src/common/riscv_addrenv.c
+++ b/arch/risc-v/src/common/riscv_addrenv.c
@@ -89,6 +89,11 @@
 
 #define ADDRENV_VBASE       (CONFIG_ARCH_DATA_VBASE)
 
+/* Make sure the address environment virtual address boundary is valid */
+
+static_assert((ADDRENV_VBASE & RV_MMU_SECTION_ALIGN) == 0,
+              "Addrenv start address is not aligned to section boundary");
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
diff --git a/arch/risc-v/src/common/riscv_mmu.h b/arch/risc-v/src/common/riscv_mmu.h
index 9b4173597d..e2b0fd3132 100644
--- a/arch/risc-v/src/common/riscv_mmu.h
+++ b/arch/risc-v/src/common/riscv_mmu.h
@@ -107,6 +107,10 @@
 #define RV_MMU_L1_PAGE_SIZE     (0x40000000) /* 1G */
 #define RV_MMU_L2_PAGE_SIZE     (0x200000)   /* 2M */
 #define RV_MMU_L3_PAGE_SIZE     (0x1000)     /* 4K */
+
+/* Minimum alignment requirement for any section of memory is 2MB */
+
+#define RV_MMU_SECTION_ALIGN    (RV_MMU_L2_PAGE_SIZE)
 #else
 #error "Unsupported RISC-V MMU implementation selected"
 #endif /* CONFIG_ARCH_MMU_TYPE_SV39 */
diff --git a/arch/risc-v/src/mpfs/mpfs_mm_init.c b/arch/risc-v/src/mpfs/mpfs_mm_init.c
index cc5cf5eab3..6a3830a4fd 100644
--- a/arch/risc-v/src/mpfs/mpfs_mm_init.c
+++ b/arch/risc-v/src/mpfs/mpfs_mm_init.c
@@ -172,7 +172,7 @@ static void map_region(uintptr_t paddr, uintptr_t vaddr, size_t size,
           /* No, allocate 1 page, this must not fail */
 
           l3pbase = slab_alloc();
-          DEBUGASSERT(l3pbase);
+          ASSERT(l3pbase);
 
           /* Map it to the L3 table */
 
@@ -205,6 +205,15 @@ static void map_region(uintptr_t paddr, uintptr_t vaddr, size_t size,
 
 void mpfs_kernel_mappings(void)
 {
+  /* Ensure the sections are aligned properly, requirement is 2MB due to the
+   * L3 page table size (one table maps 2MB of memory). This mapping cannot
+   * handle unaligned L3 sections.
+   */
+
+  ASSERT((KFLASH_START & RV_MMU_SECTION_ALIGN) == 0);
+  ASSERT((KSRAM_START & RV_MMU_SECTION_ALIGN) == 0);
+  ASSERT((PGPOOL_START & RV_MMU_SECTION_ALIGN) == 0);
+
   /* Initialize slab allocator for L3 page tables */
 
   slab_init(PGT_L3_PBASE);