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SAMA5 OHCI: When UPLL drives OHCI the logically correct divider of 10 does not work; But a divider of 5 does. Why?

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This commit is contained in:
Gregory Nutt 2013-09-19 16:10:46 -06:00
parent 92617fade5
commit dbf07d6d01
3 changed files with 16 additions and 2 deletions
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3
ChangeLog
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@ -5594,4 +5594,7 @@
Correct some inconsistencies in the way that USB configuration
settings are used. This caused compilation errors in SAMA5 OHCI
when USB debug was ON but USB host tracing was off (2013-9-19).
* nuttx/arch/arm/src/sama5/sam_clockconfig.c: When 480MHz UPLL
is used to drive OHCI, it should have a divider of 10. However,
that does not work. A divider of 5 does. Why? (2013-9-19).

9
arch/arm/src/sama5/sam_clockconfig.c
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@ -397,9 +397,16 @@ static inline void sam_usbclockconfig(void)
/* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
* selected.
*
* REVISIT: The divisor of 10 produces a rate that is too high. Division
* by 5, however, seems to work just fine. No idea why?
*/
regval |= PMC_USB_USBDIV(9);
#if 1 /* REVISIT */
regval |= PMC_USB_USBDIV(4); /* Division by 5 */
#else
regval |= PMC_USB_USBDIV(9); /* Division by 10 */
#endif
putreg32(regval, SAM_PMC_USB);
#else /* BOARD_USE_UPLL */

6
configs/sama5d3x-ek/include/board_384mhz.h
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@ -136,7 +136,11 @@
# undef BOARD_USE_UPLL /* Use PLLA as source clock */
# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA /* Input is PLLACK */
# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */
# if 1 /* REVISIT */
# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */
# else
# define BOARD_OHCI_DIVIDER (15) /* Divided by 16 */
# endif
#endif
/* Resulting frequencies */