Coding style fixes. Run every new file through tools/nxstyle to assure that it is close to the NuttX coding standard.
This commit is contained in:
Gregory Nutt
parent
64c918783b
commit
dc09d7018b
@ -2,7 +2,7 @@
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* boards/arm/lpc17xx_40xx/lx_cpu/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -52,9 +52,11 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here
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* because the including C file may not have that file in its include path.
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/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included
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* here because the including C file may not have that file in its include path.
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
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@ -163,11 +165,11 @@
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#define GPIO_USB_PWRD (GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN10)
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/*
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#define GPIO_USB_PPWR
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#define GPIO_USB_PWRD
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#define GPIO_USB_OVRCR
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*/
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#if 0
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# define GPIO_USB_PPWR
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# define GPIO_USB_PWRD
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# define GPIO_USB_OVRCR
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#endif
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/* FLASH Configuration */
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@ -252,9 +254,10 @@
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#define BOARD_NADDR 16
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#define BOARD_NDATA 32
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//#define BOARD_EMC_CONFIG_BY_LOADER 1
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/* #define BOARD_EMC_CONFIG_BY_LOADER 1 */
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/* LED definitions ******************************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
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* any way. The following definitions are used to access individual LEDs.
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*
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@ -284,7 +287,7 @@
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#define LED_HEAPALLOCATE 1 /* ON OFF OFF OFF */
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#define LED_IRQSENABLED 2 /* OFF ON OFF OFF */
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#define LED_STACKCREATED 3 /* ON ON OFF OFF */
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#define LED_INIRQ 4 /* LED3 glows, on while in interrupt */
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#define LED_INIRQ 4 /* LED3 glows, on while in interrupt */
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#define LED_SIGNAL 4 /* LED3 glows, on while in signal handler */
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#define LED_ASSERTION 4 /* LED3 glows, on while in assertion */
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#define LED_PANIC 4 /* LED3 Flashes at 2Hz */
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@ -292,6 +295,7 @@
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* OFF while sleeping */
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/* Button definitions ***************************************************************/
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/* The LX_CPU supports several buttons. All must be pulled up by the LX_CPU.
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* When closed, the pins will be pulled to ground. So the buttons will read "1"
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* when open and "0" when closed. All except USER1 are capable of generating
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@ -313,7 +317,6 @@
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* release).
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*/
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#define BOARD_BUTTON_USER1 0
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#define BOARD_BUTTON_USER2 1
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#define BOARD_BUTTON_USER3 2
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@ -448,20 +451,21 @@
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/* XPT2046 Touchscreen:
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*
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/* -------------- -------------------- ------------ --------------------------------
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* -------------- -------------------- ------------ --------------------------------
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* XTPT2046 Module Module LX_CPU LED
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* Signal Connector Connector
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* -------------- -------------------- ------------ ---------------------------------
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* Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ
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* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED)
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* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP
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* LED)
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* Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY
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* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin)
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* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up
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* LED and SD CD pin)
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* Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV)
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* Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1
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* -------------- -------------------- ------------ ---------------------------------
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*/
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#define GPIO_SSP1_MISO GPIO_SSP1_MISO_3
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#define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2
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#define GPIO_SSP1_SCK GPIO_SSP1_SCK_2
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@ -473,7 +477,8 @@
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#define UL_DRV_SYSLESS_IRQ LPC17_40_IRQ_UART1
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#define UL_DRV_SYSLESS_MY_ADR_DEFAULT 3
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typedef struct nuttx_ulan_chip_data {
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struct nuttx_ulan_chip_data_s
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{
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const char *chip;
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int my_adr;
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int baud;
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@ -482,6 +487,6 @@ typedef struct nuttx_ulan_chip_data {
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int port;
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};
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int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data *chip_data);
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int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data_s *chip_data);
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#endif /* __BOARDS_ARM_LX_CPU_INCLUDE_BOARD_H */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -67,7 +67,7 @@
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* arg - The boardctl() argument is passed to the board_app_initialize()
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* implementation without modification. The argument has no
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* meaning to NuttX; the meaning of the argument is a contract
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* between the board-specific initalization logic and the
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* between the board-specific initialization logic and the
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* matching application logic. The value cold be such things as a
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* mode enumeration value, a set of DIP switch switch settings, a
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* pointer to configuration data read from a file or serial FLASH,
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@ -1,7 +1,7 @@
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/****************************************************************************
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* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c
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*
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* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -1,7 +1,7 @@
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/************************************************************************************
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* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c
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*
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* Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -51,14 +51,6 @@
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#include "lx_cpu.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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@ -67,9 +59,9 @@
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* Name: lpc17_40_boardinitialize
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*
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* Description:
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* All LPC17xx architectures must provide the following entry point. This entry point
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* is called early in the intitialization -- after all memory has been configured
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* and mapped but before any devices have been initialized.
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* All LPC17xx architectures must provide the following entry point. This entry
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* point is called early in the initialization -- after all memory has been
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* configured and mapped but before any devices have been initialized.
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*
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************************************************************************************/
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@ -1,7 +1,7 @@
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/****************************************************************************
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* config/lx_cpu/src/lpc17_40_bringup.c
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*
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* Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -62,6 +62,7 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#define NSH_HAVE_MMCSD 1
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@ -73,7 +74,8 @@
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/* MMC/SD support */
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#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO)
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#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && \
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!defined(CONFIG_MMCD_SDIO)
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# undef NSH_HAVE_MMCSD
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#endif
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@ -83,7 +85,9 @@
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# undef NSH_HAVE_MMCSD
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#endif
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/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */
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/* MMC/SD support requires that an SPI support is enabled and an SPI port
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* is selected.
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*/
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#ifdef NSH_HAVE_MMCSD
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# if !defined(CONFIG_NSH_MMCSDSLOTNO)
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@ -99,9 +103,9 @@
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# endif
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#endif
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/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also
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* used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper
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* on board that enables the CD pin.
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/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It
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* is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected.
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* There is a jumper on board that enables the CD pin.
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*/
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#ifdef NSH_HAVE_MMCSD
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@ -180,7 +184,7 @@ static int nsh_waiter(int argc, char *argv[])
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struct usbhost_hubport_s *hport;
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syslog(LOG_INFO, "nsh_waiter: Running\n");
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for (;;)
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for (; ; )
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{
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/* Wait for the device to change state */
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@ -252,9 +256,8 @@ static int nsh_sdinitialize(void)
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* inserted or deleted.
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*/
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(void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL);
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up_enable_irq(LPC17_40_IRQ_P0p13);
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(void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL);
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up_enable_irq(LPC17_40_IRQ_P0p13);
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#endif
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#endif
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@ -321,7 +324,9 @@ static int nsh_usbhostinitialize(void)
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ret = usbhost_msc_initialize();
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if (ret != OK)
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{
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syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret);
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syslog(LOG_ERR,
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"ERROR: Failed to register the mass storage class: %d\n",
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ret);
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}
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#endif
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@ -331,7 +336,9 @@ static int nsh_usbhostinitialize(void)
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ret = usbhost_cdcacm_initialize();
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if (ret != OK)
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{
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syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
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syslog(LOG_ERR,
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"ERROR: Failed to register the CDC/ACM serial class: %d\n",
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ret);
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}
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#endif
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@ -6,7 +6,7 @@
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*
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* Based on boards/olimex-lpc1766stk/src/lpc17_40_can.c
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*
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* Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2012, 2016, 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -61,6 +61,7 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#define CAN_PORT1 1
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@ -71,7 +72,7 @@
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************************************************************************************/
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/************************************************************************************
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* Name: zkit_can_setup
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* Name: lx_cpu_can_setup
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*
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* Description:
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* Initialize CAN and register the CAN device
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@ -1,11 +1,10 @@
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/*****************************************************************************
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* boards/pnev5180b/src/lpc17_40_composite.c
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* Configure and register CDC-ACM and CDC-ECM
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Michael Jung <mijung@gmx.net>
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*
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* Configure and register CDC-ACM and CDC-ECM
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -64,9 +63,8 @@
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int board_composite_initialize(int port)
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{
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syslog(LOG_INFO, "board_composite_initialize(port: %d)\n", port);
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return OK;
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syslog(LOG_INFO, "board_composite_initialize(port: %d)\n", port);
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return OK;
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}
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/*****************************************************************************
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@ -1,8 +1,7 @@
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/************************************************************************************
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* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c
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* arch/arm/src/board/lpc17_40_sdraminitialize.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -54,10 +53,15 @@
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#include "lx_cpu.h"
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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void lx_cpu_fpga_initialize(void)
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{
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uint32_t regval;
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/* Initialze EMC for FPGA */
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/* Initialize EMC for FPGA */
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lpc17_40_configgpio(BOARD_XC_PROGRAM_PIN);
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lpc17_40_configgpio(BOARD_XC_DONE_PIN);
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@ -73,6 +77,7 @@ void lx_cpu_fpga_initialize(void)
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* Buffer: disabled
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* Write protection: disabled
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*/
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putreg32(0x00000002, LPC17_40_EMC_STATICCONFIG0);
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/* Delays - not measured at this point
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@ -81,11 +86,13 @@ void lx_cpu_fpga_initialize(void)
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* Write: 33 cycles
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* Turnaround: 2 cycles (cca. 28 ns)
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*/
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putreg32(0x1F, LPC17_40_EMC_STATICWAITRD0);
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putreg32(0x1F, LPC17_40_EMC_STATICWAITWR0);
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putreg32(0x1f, LPC17_40_EMC_STATICWAITRD0);
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putreg32(0x1f, LPC17_40_EMC_STATICWAITWR0);
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putreg32(0x01, LPC17_40_EMC_STATICWAITTURN0);
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/* Shift addresses by 2 (32-bit bus) */
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regval = getreg32(LPC17_40_SYSCON_SCS);
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regval &= ~SYSCON_SCS_EMCSC;
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putreg32(regval, LPC17_40_SYSCON_SCS);
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@ -1,8 +1,7 @@
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/****************************************************************************
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* config/lx_cpu/src/lpc17_40_nsh.c
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* arch/arm/src/board/lpc17_40_nsh.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -60,6 +59,7 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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#define NSH_HAVE_MMCSD 1
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@ -71,7 +71,8 @@
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/* MMC/SD support */
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#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO)
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#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && \
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!defined(CONFIG_MMCD_SDIO)
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# undef NSH_HAVE_MMCSD
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#endif
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@ -81,7 +82,9 @@
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# undef NSH_HAVE_MMCSD
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#endif
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/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */
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/* MMC/SD support requires that an SPI support is enabled and an SPI port is
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* selected.
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*/
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#ifdef NSH_HAVE_MMCSD
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# if !defined(CONFIG_NSH_MMCSDSLOTNO)
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@ -97,9 +100,9 @@
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# endif
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#endif
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/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also
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* used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper
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* on board that enables the CD pin.
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/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It
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* is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected.
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* There is a jumper on board that enables the CD pin.
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*/
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#ifdef NSH_HAVE_MMCSD
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@ -178,12 +181,13 @@ static int nsh_waiter(int argc, char *argv[])
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struct usbhost_hubport_s *hport;
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syslog(LOG_INFO, "nsh_waiter: Running\n");
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for (;;)
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for (; ; )
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{
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/* Wait for the device to change state */
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DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
|
||||
syslog(LOG_INFO, "nsh_waiter: %s\n", hport->connected ? "connected" : "disconnected");
|
||||
syslog(LOG_INFO, "nsh_waiter: %s\n",
|
||||
hport->connected ? "connected" : "disconnected");
|
||||
|
||||
/* Did we just become connected? */
|
||||
|
||||
@ -244,15 +248,13 @@ static int nsh_sdinitialize(void)
|
||||
|
||||
lpc17_40_configgpio(GPIO_SD_CD);
|
||||
|
||||
#if NSH_HAVE_MMCSD_CDINT
|
||||
/* Attach an interrupt handler to get notifications when a card is
|
||||
* inserted or deleted.
|
||||
*/
|
||||
|
||||
#if NSH_HAVE_MMCSD_CDINT
|
||||
|
||||
(void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt);
|
||||
up_enable_irq(LPC17_40_IRQ_P0p13);
|
||||
|
||||
(void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt);
|
||||
up_enable_irq(LPC17_40_IRQ_P0p13);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -319,7 +321,9 @@ static int nsh_usbhostinitialize(void)
|
||||
ret = usbhost_msc_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret);
|
||||
syslog(LOG_ERR,
|
||||
"ERROR: Failed to register the mass storage class: %d\n",
|
||||
ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -329,7 +333,9 @@ static int nsh_usbhostinitialize(void)
|
||||
ret = usbhost_cdcacm_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
|
||||
syslog(LOG_ERR,
|
||||
"ERROR: Failed to register the CDC/ACM serial class: %d\n",
|
||||
ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Author: Philippe Coval <p.coval@samsung.com>
|
||||
* Author: Philippe Coval <p.coval@samsung.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -46,7 +46,7 @@
|
||||
#ifdef CONFIG_BOARDCTL_RESET
|
||||
|
||||
/****************************************************************************
|
||||
* Public functions
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
/************************************************************************************
|
||||
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c
|
||||
* arch/arm/src/board/lpc17_40_sdraminitialize.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -59,8 +58,8 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided), or
|
||||
* LPC17_40_CCLK / 2 as determined by settings in the board.h header file.
|
||||
/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided)
|
||||
* or LPC17_40_CCLK / 2 as determined by settings in the board.h header file.
|
||||
*
|
||||
* For example:
|
||||
* LPC17_40_CCLCK = 120,000,000
|
||||
@ -99,12 +98,14 @@
|
||||
|
||||
#define SDRAM_BASE 0xa0000000 /* CS0 */
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static volatile uint32_t lx_cpu_ringosccount[2] = {0,0};
|
||||
static volatile uint32_t lx_cpu_ringosccount[2] =
|
||||
{
|
||||
0, 0
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
@ -129,9 +130,13 @@ static int lx_cpu_running_from_sdram(void)
|
||||
|
||||
if (((uint32_t)lx_cpu_running_from_sdram >= LPC17_40_EXTDRAM_CS0) &&
|
||||
((uint32_t)lx_cpu_running_from_sdram < extdram_end))
|
||||
return 1;
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* SDRAM code based on NXP application notes and emc_sdram.c example */
|
||||
@ -147,17 +152,20 @@ static int lx_cpu_running_from_sdram(void)
|
||||
* 1 if test passed, otherwise 0
|
||||
*
|
||||
****************************************************************************/
|
||||
static uint32_t lx_cpu_sdram_test( void )
|
||||
|
||||
static uint32_t lx_cpu_sdram_test(void)
|
||||
{
|
||||
volatile uint32_t *wr_ptr;
|
||||
volatile uint16_t *short_wr_ptr;
|
||||
uint32_t data;
|
||||
uint32_t i, j;
|
||||
uint32_t i;
|
||||
uint32_t j;
|
||||
|
||||
wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0;
|
||||
short_wr_ptr = (uint16_t *)wr_ptr;
|
||||
|
||||
/* 16 bit write */
|
||||
|
||||
for (i = 0; i < 64; i++)
|
||||
{
|
||||
for (j = 0; j < 0x100; j++)
|
||||
@ -168,19 +176,22 @@ static uint32_t lx_cpu_sdram_test( void )
|
||||
}
|
||||
|
||||
/* Verifying */
|
||||
|
||||
wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0;
|
||||
for (i = 0; i < 64; i++)
|
||||
{
|
||||
for (j = 0; j < 0x100; j++)
|
||||
{
|
||||
data = *wr_ptr;
|
||||
if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF)))
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
if (data != (((((i + j) + 1) & 0xffff) << 16) | ((i + j) & 0xffff)))
|
||||
{
|
||||
return 0x0;
|
||||
}
|
||||
|
||||
wr_ptr++;
|
||||
}
|
||||
}
|
||||
|
||||
return 0x1;
|
||||
}
|
||||
|
||||
@ -194,55 +205,65 @@ static uint32_t lx_cpu_sdram_test( void )
|
||||
* 1 if test passed, otherwise 0
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t lx_cpu_sdram_find_cmddly(void)
|
||||
{
|
||||
uint32_t cmddly, cmddlystart, cmddlyend, regval;
|
||||
uint32_t ppass = 0x0, pass = 0x0;
|
||||
uint32_t cmddly;
|
||||
uint32_t cmddlystart;
|
||||
uint32_t cmddlyend;
|
||||
uint32_t regval;
|
||||
uint32_t ppass = 0x0;
|
||||
uint32_t pass = 0x0;
|
||||
|
||||
cmddly = 0x0;
|
||||
cmddlystart = cmddlyend = 0xFF;
|
||||
cmddlystart = cmddlyend = 0xff;
|
||||
|
||||
while (cmddly < 32)
|
||||
{
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
|
||||
{
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
|
||||
|
||||
if (lx_cpu_sdram_test() == 0x1)
|
||||
{
|
||||
/* Test passed */
|
||||
if (cmddlystart == 0xFF)
|
||||
{
|
||||
cmddlystart = cmddly;
|
||||
}
|
||||
ppass = 0x1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Test failed */
|
||||
if (ppass == 1)
|
||||
{
|
||||
cmddlyend = cmddly;
|
||||
pass = 0x1;
|
||||
ppass = 0x0;
|
||||
}
|
||||
}
|
||||
if (lx_cpu_sdram_test() == 0x1)
|
||||
{
|
||||
/* Test passed */
|
||||
|
||||
/* Try next value */
|
||||
cmddly++;
|
||||
if (cmddlystart == 0xff)
|
||||
{
|
||||
cmddlystart = cmddly;
|
||||
}
|
||||
|
||||
ppass = 0x1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Test failed */
|
||||
|
||||
if (ppass == 1)
|
||||
{
|
||||
cmddlyend = cmddly;
|
||||
pass = 0x1;
|
||||
ppass = 0x0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Try next value */
|
||||
|
||||
cmddly++;
|
||||
}
|
||||
|
||||
/* If the test passed, the we can use the average of the min and max
|
||||
* values to get an optimal DQSIN delay
|
||||
*/
|
||||
|
||||
if (pass == 0x1)
|
||||
{
|
||||
cmddly = (cmddlystart + cmddlyend) / 2;
|
||||
}
|
||||
else if (ppass == 0x1)
|
||||
{
|
||||
cmddly = (cmddlystart + 0x1F) / 2;
|
||||
cmddly = (cmddlystart + 0x1f) / 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -251,7 +272,8 @@ static uint32_t lx_cpu_sdram_find_cmddly(void)
|
||||
*/
|
||||
cmddly = 0x10;
|
||||
}
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
|
||||
@ -269,13 +291,18 @@ static uint32_t lx_cpu_sdram_find_cmddly(void)
|
||||
* 1 if test passed, otherwise 0
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t lx_cpu_sdram_find_fbclkdly(void)
|
||||
{
|
||||
uint32_t fbclkdly, fbclkdlystart, fbclkdlyend, regval;
|
||||
uint32_t ppass = 0x0, pass = 0x0;
|
||||
uint32_t fbclkdly;
|
||||
uint32_t fbclkdlystart;
|
||||
uint32_t fbclkdlyend;
|
||||
uint32_t regval;
|
||||
uint32_t ppass = 0x0;
|
||||
uint32_t pass = 0x0;
|
||||
|
||||
fbclkdly = 0x0;
|
||||
fbclkdlystart = fbclkdlyend = 0xFF;
|
||||
fbclkdlystart = fbclkdlyend = 0xff;
|
||||
|
||||
while (fbclkdly < 32)
|
||||
{
|
||||
@ -287,15 +314,18 @@ static uint32_t lx_cpu_sdram_find_fbclkdly(void)
|
||||
if (lx_cpu_sdram_test() == 0x1)
|
||||
{
|
||||
/* Test passed */
|
||||
if (fbclkdlystart == 0xFF)
|
||||
|
||||
if (fbclkdlystart == 0xff)
|
||||
{
|
||||
fbclkdlystart = fbclkdly;
|
||||
}
|
||||
|
||||
ppass = 0x1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Test failed */
|
||||
|
||||
if (ppass == 1)
|
||||
{
|
||||
fbclkdlyend = fbclkdly;
|
||||
@ -305,29 +335,32 @@ static uint32_t lx_cpu_sdram_find_fbclkdly(void)
|
||||
}
|
||||
|
||||
/* Try next value */
|
||||
|
||||
fbclkdly++;
|
||||
}
|
||||
|
||||
/* If the test passed, the we can use the average of the
|
||||
* min and max values to get an optimal DQSIN delay
|
||||
*/
|
||||
if (pass == 0x1)
|
||||
{
|
||||
fbclkdly = (fbclkdlystart + fbclkdlyend) / 2;
|
||||
}
|
||||
else if (ppass == 0x1)
|
||||
{
|
||||
fbclkdly = (fbclkdlystart + 0x1F) / 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* A working value couldn't be found, just pick something
|
||||
* safe so the system doesn't become unstable
|
||||
*/
|
||||
fbclkdly = 0x10;
|
||||
}
|
||||
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
if (pass == 0x1)
|
||||
{
|
||||
fbclkdly = (fbclkdlystart + fbclkdlyend) / 2;
|
||||
}
|
||||
else if (ppass == 0x1)
|
||||
{
|
||||
fbclkdly = (fbclkdlystart + 0x1f) / 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* A working value couldn't be found, just pick something
|
||||
* safe so the system doesn't become unstable
|
||||
*/
|
||||
|
||||
fbclkdly = 0x10;
|
||||
}
|
||||
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
regval &= ~SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
regval |= fbclkdly << SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT;
|
||||
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
|
||||
@ -345,10 +378,12 @@ static uint32_t lx_cpu_sdram_find_fbclkdly(void)
|
||||
* current ring osc count
|
||||
*
|
||||
****************************************************************************/
|
||||
static uint32_t lx_cpu_sdram_calibration( void )
|
||||
|
||||
static uint32_t lx_cpu_sdram_calibration(void)
|
||||
{
|
||||
uint32_t regval, i;
|
||||
uint32_t regval;
|
||||
uint32_t cnt = 0;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < 10; i++)
|
||||
{
|
||||
@ -361,8 +396,10 @@ static uint32_t lx_cpu_sdram_calibration( void )
|
||||
{
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCCAL);
|
||||
}
|
||||
cnt += (regval & 0xFF);
|
||||
}
|
||||
|
||||
cnt += (regval & 0xff);
|
||||
}
|
||||
|
||||
return (cnt / 10);
|
||||
}
|
||||
|
||||
@ -376,29 +413,33 @@ static uint32_t lx_cpu_sdram_calibration( void )
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
static void lx_cpu_sdram_adjust_timing( void )
|
||||
|
||||
static void lx_cpu_sdram_adjust_timing(void)
|
||||
{
|
||||
uint32_t regval, cmddly, fbclkdly;
|
||||
uint32_t regval;
|
||||
uint32_t cmddly;
|
||||
uint32_t fbclkdly;
|
||||
|
||||
/* Current value */
|
||||
|
||||
lx_cpu_ringosccount[1] = lx_cpu_sdram_calibration();
|
||||
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
|
||||
|
||||
cmddly = regval & SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
cmddly >>= SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
cmddly = cmddly * lx_cpu_ringosccount[0] / lx_cpu_ringosccount[1];
|
||||
cmddly <<= SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
cmddly &= SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
cmddly = regval & SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
cmddly >>= SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
cmddly = cmddly * lx_cpu_ringosccount[0] / lx_cpu_ringosccount[1];
|
||||
cmddly <<= SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
|
||||
cmddly &= SYSCON_EMCDLYCTL_CMDDLY_MASK;
|
||||
|
||||
fbclkdly = regval & SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
fbclkdly = regval & SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
fbclkdly >>= SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT;
|
||||
fbclkdly = fbclkdly * lx_cpu_ringosccount[0] / lx_cpu_ringosccount[1];
|
||||
fbclkdly = fbclkdly * lx_cpu_ringosccount[0] / lx_cpu_ringosccount[1];
|
||||
fbclkdly <<= SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT;
|
||||
fbclkdly &= SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
fbclkdly &= SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
|
||||
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK | SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
regval |= cmddly | fbclkdly;
|
||||
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK | SYSCON_EMCDLYCTL_FBCLKDLY_MASK;
|
||||
regval |= cmddly | fbclkdly;
|
||||
|
||||
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
|
||||
}
|
||||
@ -426,9 +467,11 @@ void lx_cpu_sdram_initialize(void)
|
||||
volatile uint32_t delay;
|
||||
|
||||
if (lx_cpu_running_from_sdram())
|
||||
return;
|
||||
/*
|
||||
* Memory MT48LC4M32B2P
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Memory MT48LC4M32B2P
|
||||
* 4 Meg x 32 (1 Meg x 32 x 4 banks)
|
||||
* Configuration 1 Meg x 32 x 4 banks
|
||||
* Refresh count 4K
|
||||
@ -437,7 +480,6 @@ void lx_cpu_sdram_initialize(void)
|
||||
* Column addressing 256 8-bit A[7:0]
|
||||
*/
|
||||
|
||||
|
||||
/* Reconfigure delays:
|
||||
*
|
||||
* CMDDLY: Programmable delay value for EMC outputs in command delayed
|
||||
@ -460,14 +502,14 @@ void lx_cpu_sdram_initialize(void)
|
||||
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
|
||||
putreg32(0, LPC17_40_EMC_CONFIG);
|
||||
|
||||
|
||||
/* Timing for 72 MHz Bus */
|
||||
regval = MDKCFG_CASVAL << EMC_DYNAMICRASCAS_CAS_SHIFT;
|
||||
|
||||
regval = MDKCFG_CASVAL << EMC_DYNAMICRASCAS_CAS_SHIFT;
|
||||
regval |= MDKCFG_RASVAL << EMC_DYNAMICRASCAS_RAS_SHIFT;
|
||||
putreg32(regval, LPC17_40_EMC_DYNAMICRASCAS0); /* 2 RAS, 2 CAS latency */
|
||||
putreg32(1, LPC17_40_EMC_DYNAMICREADCONFIG); /* Command delayed strategy, using EMCCLKDELAY */
|
||||
|
||||
/* EMC_NS2CLK(20) TRP = 20 nS */
|
||||
/* EMC_NS2CLK(20) TRP = 20 nS */
|
||||
putreg32(1, LPC17_40_EMC_DYNAMICRP); /* ( n + 1 ) -> 2 clock cycles */
|
||||
|
||||
putreg32(3, LPC17_40_EMC_DYNAMICRAS); /* ( n + 1 ) -> 4 clock cycles */
|
||||
@ -476,20 +518,20 @@ void lx_cpu_sdram_initialize(void)
|
||||
|
||||
putreg32(2, LPC17_40_EMC_DYNAMICAPR); /* ( n + 1 ) -> 3 clock cycles */
|
||||
|
||||
/* EMC_NS2CLK(20) + 2 TRP + TDPL = 20ns + 2clk */
|
||||
/* EMC_NS2CLK(20) + 2 TRP + TDPL = 20ns + 2clk */
|
||||
putreg32(3, LPC17_40_EMC_DYNAMICDAL); /* ( n ) -> 3 clock cycles */
|
||||
|
||||
putreg32(1, LPC17_40_EMC_DYNAMICWR); /* ( n + 1 ) -> 2 clock cycles */
|
||||
|
||||
/* EMC_NS2CLK(63) */
|
||||
/* EMC_NS2CLK(63) */
|
||||
putreg32(4, LPC17_40_EMC_DYNAMICRC); /* ( n + 1 ) -> 5 clock cycles */
|
||||
|
||||
/* EMC_NS2CLK(63) */
|
||||
/* EMC_NS2CLK(63) */
|
||||
putreg32(4, LPC17_40_EMC_DYNAMICRFC); /* ( n + 1 ) -> 5 clock cycles */
|
||||
|
||||
putreg32(5, LPC17_40_EMC_DYNAMICXSR); /* ( n + 1 ) -> 6 clock cycles */
|
||||
|
||||
/* EMC_NS2CLK(63) */
|
||||
/* EMC_NS2CLK(63) */
|
||||
putreg32(1, LPC17_40_EMC_DYNAMICRRD); /* ( n + 1 ) -> 2 clock cycles */
|
||||
|
||||
putreg32(1, LPC17_40_EMC_STATICEXTENDEDWAIT); /* ( n + 1 ) -> 2 clock cycles */
|
||||
@ -498,54 +540,59 @@ void lx_cpu_sdram_initialize(void)
|
||||
up_mdelay(100);
|
||||
regval = dynctl | EMC_DYNAMICCONTROL_I_NOP;
|
||||
putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NOP command */
|
||||
up_mdelay(200); /* wait 200ms */
|
||||
|
||||
up_mdelay(200); /* wait 200ms */
|
||||
regval = dynctl | EMC_DYNAMICCONTROL_I_PALL;
|
||||
putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue PAL command */
|
||||
putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */
|
||||
for(delay = 0; delay < 0x80; delay++); /* wait 128 AHB clock cycles */
|
||||
|
||||
for (delay = 0; delay < 0x80; delay++); /* wait 128 AHB clock cycles */
|
||||
|
||||
/* Timing for 72MHz Bus */
|
||||
/* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS ( 64ms / 4096 row ) */
|
||||
|
||||
regval = 64000000 / (1 << 12);
|
||||
regval -= 16;
|
||||
/* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS (64ms / 4096 row) */
|
||||
|
||||
regval = 64000000 / (1 << 12);
|
||||
regval -= 16;
|
||||
regval >>= 4;
|
||||
regval = regval * LPC17_40_EMCCLK_MHZ / 1000;
|
||||
regval = regval * LPC17_40_EMCCLK_MHZ / 1000;
|
||||
putreg32(regval, LPC17_40_EMC_DYNAMICREFRESH);
|
||||
|
||||
regval = dynctl | EMC_DYNAMICCONTROL_I_MODE;
|
||||
regval = dynctl | EMC_DYNAMICCONTROL_I_MODE;
|
||||
putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue MODE command */
|
||||
|
||||
/* Timing for 48/60/72MHZ Bus */
|
||||
modeval = LPC17_40_EXTDRAM_CS0;
|
||||
|
||||
modeval = LPC17_40_EXTDRAM_CS0;
|
||||
modeval |= 0x22 << (2 + 2 + 9); /* 4 burst, 2 CAS latency */
|
||||
regval = *(volatile uint32_t *)modeval;
|
||||
regval = *(volatile uint32_t *)modeval;
|
||||
putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NORMAL command */
|
||||
|
||||
/* [re]enable buffers */
|
||||
|
||||
/* 256MB, 8Mx32, 4 banks, row=12, column=9 */
|
||||
regval = EMC_DYNAMICCONFIG_MD_SDRAM;
|
||||
|
||||
regval = EMC_DYNAMICCONFIG_MD_SDRAM;
|
||||
regval |= 9 << EMC_DYNAMICCONFIG_AM0_SHIFT;
|
||||
regval |= 1 * EMC_DYNAMICCONFIG_AM1;
|
||||
regval |= EMC_DYNAMICCONFIG_B;
|
||||
putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0);
|
||||
|
||||
/* Nominal value */
|
||||
|
||||
lx_cpu_ringosccount[0] = lx_cpu_sdram_calibration();
|
||||
|
||||
if (lx_cpu_sdram_find_cmddly() == 0x0)
|
||||
{
|
||||
return; /* fatal error */
|
||||
}
|
||||
{
|
||||
return; /* fatal error */
|
||||
}
|
||||
|
||||
if (lx_cpu_sdram_find_fbclkdly() == 0x0)
|
||||
{
|
||||
{
|
||||
return; /* fatal error */
|
||||
}
|
||||
}
|
||||
|
||||
lx_cpu_sdram_adjust_timing();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c
|
||||
* arch/arm/src/board/lpc17_40_ssp.c
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -104,30 +103,31 @@ void weak_function lx_cpu_sspdev_initialize(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status
|
||||
* must be provided by board-specific logic. They are implementations of the select
|
||||
* and status methods of the SPI interface defined by struct spi_ops_s (see
|
||||
* include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize())
|
||||
* are provided by common LPC17xx logic. To use this common SPI logic on your
|
||||
* board:
|
||||
* The external functions, lpc17_40_ssp0/1/2select and
|
||||
* lpc17_40_ssp0/1/2status must be provided by board-specific logic. They
|
||||
* are implementations of the select and status methods of the SPI
|
||||
* interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
|
||||
* All other methods (including lpc17_40_sspbus_initialize()) are provided
|
||||
* by common LPC17xx logic. To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select
|
||||
* pins.
|
||||
* 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status() functions
|
||||
* in your board-specific logic. These functions will perform chip selection
|
||||
* and status operations using GPIOs in the way your board is configured.
|
||||
* 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP
|
||||
* chip select pins.
|
||||
* 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status()
|
||||
* functions in your board-specific logic. These functions will
|
||||
* perform chip selection and status operations using GPIOs in the way
|
||||
* your board is configured.
|
||||
* 3. Add a calls to lpc17_40_sspbus_initialize() in your low level
|
||||
* application initialization logic
|
||||
* 4. The handle returned by lpc17_40_sspbus_initialize() may then be
|
||||
* used to bind the SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC17_40_SSP0
|
||||
void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
|
||||
@ -56,11 +56,6 @@
|
||||
|
||||
#include "lx_cpu.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
@ -73,14 +68,15 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data *chip_data)
|
||||
int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data_s *chip_data)
|
||||
{
|
||||
uint32_t regval;
|
||||
irqstate_t flags;
|
||||
|
||||
if (minor > 0)
|
||||
return 0;
|
||||
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Step 1: Enable power on UART1 */
|
||||
|
||||
@ -115,4 +111,3 @@ int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data *chip_data)
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c
|
||||
* arch/arm/src/board/lpc17_40_userleds.c
|
||||
*
|
||||
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2019Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h
|
||||
* arch/arm/src/board/lx_cpu.n
|
||||
*
|
||||
* Copyright (C) 2013, 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -32,23 +31,23 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef _CONFIGS_LX_CPU_SRC_LX_CPU_H
|
||||
#define _CONFIGS_LX_CPU_SRC_LX_CPU_H
|
||||
#ifndef _BOARDS_ARM_LPC17XX_40XX_LX_CPU_SRC_LX_CPU_SRC_LX_CPU_H
|
||||
#define _BOARDS_ARM_LPC17XX_40XX_LX_CPU_SRC_LX_CPU_SRC_LX_CPU_H
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/* LX_CPU GPIO Pin Definitions ****************************************************/
|
||||
/* LX_CPU GPIO Pin Definitions **********************************************/
|
||||
|
||||
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
|
||||
* any way. The following definitions are used to access individual LEDs.
|
||||
@ -56,36 +55,47 @@
|
||||
* LED1 -- Connected to P1[29] RED
|
||||
* LED2 -- Connected to P0[16] GREEN
|
||||
*
|
||||
* These LEDs are connecte to ground so a high output value will illuminate them.
|
||||
* These LEDs are connected to ground so a high output value will illuminate
|
||||
* them.
|
||||
*/
|
||||
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN29)
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN16)
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | \
|
||||
GPIO_PIN29)
|
||||
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | \
|
||||
GPIO_PIN16)
|
||||
|
||||
/* SD Card **************************************************************************/
|
||||
/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also
|
||||
* used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper
|
||||
* on board that enables the CD pin.
|
||||
/* SD Card ******************************************************************/
|
||||
|
||||
/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It
|
||||
* is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected.
|
||||
* There is a jumper on board that enables the CD pin.
|
||||
*
|
||||
* The CD pin is interrupting:
|
||||
*/
|
||||
|
||||
#define GPIO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13)
|
||||
#define GPIO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | \
|
||||
GPIO_PIN13)
|
||||
|
||||
/* LCD **********************************************************************/
|
||||
|
||||
/* LCD ******************************************************************************/
|
||||
/* Backlight enable, P2[1]. Initial state is OFF (zero) */
|
||||
|
||||
#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN1)
|
||||
#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | \
|
||||
GPIO_PIN1)
|
||||
|
||||
/* XPT2046 Touchscreen **************************************************************/
|
||||
/* -------------- -------------------- ------------ --------------------------------
|
||||
/* XPT2046 Touchscreen ******************************************************/
|
||||
|
||||
/* -------------- -------------------- ------------ ---------------------------------
|
||||
* XTPT2046 Module Module LX_CPU LED
|
||||
* Signal Connector Connector
|
||||
* -------------- -------------------- ------------ ---------------------------------
|
||||
* Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ
|
||||
* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED)
|
||||
* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP
|
||||
* LED)
|
||||
* Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY
|
||||
* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin)
|
||||
* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device
|
||||
* up LED and SD CD
|
||||
* pin)
|
||||
* Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV)
|
||||
* Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1
|
||||
* -------------- -------------------- ------------ ---------------------------------
|
||||
@ -100,17 +110,17 @@
|
||||
|
||||
#define LPC17_40_IRQ_PENIRQ LPC17_40_IRQ_P2p15
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public data
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: lx_cpu_bringup
|
||||
*
|
||||
* Description:
|
||||
@ -122,57 +132,57 @@
|
||||
* CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
|
||||
* Called from the NSH library via boardctl()
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
int lx_cpu_bringup(void);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: lx_cpu_sspdev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the WaveShare LX_CPU board.
|
||||
* Called to configure SPI chip select GPIO pins for the WaveShare LX_CPU
|
||||
* board.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function lx_cpu_sspdev_initialize(void);
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: lx_cpu_sdram_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDRAM
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC17_40_EMC
|
||||
#ifdef CONFIG_LPC17_40_EXTDRAM
|
||||
void lx_cpu_sdram_initialize(void);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: lx_cpu_fpga_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize FPGA chipselect
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void lx_cpu_fpga_initialize(void);
|
||||
|
||||
#endif /* CONFIG_LPC17_40_EMC */
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Name: lx_cpu_can_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize CAN and register the CAN device
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
int lx_cpu_can_setup(void);
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _CONFIGS_LX_CPU_SRC_LX_CPU_H */
|
||||
#endif /* _BOARDS_ARM_LPC17XX_40XX_LX_CPU_SRC_LX_CPU_SRC_LX_CPU_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user