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Coding style fixes. Run every new file through tools/nxstyle to assure that it is close to the NuttX coding standard.

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This commit is contained in:
Gregory Nutt 2019-08-30 08:37:27 -06:00
parent 64c918783b
commit dc09d7018b
15 changed files with 322 additions and 255 deletions
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37
boards/arm/lpc17xx_40xx/lx_cpu/include/board.h
View File

@ -2,7 +2,7 @@
* boards/arm/lpc17xx_40xx/lx_cpu/include/board.h * boards/arm/lpc17xx_40xx/lx_cpu/include/board.h
* include/arch/board/board.h * include/arch/board/board.h
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -52,9 +52,11 @@
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Clocking *************************************************************************/ /* Clocking *************************************************************************/
/* NOTE: The following definitions require lpc17_40_syscon.h. It is not included here
* because the including C file may not have that file in its include path. /* NOTE: The following definitions require lpc17_40_syscon.h. It is not included
* here because the including C file may not have that file in its include path.
*/ */
#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */ #define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
@ -163,11 +165,11 @@
#define GPIO_USB_PWRD (GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN10) #define GPIO_USB_PWRD (GPIO_FLOAT | GPIO_PORT2 | GPIO_PIN10)
/* #if 0
#define GPIO_USB_PPWR # define GPIO_USB_PPWR
#define GPIO_USB_PWRD # define GPIO_USB_PWRD
#define GPIO_USB_OVRCR # define GPIO_USB_OVRCR
*/ #endif
/* FLASH Configuration */ /* FLASH Configuration */
@ -252,9 +254,10 @@
#define BOARD_NADDR 16 #define BOARD_NADDR 16
#define BOARD_NDATA 32 #define BOARD_NDATA 32
//#define BOARD_EMC_CONFIG_BY_LOADER 1 /* #define BOARD_EMC_CONFIG_BY_LOADER 1 */
/* LED definitions ******************************************************************/ /* LED definitions ******************************************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in /* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
* any way. The following definitions are used to access individual LEDs. * any way. The following definitions are used to access individual LEDs.
* *
@ -292,6 +295,7 @@
* OFF while sleeping */ * OFF while sleeping */
/* Button definitions ***************************************************************/ /* Button definitions ***************************************************************/
/* The LX_CPU supports several buttons. All must be pulled up by the LX_CPU. /* The LX_CPU supports several buttons. All must be pulled up by the LX_CPU.
* When closed, the pins will be pulled to ground. So the buttons will read "1" * When closed, the pins will be pulled to ground. So the buttons will read "1"
* when open and "0" when closed. All except USER1 are capable of generating * when open and "0" when closed. All except USER1 are capable of generating
@ -313,7 +317,6 @@
* release). * release).
*/ */
#define BOARD_BUTTON_USER1 0 #define BOARD_BUTTON_USER1 0
#define BOARD_BUTTON_USER2 1 #define BOARD_BUTTON_USER2 1
#define BOARD_BUTTON_USER3 2 #define BOARD_BUTTON_USER3 2
@ -448,20 +451,21 @@
/* XPT2046 Touchscreen: /* XPT2046 Touchscreen:
* *
/* -------------- -------------------- ------------ -------------------------------- * -------------- -------------------- ------------ --------------------------------
* XTPT2046 Module Module LX_CPU LED * XTPT2046 Module Module LX_CPU LED
* Signal Connector Connector * Signal Connector Connector
* -------------- -------------------- ------------ --------------------------------- * -------------- -------------------- ------------ ---------------------------------
* Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ
* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP
* LED)
* Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY
* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up
* LED and SD CD pin)
* Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV)
* Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1
* -------------- -------------------- ------------ --------------------------------- * -------------- -------------------- ------------ ---------------------------------
*/ */
#define GPIO_SSP1_MISO GPIO_SSP1_MISO_3 #define GPIO_SSP1_MISO GPIO_SSP1_MISO_3
#define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2 #define GPIO_SSP1_MOSI GPIO_SSP1_MOSI_2
#define GPIO_SSP1_SCK GPIO_SSP1_SCK_2 #define GPIO_SSP1_SCK GPIO_SSP1_SCK_2
@ -473,7 +477,8 @@
#define UL_DRV_SYSLESS_IRQ LPC17_40_IRQ_UART1 #define UL_DRV_SYSLESS_IRQ LPC17_40_IRQ_UART1
#define UL_DRV_SYSLESS_MY_ADR_DEFAULT 3 #define UL_DRV_SYSLESS_MY_ADR_DEFAULT 3
typedef struct nuttx_ulan_chip_data { struct nuttx_ulan_chip_data_s
{
const char *chip; const char *chip;
int my_adr; int my_adr;
int baud; int baud;
@ -482,6 +487,6 @@ typedef struct nuttx_ulan_chip_data {
int port; int port;
}; };
int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data *chip_data); int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data_s *chip_data);
#endif /* __BOARDS_ARM_LX_CPU_INCLUDE_BOARD_H */ #endif /* __BOARDS_ARM_LX_CPU_INCLUDE_BOARD_H */

4
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_appinit.c
* *
* Copyright (C) 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -67,7 +67,7 @@
* arg - The boardctl() argument is passed to the board_app_initialize() * arg - The boardctl() argument is passed to the board_app_initialize()
* implementation without modification. The argument has no * implementation without modification. The argument has no
* meaning to NuttX; the meaning of the argument is a contract * meaning to NuttX; the meaning of the argument is a contract
* between the board-specific initalization logic and the * between the board-specific initialization logic and the
* matching application logic. The value cold be such things as a * matching application logic. The value cold be such things as a
* mode enumeration value, a set of DIP switch switch settings, a * mode enumeration value, a set of DIP switch switch settings, a
* pointer to configuration data read from a file or serial FLASH, * pointer to configuration data read from a file or serial FLASH,

2
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_autoleds.c
* *
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without

16
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c
View File

@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_boardinitialize.c
* *
* Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -51,14 +51,6 @@
#include "lx_cpu.h" #include "lx_cpu.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions
************************************************************************************/ ************************************************************************************/
@ -67,9 +59,9 @@
* Name: lpc17_40_boardinitialize * Name: lpc17_40_boardinitialize
* *
* Description: * Description:
* All LPC17xx architectures must provide the following entry point. This entry point * All LPC17xx architectures must provide the following entry point. This entry
* is called early in the intitialization -- after all memory has been configured * point is called early in the initialization -- after all memory has been
* and mapped but before any devices have been initialized. * configured and mapped but before any devices have been initialized.
* *
************************************************************************************/ ************************************************************************************/

27
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_bringup.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* config/lx_cpu/src/lpc17_40_bringup.c * config/lx_cpu/src/lpc17_40_bringup.c
* *
* Copyright (C) 2013, 2016-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -62,6 +62,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Configuration ************************************************************/ /* Configuration ************************************************************/
#define NSH_HAVE_MMCSD 1 #define NSH_HAVE_MMCSD 1
@ -73,7 +74,8 @@
/* MMC/SD support */ /* MMC/SD support */
#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) #if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && \
!defined(CONFIG_MMCD_SDIO)
# undef NSH_HAVE_MMCSD # undef NSH_HAVE_MMCSD
#endif #endif
@ -83,7 +85,9 @@
# undef NSH_HAVE_MMCSD # undef NSH_HAVE_MMCSD
#endif #endif
/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ /* MMC/SD support requires that an SPI support is enabled and an SPI port
* is selected.
*/
#ifdef NSH_HAVE_MMCSD #ifdef NSH_HAVE_MMCSD
# if !defined(CONFIG_NSH_MMCSDSLOTNO) # if !defined(CONFIG_NSH_MMCSDSLOTNO)
@ -99,9 +103,9 @@
# endif # endif
#endif #endif
/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also /* The SD card detect (CD) signal is on P0[13]. This signal is shared. It
* used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper * is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected.
* on board that enables the CD pin. * There is a jumper on board that enables the CD pin.
*/ */
#ifdef NSH_HAVE_MMCSD #ifdef NSH_HAVE_MMCSD
@ -180,7 +184,7 @@ static int nsh_waiter(int argc, char *argv[])
struct usbhost_hubport_s *hport; struct usbhost_hubport_s *hport;
syslog(LOG_INFO, "nsh_waiter: Running\n"); syslog(LOG_INFO, "nsh_waiter: Running\n");
for (;;) for (; ; )
{ {
/* Wait for the device to change state */ /* Wait for the device to change state */
@ -254,7 +258,6 @@ static int nsh_sdinitialize(void)
(void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL); (void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt, NULL);
up_enable_irq(LPC17_40_IRQ_P0p13); up_enable_irq(LPC17_40_IRQ_P0p13);
#endif #endif
#endif #endif
@ -321,7 +324,9 @@ static int nsh_usbhostinitialize(void)
ret = usbhost_msc_initialize(); ret = usbhost_msc_initialize();
if (ret != OK) if (ret != OK)
{ {
syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); syslog(LOG_ERR,
"ERROR: Failed to register the mass storage class: %d\n",
ret);
} }
#endif #endif
@ -331,7 +336,9 @@ static int nsh_usbhostinitialize(void)
ret = usbhost_cdcacm_initialize(); ret = usbhost_cdcacm_initialize();
if (ret != OK) if (ret != OK)
{ {
syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); syslog(LOG_ERR,
"ERROR: Failed to register the CDC/ACM serial class: %d\n",
ret);
} }
#endif #endif

5
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_can.c
View File

@ -6,7 +6,7 @@
* *
* Based on boards/olimex-lpc1766stk/src/lpc17_40_can.c * Based on boards/olimex-lpc1766stk/src/lpc17_40_can.c
* *
* Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2012, 2016, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -61,6 +61,7 @@
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* Configuration ********************************************************************/ /* Configuration ********************************************************************/
#define CAN_PORT1 1 #define CAN_PORT1 1
@ -71,7 +72,7 @@
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Name: zkit_can_setup * Name: lx_cpu_can_setup
* *
* Description: * Description:
* Initialize CAN and register the CAN device * Initialize CAN and register the CAN device

4
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_composite.c
View File

@ -1,11 +1,10 @@
/***************************************************************************** /*****************************************************************************
* boards/pnev5180b/src/lpc17_40_composite.c * boards/pnev5180b/src/lpc17_40_composite.c
* Configure and register CDC-ACM and CDC-ECM
* *
* Copyright (C) 2019 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Michael Jung <mijung@gmx.net> * Author: Michael Jung <mijung@gmx.net>
* *
* Configure and register CDC-ACM and CDC-ECM
*
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
@ -65,7 +64,6 @@
int board_composite_initialize(int port) int board_composite_initialize(int port)
{ {
syslog(LOG_INFO, "board_composite_initialize(port: %d)\n", port); syslog(LOG_INFO, "board_composite_initialize(port: %d)\n", port);
return OK; return OK;
} }

17
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_fpgainitialize.c
View File

@ -1,8 +1,7 @@
/************************************************************************************ /************************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c
* arch/arm/src/board/lpc17_40_sdraminitialize.c
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -54,10 +53,15 @@
#include "lx_cpu.h" #include "lx_cpu.h"
/************************************************************************************
* Public Functions
************************************************************************************/
void lx_cpu_fpga_initialize(void) void lx_cpu_fpga_initialize(void)
{ {
uint32_t regval; uint32_t regval;
/* Initialze EMC for FPGA */
/* Initialize EMC for FPGA */
lpc17_40_configgpio(BOARD_XC_PROGRAM_PIN); lpc17_40_configgpio(BOARD_XC_PROGRAM_PIN);
lpc17_40_configgpio(BOARD_XC_DONE_PIN); lpc17_40_configgpio(BOARD_XC_DONE_PIN);
@ -73,6 +77,7 @@ void lx_cpu_fpga_initialize(void)
* Buffer: disabled * Buffer: disabled
* Write protection: disabled * Write protection: disabled
*/ */
putreg32(0x00000002, LPC17_40_EMC_STATICCONFIG0); putreg32(0x00000002, LPC17_40_EMC_STATICCONFIG0);
/* Delays - not measured at this point /* Delays - not measured at this point
@ -81,11 +86,13 @@ void lx_cpu_fpga_initialize(void)
* Write: 33 cycles * Write: 33 cycles
* Turnaround: 2 cycles (cca. 28 ns) * Turnaround: 2 cycles (cca. 28 ns)
*/ */
putreg32(0x1F, LPC17_40_EMC_STATICWAITRD0);
putreg32(0x1F, LPC17_40_EMC_STATICWAITWR0); putreg32(0x1f, LPC17_40_EMC_STATICWAITRD0);
putreg32(0x1f, LPC17_40_EMC_STATICWAITWR0);
putreg32(0x01, LPC17_40_EMC_STATICWAITTURN0); putreg32(0x01, LPC17_40_EMC_STATICWAITTURN0);
/* Shift addresses by 2 (32-bit bus) */ /* Shift addresses by 2 (32-bit bus) */
regval = getreg32(LPC17_40_SYSCON_SCS); regval = getreg32(LPC17_40_SYSCON_SCS);
regval &= ~SYSCON_SCS_EMCSC; regval &= ~SYSCON_SCS_EMCSC;
putreg32(regval, LPC17_40_SYSCON_SCS); putreg32(regval, LPC17_40_SYSCON_SCS);

34
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_nsh.c
View File

@ -1,8 +1,7 @@
/**************************************************************************** /****************************************************************************
* config/lx_cpu/src/lpc17_40_nsh.c * config/lx_cpu/src/lpc17_40_nsh.c
* arch/arm/src/board/lpc17_40_nsh.c
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -60,6 +59,7 @@
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* Configuration ************************************************************/ /* Configuration ************************************************************/
#define NSH_HAVE_MMCSD 1 #define NSH_HAVE_MMCSD 1
@ -71,7 +71,8 @@
/* MMC/SD support */ /* MMC/SD support */
#if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && !defined(CONFIG_MMCD_SDIO) #if !defined(CONFIG_LPC17_40_SDCARD) || !defined(CONFIG_MMCSD) && \
!defined(CONFIG_MMCD_SDIO)
# undef NSH_HAVE_MMCSD # undef NSH_HAVE_MMCSD
#endif #endif
@ -81,7 +82,9 @@
# undef NSH_HAVE_MMCSD # undef NSH_HAVE_MMCSD
#endif #endif
/* MMC/SD support requires that an SPI support is enabled and an SPI port is selected */ /* MMC/SD support requires that an SPI support is enabled and an SPI port is
* selected.
*/
#ifdef NSH_HAVE_MMCSD #ifdef NSH_HAVE_MMCSD
# if !defined(CONFIG_NSH_MMCSDSLOTNO) # if !defined(CONFIG_NSH_MMCSDSLOTNO)
@ -97,9 +100,9 @@
# endif # endif
#endif #endif
/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also /* The SD card detect (CD) signal is on P0[13]. This signal is shared. It
* used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper * is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected.
* on board that enables the CD pin. * There is a jumper on board that enables the CD pin.
*/ */
#ifdef NSH_HAVE_MMCSD #ifdef NSH_HAVE_MMCSD
@ -178,12 +181,13 @@ static int nsh_waiter(int argc, char *argv[])
struct usbhost_hubport_s *hport; struct usbhost_hubport_s *hport;
syslog(LOG_INFO, "nsh_waiter: Running\n"); syslog(LOG_INFO, "nsh_waiter: Running\n");
for (;;) for (; ; )
{ {
/* Wait for the device to change state */ /* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
syslog(LOG_INFO, "nsh_waiter: %s\n", hport->connected ? "connected" : "disconnected"); syslog(LOG_INFO, "nsh_waiter: %s\n",
hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */ /* Did we just become connected? */
@ -244,15 +248,13 @@ static int nsh_sdinitialize(void)
lpc17_40_configgpio(GPIO_SD_CD); lpc17_40_configgpio(GPIO_SD_CD);
#if NSH_HAVE_MMCSD_CDINT
/* Attach an interrupt handler to get notifications when a card is /* Attach an interrupt handler to get notifications when a card is
* inserted or deleted. * inserted or deleted.
*/ */
#if NSH_HAVE_MMCSD_CDINT
(void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt); (void)irq_attach(LPC17_40_IRQ_P0p13, nsh_cdinterrupt);
up_enable_irq(LPC17_40_IRQ_P0p13); up_enable_irq(LPC17_40_IRQ_P0p13);
#endif #endif
#endif #endif
@ -319,7 +321,9 @@ static int nsh_usbhostinitialize(void)
ret = usbhost_msc_initialize(); ret = usbhost_msc_initialize();
if (ret != OK) if (ret != OK)
{ {
syslog(LOG_ERR, "ERROR: Failed to register the mass storage class: %d\n", ret); syslog(LOG_ERR,
"ERROR: Failed to register the mass storage class: %d\n",
ret);
} }
#endif #endif
@ -329,7 +333,9 @@ static int nsh_usbhostinitialize(void)
ret = usbhost_cdcacm_initialize(); ret = usbhost_cdcacm_initialize();
if (ret != OK) if (ret != OK)
{ {
syslog(LOG_ERR, "ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); syslog(LOG_ERR,
"ERROR: Failed to register the CDC/ACM serial class: %d\n",
ret);
} }
#endif #endif

2
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_reset.c
View File

@ -46,7 +46,7 @@
#ifdef CONFIG_BOARDCTL_RESET #ifdef CONFIG_BOARDCTL_RESET
/**************************************************************************** /****************************************************************************
* Public functions * Public Functions
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************

109
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c
View File

@ -1,8 +1,7 @@
/************************************************************************************ /************************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_sdraminitialize.c
* arch/arm/src/board/lpc17_40_sdraminitialize.c
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -59,8 +58,8 @@
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ************************************************************************************/
/* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided), or /* The core clock is LPC17_40_EMCCLK which may be either LPC17_40_CCLK* (undivided)
* LPC17_40_CCLK / 2 as determined by settings in the board.h header file. * or LPC17_40_CCLK / 2 as determined by settings in the board.h header file.
* *
* For example: * For example:
* LPC17_40_CCLCK = 120,000,000 * LPC17_40_CCLCK = 120,000,000
@ -99,12 +98,14 @@
#define SDRAM_BASE 0xa0000000 /* CS0 */ #define SDRAM_BASE 0xa0000000 /* CS0 */
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
static volatile uint32_t lx_cpu_ringosccount[2] = {0,0}; static volatile uint32_t lx_cpu_ringosccount[2] =
{
0, 0
};
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
@ -129,9 +130,13 @@ static int lx_cpu_running_from_sdram(void)
if (((uint32_t)lx_cpu_running_from_sdram >= LPC17_40_EXTDRAM_CS0) && if (((uint32_t)lx_cpu_running_from_sdram >= LPC17_40_EXTDRAM_CS0) &&
((uint32_t)lx_cpu_running_from_sdram < extdram_end)) ((uint32_t)lx_cpu_running_from_sdram < extdram_end))
{
return 1; return 1;
}
else else
{
return 0; return 0;
}
} }
/* SDRAM code based on NXP application notes and emc_sdram.c example */ /* SDRAM code based on NXP application notes and emc_sdram.c example */
@ -147,17 +152,20 @@ static int lx_cpu_running_from_sdram(void)
* 1 if test passed, otherwise 0 * 1 if test passed, otherwise 0
* *
****************************************************************************/ ****************************************************************************/
static uint32_t lx_cpu_sdram_test( void )
static uint32_t lx_cpu_sdram_test(void)
{ {
volatile uint32_t *wr_ptr; volatile uint32_t *wr_ptr;
volatile uint16_t *short_wr_ptr; volatile uint16_t *short_wr_ptr;
uint32_t data; uint32_t data;
uint32_t i, j; uint32_t i;
uint32_t j;
wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0; wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0;
short_wr_ptr = (uint16_t *)wr_ptr; short_wr_ptr = (uint16_t *)wr_ptr;
/* 16 bit write */ /* 16 bit write */
for (i = 0; i < 64; i++) for (i = 0; i < 64; i++)
{ {
for (j = 0; j < 0x100; j++) for (j = 0; j < 0x100; j++)
@ -168,19 +176,22 @@ static uint32_t lx_cpu_sdram_test( void )
} }
/* Verifying */ /* Verifying */
wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0; wr_ptr = (uint32_t *)LPC17_40_EXTDRAM_CS0;
for (i = 0; i < 64; i++) for (i = 0; i < 64; i++)
{ {
for (j = 0; j < 0x100; j++) for (j = 0; j < 0x100; j++)
{ {
data = *wr_ptr; data = *wr_ptr;
if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF))) if (data != (((((i + j) + 1) & 0xffff) << 16) | ((i + j) & 0xffff)))
{ {
return 0x0; return 0x0;
} }
wr_ptr++; wr_ptr++;
} }
} }
return 0x1; return 0x1;
} }
@ -194,13 +205,18 @@ static uint32_t lx_cpu_sdram_test( void )
* 1 if test passed, otherwise 0 * 1 if test passed, otherwise 0
* *
****************************************************************************/ ****************************************************************************/
static uint32_t lx_cpu_sdram_find_cmddly(void) static uint32_t lx_cpu_sdram_find_cmddly(void)
{ {
uint32_t cmddly, cmddlystart, cmddlyend, regval; uint32_t cmddly;
uint32_t ppass = 0x0, pass = 0x0; uint32_t cmddlystart;
uint32_t cmddlyend;
uint32_t regval;
uint32_t ppass = 0x0;
uint32_t pass = 0x0;
cmddly = 0x0; cmddly = 0x0;
cmddlystart = cmddlyend = 0xFF; cmddlystart = cmddlyend = 0xff;
while (cmddly < 32) while (cmddly < 32)
{ {
@ -212,15 +228,18 @@ static uint32_t lx_cpu_sdram_find_cmddly(void)
if (lx_cpu_sdram_test() == 0x1) if (lx_cpu_sdram_test() == 0x1)
{ {
/* Test passed */ /* Test passed */
if (cmddlystart == 0xFF)
if (cmddlystart == 0xff)
{ {
cmddlystart = cmddly; cmddlystart = cmddly;
} }
ppass = 0x1; ppass = 0x1;
} }
else else
{ {
/* Test failed */ /* Test failed */
if (ppass == 1) if (ppass == 1)
{ {
cmddlyend = cmddly; cmddlyend = cmddly;
@ -230,19 +249,21 @@ static uint32_t lx_cpu_sdram_find_cmddly(void)
} }
/* Try next value */ /* Try next value */
cmddly++; cmddly++;
} }
/* If the test passed, the we can use the average of the min and max /* If the test passed, the we can use the average of the min and max
* values to get an optimal DQSIN delay * values to get an optimal DQSIN delay
*/ */
if (pass == 0x1) if (pass == 0x1)
{ {
cmddly = (cmddlystart + cmddlyend) / 2; cmddly = (cmddlystart + cmddlyend) / 2;
} }
else if (ppass == 0x1) else if (ppass == 0x1)
{ {
cmddly = (cmddlystart + 0x1F) / 2; cmddly = (cmddlystart + 0x1f) / 2;
} }
else else
{ {
@ -251,6 +272,7 @@ static uint32_t lx_cpu_sdram_find_cmddly(void)
*/ */
cmddly = 0x10; cmddly = 0x10;
} }
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK; regval &= ~SYSCON_EMCDLYCTL_CMDDLY_MASK;
regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT; regval |= cmddly << SYSCON_EMCDLYCTL_CMDDLY_SHIFT;
@ -269,13 +291,18 @@ static uint32_t lx_cpu_sdram_find_cmddly(void)
* 1 if test passed, otherwise 0 * 1 if test passed, otherwise 0
* *
****************************************************************************/ ****************************************************************************/
static uint32_t lx_cpu_sdram_find_fbclkdly(void) static uint32_t lx_cpu_sdram_find_fbclkdly(void)
{ {
uint32_t fbclkdly, fbclkdlystart, fbclkdlyend, regval; uint32_t fbclkdly;
uint32_t ppass = 0x0, pass = 0x0; uint32_t fbclkdlystart;
uint32_t fbclkdlyend;
uint32_t regval;
uint32_t ppass = 0x0;
uint32_t pass = 0x0;
fbclkdly = 0x0; fbclkdly = 0x0;
fbclkdlystart = fbclkdlyend = 0xFF; fbclkdlystart = fbclkdlyend = 0xff;
while (fbclkdly < 32) while (fbclkdly < 32)
{ {
@ -287,15 +314,18 @@ static uint32_t lx_cpu_sdram_find_fbclkdly(void)
if (lx_cpu_sdram_test() == 0x1) if (lx_cpu_sdram_test() == 0x1)
{ {
/* Test passed */ /* Test passed */
if (fbclkdlystart == 0xFF)
if (fbclkdlystart == 0xff)
{ {
fbclkdlystart = fbclkdly; fbclkdlystart = fbclkdly;
} }
ppass = 0x1; ppass = 0x1;
} }
else else
{ {
/* Test failed */ /* Test failed */
if (ppass == 1) if (ppass == 1)
{ {
fbclkdlyend = fbclkdly; fbclkdlyend = fbclkdly;
@ -305,25 +335,28 @@ static uint32_t lx_cpu_sdram_find_fbclkdly(void)
} }
/* Try next value */ /* Try next value */
fbclkdly++; fbclkdly++;
} }
/* If the test passed, the we can use the average of the /* If the test passed, the we can use the average of the
* min and max values to get an optimal DQSIN delay * min and max values to get an optimal DQSIN delay
*/ */
if (pass == 0x1) if (pass == 0x1)
{ {
fbclkdly = (fbclkdlystart + fbclkdlyend) / 2; fbclkdly = (fbclkdlystart + fbclkdlyend) / 2;
} }
else if (ppass == 0x1) else if (ppass == 0x1)
{ {
fbclkdly = (fbclkdlystart + 0x1F) / 2; fbclkdly = (fbclkdlystart + 0x1f) / 2;
} }
else else
{ {
/* A working value couldn't be found, just pick something /* A working value couldn't be found, just pick something
* safe so the system doesn't become unstable * safe so the system doesn't become unstable
*/ */
fbclkdly = 0x10; fbclkdly = 0x10;
} }
@ -345,10 +378,12 @@ static uint32_t lx_cpu_sdram_find_fbclkdly(void)
* current ring osc count * current ring osc count
* *
****************************************************************************/ ****************************************************************************/
static uint32_t lx_cpu_sdram_calibration( void )
static uint32_t lx_cpu_sdram_calibration(void)
{ {
uint32_t regval, i; uint32_t regval;
uint32_t cnt = 0; uint32_t cnt = 0;
uint32_t i;
for (i = 0; i < 10; i++) for (i = 0; i < 10; i++)
{ {
@ -361,8 +396,10 @@ static uint32_t lx_cpu_sdram_calibration( void )
{ {
regval = getreg32(LPC17_40_SYSCON_EMCCAL); regval = getreg32(LPC17_40_SYSCON_EMCCAL);
} }
cnt += (regval & 0xFF);
cnt += (regval & 0xff);
} }
return (cnt / 10); return (cnt / 10);
} }
@ -376,11 +413,15 @@ static uint32_t lx_cpu_sdram_calibration( void )
* None * None
* *
****************************************************************************/ ****************************************************************************/
static void lx_cpu_sdram_adjust_timing( void )
static void lx_cpu_sdram_adjust_timing(void)
{ {
uint32_t regval, cmddly, fbclkdly; uint32_t regval;
uint32_t cmddly;
uint32_t fbclkdly;
/* Current value */ /* Current value */
lx_cpu_ringosccount[1] = lx_cpu_sdram_calibration(); lx_cpu_ringosccount[1] = lx_cpu_sdram_calibration();
regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL); regval = getreg32(LPC17_40_SYSCON_EMCDLYCTL);
@ -426,9 +467,11 @@ void lx_cpu_sdram_initialize(void)
volatile uint32_t delay; volatile uint32_t delay;
if (lx_cpu_running_from_sdram()) if (lx_cpu_running_from_sdram())
{
return; return;
/* }
* Memory MT48LC4M32B2P
/* Memory MT48LC4M32B2P
* 4 Meg x 32 (1 Meg x 32 x 4 banks) * 4 Meg x 32 (1 Meg x 32 x 4 banks)
* Configuration 1 Meg x 32 x 4 banks * Configuration 1 Meg x 32 x 4 banks
* Refresh count 4K * Refresh count 4K
@ -437,7 +480,6 @@ void lx_cpu_sdram_initialize(void)
* Column addressing 256 8-bit A[7:0] * Column addressing 256 8-bit A[7:0]
*/ */
/* Reconfigure delays: /* Reconfigure delays:
* *
* CMDDLY: Programmable delay value for EMC outputs in command delayed * CMDDLY: Programmable delay value for EMC outputs in command delayed
@ -460,8 +502,8 @@ void lx_cpu_sdram_initialize(void)
putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL); putreg32(regval, LPC17_40_SYSCON_EMCDLYCTL);
putreg32(0, LPC17_40_EMC_CONFIG); putreg32(0, LPC17_40_EMC_CONFIG);
/* Timing for 72 MHz Bus */ /* Timing for 72 MHz Bus */
regval = MDKCFG_CASVAL << EMC_DYNAMICRASCAS_CAS_SHIFT; regval = MDKCFG_CASVAL << EMC_DYNAMICRASCAS_CAS_SHIFT;
regval |= MDKCFG_RASVAL << EMC_DYNAMICRASCAS_RAS_SHIFT; regval |= MDKCFG_RASVAL << EMC_DYNAMICRASCAS_RAS_SHIFT;
putreg32(regval, LPC17_40_EMC_DYNAMICRASCAS0); /* 2 RAS, 2 CAS latency */ putreg32(regval, LPC17_40_EMC_DYNAMICRASCAS0); /* 2 RAS, 2 CAS latency */
@ -498,15 +540,17 @@ void lx_cpu_sdram_initialize(void)
up_mdelay(100); up_mdelay(100);
regval = dynctl | EMC_DYNAMICCONTROL_I_NOP; regval = dynctl | EMC_DYNAMICCONTROL_I_NOP;
putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NOP command */ putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NOP command */
up_mdelay(200); /* wait 200ms */ up_mdelay(200); /* wait 200ms */
regval = dynctl | EMC_DYNAMICCONTROL_I_PALL; regval = dynctl | EMC_DYNAMICCONTROL_I_PALL;
putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue PAL command */ putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue PAL command */
putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */ putreg32(2, LPC17_40_EMC_DYNAMICREFRESH); /* ( n * 16 ) -> 32 clock cycles */
for(delay = 0; delay < 0x80; delay++); /* wait 128 AHB clock cycles */
for (delay = 0; delay < 0x80; delay++); /* wait 128 AHB clock cycles */
/* Timing for 72MHz Bus */ /* Timing for 72MHz Bus */
/* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS ( 64ms / 4096 row ) */
/* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS (64ms / 4096 row) */
regval = 64000000 / (1 << 12); regval = 64000000 / (1 << 12);
regval -= 16; regval -= 16;
@ -518,13 +562,16 @@ void lx_cpu_sdram_initialize(void)
putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue MODE command */ putreg32(regval, LPC17_40_EMC_DYNAMICCONTROL); /* Issue MODE command */
/* Timing for 48/60/72MHZ Bus */ /* Timing for 48/60/72MHZ Bus */
modeval = LPC17_40_EXTDRAM_CS0; modeval = LPC17_40_EXTDRAM_CS0;
modeval |= 0x22 << (2 + 2 + 9); /* 4 burst, 2 CAS latency */ modeval |= 0x22 << (2 + 2 + 9); /* 4 burst, 2 CAS latency */
regval = *(volatile uint32_t *)modeval; regval = *(volatile uint32_t *)modeval;
putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NORMAL command */ putreg32(EMC_DYNAMICCONTROL_I_NORMAL, LPC17_40_EMC_DYNAMICCONTROL); /* Issue NORMAL command */
/* [re]enable buffers */ /* [re]enable buffers */
/* 256MB, 8Mx32, 4 banks, row=12, column=9 */ /* 256MB, 8Mx32, 4 banks, row=12, column=9 */
regval = EMC_DYNAMICCONFIG_MD_SDRAM; regval = EMC_DYNAMICCONFIG_MD_SDRAM;
regval |= 9 << EMC_DYNAMICCONFIG_AM0_SHIFT; regval |= 9 << EMC_DYNAMICCONFIG_AM0_SHIFT;
regval |= 1 * EMC_DYNAMICCONFIG_AM1; regval |= 1 * EMC_DYNAMICCONFIG_AM1;
@ -532,6 +579,7 @@ void lx_cpu_sdram_initialize(void)
putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0); putreg32(regval, LPC17_40_EMC_DYNAMICCONFIG0);
/* Nominal value */ /* Nominal value */
lx_cpu_ringosccount[0] = lx_cpu_sdram_calibration(); lx_cpu_ringosccount[0] = lx_cpu_sdram_calibration();
if (lx_cpu_sdram_find_cmddly() == 0x0) if (lx_cpu_sdram_find_cmddly() == 0x0)
@ -545,7 +593,6 @@ void lx_cpu_sdram_initialize(void)
} }
lx_cpu_sdram_adjust_timing(); lx_cpu_sdram_adjust_timing();
return; return;
} }

38
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c
View File

@ -1,8 +1,7 @@
/**************************************************************************** /****************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ssp.c
* arch/arm/src/board/lpc17_40_ssp.c
* *
* Copyright (C) 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -104,30 +103,31 @@ void weak_function lx_cpu_sspdev_initialize(void)
#endif #endif
} }
/************************************************************************************ /****************************************************************************
* Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status * Name: lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status
* *
* Description: * Description:
* The external functions, lpc17_40_ssp0/1/2select and lpc17_40_ssp0/1/2status * The external functions, lpc17_40_ssp0/1/2select and
* must be provided by board-specific logic. They are implementations of the select * lpc17_40_ssp0/1/2status must be provided by board-specific logic. They
* and status methods of the SPI interface defined by struct spi_ops_s (see * are implementations of the select and status methods of the SPI
* include/nuttx/spi/spi.h). All other methods (including lpc17_40_sspbus_initialize()) * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
* are provided by common LPC17xx logic. To use this common SPI logic on your * All other methods (including lpc17_40_sspbus_initialize()) are provided
* board: * by common LPC17xx logic. To use this common SPI logic on your board:
* *
* 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP chip select * 1. Provide logic in lpc17_40_boardinitialize() to configure SPI/SSP
* pins. * chip select pins.
* 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status() functions * 2. Provide lpc17_40_ssp0/1/2select() and lpc17_40_ssp0/1/2status()
* in your board-specific logic. These functions will perform chip selection * functions in your board-specific logic. These functions will
* and status operations using GPIOs in the way your board is configured. * perform chip selection and status operations using GPIOs in the way
* 3. Add a calls to lpc17_40_sspbus_initialize() in your low level application * your board is configured.
* initialization logic * 3. Add a calls to lpc17_40_sspbus_initialize() in your low level
* 4. The handle returned by lpc17_40_sspbus_initialize() may then be used to bind the * application initialization logic
* SPI driver to higher level logic (e.g., calling * 4. The handle returned by lpc17_40_sspbus_initialize() may then be
* used to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver). * the SPI MMC/SD driver).
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_LPC17_40_SSP0 #ifdef CONFIG_LPC17_40_SSP0
void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) void lpc17_40_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)

11
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_ulan.c
View File

@ -56,11 +56,6 @@
#include "lx_cpu.h" #include "lx_cpu.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions
************************************************************************************/ ************************************************************************************/
@ -73,14 +68,15 @@
* *
************************************************************************************/ ************************************************************************************/
int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data *chip_data) int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data_s *chip_data)
{ {
uint32_t regval; uint32_t regval;
irqstate_t flags; irqstate_t flags;
if (minor > 0) if (minor > 0)
{
return 0; return 0;
}
/* Step 1: Enable power on UART1 */ /* Step 1: Enable power on UART1 */
@ -115,4 +111,3 @@ int nuttx_ulan_get_chip_data(int minor, struct nuttx_ulan_chip_data *chip_data)
return 1; return 1;
} }

3
boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c
View File

@ -1,8 +1,7 @@
/**************************************************************************** /****************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c * boards/arm/lpc17xx_40xx/lx_cpu/src/lpc17_40_userleds.c
* arch/arm/src/board/lpc17_40_userleds.c
* *
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. * Copyright (C) 2019Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without

94
boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h
View File

@ -1,8 +1,7 @@
/************************************************************************************ /****************************************************************************
* boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h * boards/arm/lpc17xx_40xx/lx_cpu/src/lx_cpu.h
* arch/arm/src/board/lx_cpu.n
* *
* Copyright (C) 2013, 2017-2018 Gregory Nutt. All rights reserved. * Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -32,23 +31,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ****************************************************************************/
#ifndef _CONFIGS_LX_CPU_SRC_LX_CPU_H #ifndef _BOARDS_ARM_LPC17XX_40XX_LX_CPU_SRC_LX_CPU_SRC_LX_CPU_H
#define _CONFIGS_LX_CPU_SRC_LX_CPU_H #define _BOARDS_ARM_LPC17XX_40XX_LX_CPU_SRC_LX_CPU_SRC_LX_CPU_H
/************************************************************************************ /****************************************************************************
* Included Files * Included Files
************************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/compiler.h> #include <nuttx/compiler.h>
/************************************************************************************ /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
************************************************************************************/ ****************************************************************************/
/* LX_CPU GPIO Pin Definitions ****************************************************/ /* LX_CPU GPIO Pin Definitions **********************************************/
/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in /* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
* any way. The following definitions are used to access individual LEDs. * any way. The following definitions are used to access individual LEDs.
@ -56,36 +55,47 @@
* LED1 -- Connected to P1[29] RED * LED1 -- Connected to P1[29] RED
* LED2 -- Connected to P0[16] GREEN * LED2 -- Connected to P0[16] GREEN
* *
* These LEDs are connecte to ground so a high output value will illuminate them. * These LEDs are connected to ground so a high output value will illuminate
* them.
*/ */
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN29) #define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | \
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN16) GPIO_PIN29)
#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | \
GPIO_PIN16)
/* SD Card **************************************************************************/ /* SD Card ******************************************************************/
/* The SD card detect (CD) signal is on P0[13]. This signal is shared. It is also
* used for MOSI1 and USB_UP_LED. The CD pin may be disconnected. There is a jumper /* The SD card detect (CD) signal is on P0[13]. This signal is shared. It
* on board that enables the CD pin. * is also used for MOSI1 and USB_UP_LED. The CD pin may be disconnected.
* There is a jumper on board that enables the CD pin.
* *
* The CD pin is interrupting: * The CD pin is interrupting:
*/ */
#define GPIO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN13) #define GPIO_SD_CD (GPIO_INTBOTH | GPIO_PULLUP | GPIO_PORT0 | \
GPIO_PIN13)
/* LCD **********************************************************************/
/* LCD ******************************************************************************/
/* Backlight enable, P2[1]. Initial state is OFF (zero) */ /* Backlight enable, P2[1]. Initial state is OFF (zero) */
#define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | GPIO_PIN1) #define GPIO_LCD_BL (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT2 | \
GPIO_PIN1)
/* XPT2046 Touchscreen **************************************************************/ /* XPT2046 Touchscreen ******************************************************/
/* -------------- -------------------- ------------ --------------------------------
/* -------------- -------------------- ------------ ---------------------------------
* XTPT2046 Module Module LX_CPU LED * XTPT2046 Module Module LX_CPU LED
* Signal Connector Connector * Signal Connector Connector
* -------------- -------------------- ------------ --------------------------------- * -------------- -------------------- ------------ ---------------------------------
* Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ * Pin 11 PENIRQ\ PENIRQ (pulled high) PORT3 Pin 1 P2.15 PENIRQ
* Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP LED) * Pin 12 DOUT MISO PORT3 Pin 4 P1.18 MISO1 (Also USB HOST UP
* LED)
* Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY * Pin 13 BUSY BUSY (pulled high) PORT3 Pin 9 P2.14 BUSY
* Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device up LED and SD CD pin) * Pin 14 DIN MOSI PORT3 Pin 3 P0.13 MOSI1 (Also USB Device
* up LED and SD CD
* pin)
* Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV) * Pin 15 CS\ SSEL (pulled high) PORT3 Pin 6 P1.8 GPIO (Also RMII_CRS_DV)
* Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1 * Pin 16 DCLK SCK PORT3 Pin 5 P1.19 SCK1
* -------------- -------------------- ------------ --------------------------------- * -------------- -------------------- ------------ ---------------------------------
@ -100,17 +110,17 @@
#define LPC17_40_IRQ_PENIRQ LPC17_40_IRQ_P2p15 #define LPC17_40_IRQ_PENIRQ LPC17_40_IRQ_P2p15
/************************************************************************************ /****************************************************************************
* Public data * Public data
************************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/************************************************************************************ /****************************************************************************
* Public Functions * Public Functions
************************************************************************************/ ****************************************************************************/
/************************************************************************************ /****************************************************************************
* Name: lx_cpu_bringup * Name: lx_cpu_bringup
* *
* Description: * Description:
@ -122,57 +132,57 @@
* CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library via boardctl() * Called from the NSH library via boardctl()
* *
************************************************************************************/ ****************************************************************************/
int lx_cpu_bringup(void); int lx_cpu_bringup(void);
/************************************************************************************ /****************************************************************************
* Name: lx_cpu_sspdev_initialize * Name: lx_cpu_sspdev_initialize
* *
* Description: * Description:
* Called to configure SPI chip select GPIO pins for the WaveShare LX_CPU board. * Called to configure SPI chip select GPIO pins for the WaveShare LX_CPU
* board.
* *
************************************************************************************/ ****************************************************************************/
void weak_function lx_cpu_sspdev_initialize(void); void weak_function lx_cpu_sspdev_initialize(void);
/************************************************************************************ /****************************************************************************
* Name: lx_cpu_sdram_initialize * Name: lx_cpu_sdram_initialize
* *
* Description: * Description:
* Initialize SDRAM * Initialize SDRAM
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_LPC17_40_EMC #ifdef CONFIG_LPC17_40_EMC
#ifdef CONFIG_LPC17_40_EXTDRAM #ifdef CONFIG_LPC17_40_EXTDRAM
void lx_cpu_sdram_initialize(void); void lx_cpu_sdram_initialize(void);
#endif #endif
/************************************************************************************ /****************************************************************************
* Name: lx_cpu_fpga_initialize * Name: lx_cpu_fpga_initialize
* *
* Description: * Description:
* Initialize FPGA chipselect * Initialize FPGA chipselect
* *
************************************************************************************/ ****************************************************************************/
void lx_cpu_fpga_initialize(void); void lx_cpu_fpga_initialize(void);
#endif /* CONFIG_LPC17_40_EMC */ #endif /* CONFIG_LPC17_40_EMC */
/************************************************************************************ /****************************************************************************
* Name: lx_cpu_can_setup * Name: lx_cpu_can_setup
* *
* Description: * Description:
* Initialize CAN and register the CAN device * Initialize CAN and register the CAN device
* *
************************************************************************************/ ****************************************************************************/
#ifdef CONFIG_CAN #ifdef CONFIG_CAN
int lx_cpu_can_setup(void); int lx_cpu_can_setup(void);
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* _CONFIGS_LX_CPU_SRC_LX_CPU_H */ #endif /* _BOARDS_ARM_LPC17XX_40XX_LX_CPU_SRC_LX_CPU_SRC_LX_CPU_H */