From dc1b6776b9dd48685d1926cc0bfe5d277a93feee Mon Sep 17 00:00:00 2001 From: "Alan C. Assis" Date: Thu, 3 Mar 2022 16:29:10 -0300 Subject: [PATCH] xtensa/esp32s3: Add SPI RAM/PSRAM Support --- arch/xtensa/src/esp32s3/Kconfig | 118 + arch/xtensa/src/esp32s3/Make.defs | 4 + arch/xtensa/src/esp32s3/esp32s3_psram.c | 557 +++ arch/xtensa/src/esp32s3/esp32s3_psram.h | 130 + arch/xtensa/src/esp32s3/esp32s3_spiram.c | 383 ++ arch/xtensa/src/esp32s3/esp32s3_spiram.h | 206 + arch/xtensa/src/esp32s3/esp32s3_start.c | 17 + .../esp32s3/hardware/esp32s3_spi_mem_reg.h | 3584 +++++++++++++++++ .../src/esp32s3/rom/esp32s3_opi_flash.h | 378 ++ .../esp32s3-devkit/scripts/esp32s3_rom.ld | 4 +- 10 files changed, 5379 insertions(+), 2 deletions(-) create mode 100644 arch/xtensa/src/esp32s3/esp32s3_psram.c create mode 100644 arch/xtensa/src/esp32s3/esp32s3_psram.h create mode 100644 arch/xtensa/src/esp32s3/esp32s3_spiram.c create mode 100644 arch/xtensa/src/esp32s3/esp32s3_spiram.h create mode 100644 arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h create mode 100644 arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index 8334464bc2..2cf5e351a4 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -298,6 +298,11 @@ config ESP32S3_RUN_IRAM menu "ESP32-S3 Peripheral Selection" +config ESP32S3_SPIRAM + bool "SPI RAM Support" + default n + select ARCH_HAVE_HEAP2 + config ESP32S3_UART bool default n @@ -331,6 +336,119 @@ config ESP32S3_UART2 select UART2_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS +menu "SPI RAM Config" + depends on ESP32S3_SPIRAM + +choice ESP32S3_SPIRAM_MODE + prompt "Mode (QUAD/OCT) of SPI RAM chip" + default ESP32S3_SPIRAM_MODE_QUAD + +config ESP32S3_SPIRAM_MODE_QUAD + bool "Quad Mode PSRAM" + +config ESP32S3_SPIRAM_MODE_OCT + bool "Octal Mode PSRAM" + +endchoice # ESP32S3_SPIRAM_MODE + +config ESP32S3_DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK pin" + default 30 + +config ESP32S3_DEFAULT_PSRAM_CS_IO + int "PSRAM CS pin" + default 26 + +choice ESP32S3_SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default ESP32S3_SPIRAM_TYPE_AUTO + +config ESP32S3_SPIRAM_TYPE_AUTO + bool "Auto-detect" + +config ESP32S3_SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" + +config ESP32S3_SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config ESP32S3_SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64, LY68L6400 or APS6408" + +endchoice # ESP32S3_SPIRAM_TYPE + +config ESP32S3_SPIRAM_SIZE + int + default -1 if ESP32S3_SPIRAM_TYPE_AUTO + default 2097152 if ESP32S3_SPIRAM_TYPE_ESPPSRAM16 + default 4194304 if ESP32S3_SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if ESP32S3_SPIRAM_TYPE_ESPPSRAM64 + default 16777216 if ESP32S3_SPIRAM_TYPE_ESPPSRAM128 + default 33554432 if ESP32S3_SPIRAM_TYPE_ESPPSRAM256 + default 0 + +config ESP32S3_SPIRAM_FETCH_INSTRUCTIONS + bool "Cache fetch instructions from SPI RAM" + default n + ---help--- + If enabled, instruction in flash will be copied into SPIRAM. + If ESP32S3_SPIRAM_RODATA is also enabled, you can run the instruction + when erasing or programming the flash. + +config ESP32S3_SPIRAM_RODATA + bool "Cache load read only data from SPI RAM" + default n + ---help--- + If enabled, rodata in flash will be copied into SPIRAM. + If ESP32S3_ESP32S2_SPIRAM_FETCH_INSTRUCTIONS is also enabled, + you can run the instruction when erasing or programming the + flash. + +choice ESP32S3_SPIRAM_SPEED + prompt "Set RAM clock speed" + default ESP32S3_SPIRAM_SPEED_40M + ---help--- + Select the speed for the SPI RAM chip. + +config ESP32S3_SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config ESP32S3_SPIRAM_SPEED_80M + bool "80MHz clock speed" + +config ESP32S3_SPIRAM_SPEED_120M + bool "120MHz clock speed" + +endchoice # ESP32S3_SPIRAM_SPEED + +config ESP32S3_SPIRAM_SPEED + int + default 120 if ESP32S3_SPIRAM_SPEED_120M + default 80 if ESP32S3_SPIRAM_SPEED_80M + default 40 if ESP32S3_SPIRAM_SPEED_40M + +config ESP32S3_SPIRAM_BOOT_INIT + bool "Initialize SPI RAM during startup" + depends on ESP32S3_SPIRAM + default y + ---help--- + If this is enabled, the SPI RAM will be enabled during initial + boot. Unless you have specific requirements, you'll want to leave + this enabled so memory allocated during boot-up can also be + placed in SPI RAM. + +config ESP32S3_SPIRAM_IGNORE_NOTFOUND + bool "Ignore PSRAM when not found" + default n + depends on ESP32S3_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA + ---help--- + Normally, if psram initialization is enabled during compile time + but not found at runtime, it is seen as an error making the CPU + panic. If this is enabled, booting will complete but no PSRAM + will be available. + +endmenu #SPI RAM Config + config ESP32S3_TIMER0 bool "54-bit Timer 0 (Group 0 Timer 0)" default n diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs index 2854d8c48e..d8e797651a 100644 --- a/arch/xtensa/src/esp32s3/Make.defs +++ b/arch/xtensa/src/esp32s3/Make.defs @@ -117,3 +117,7 @@ CHIP_CSRCS += esp32s3_spiflash_mtd.c endif endif +ifeq ($(CONFIG_ESP32S3_SPIRAM),y) +CHIP_CSRCS += esp32s3_spiram.c +CHIP_CSRCS += esp32s3_psram.c +endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram.c b/arch/xtensa/src/esp32s3/esp32s3_psram.c new file mode 100644 index 0000000000..6a4effc162 --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_psram.c @@ -0,0 +1,557 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_psram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "esp32s3_gpio.h" +#include "esp32s3_psram.h" + +#include "rom/esp32s3_spiflash.h" +#include "rom/esp32s3_opi_flash.h" +#include "hardware/esp32s3_spi_mem_reg.h" +#include "hardware/esp32s3_iomux.h" +#include "hardware/esp32s3_gpio_sigmap.h" + +/* EFUSE */ + +#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0) + +extern uint32_t esp_rom_efuse_get_flash_gpio_info(void); +extern uint32_t esp_rom_efuse_get_flash_wp_gpio(void); + +/* Commands for PSRAM chip */ + +#define PSRAM_READ 0x03 +#define PSRAM_FAST_READ 0x0B +#define PSRAM_FAST_READ_QUAD 0xEB +#define PSRAM_WRITE 0x02 +#define PSRAM_QUAD_WRITE 0x38 +#define PSRAM_ENTER_QMODE 0x35 +#define PSRAM_EXIT_QMODE 0xF5 +#define PSRAM_RESET_EN 0x66 +#define PSRAM_RESET 0x99 +#define PSRAM_SET_BURST_LEN 0xC0 +#define PSRAM_DEVICE_ID 0x9F + +#define PSRAM_FAST_READ_DUMMY 4 +#define PSRAM_FAST_READ_QUAD_DUMMY 6 + +/* ID */ + +#define PSRAM_ID_KGD_M 0xff +#define PSRAM_ID_KGD_S 8 +#define PSRAM_ID_KGD 0x5d +#define PSRAM_ID_EID_M 0xff +#define PSRAM_ID_EID_S 16 + +/* Use the [7:5](bit7~bit5) of EID to distinguish the psram size: + * + * BIT7 | BIT6 | BIT5 | SIZE(MBIT) + * ------------------------------------- + * 0 | 0 | 0 | 16 + * 0 | 0 | 1 | 32 + * 0 | 1 | 0 | 64 + */ + +#define PSRAM_EID_SIZE_M 0x07 +#define PSRAM_EID_SIZE_S 5 + +#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) +#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) +#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) +#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) + +#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) + +/* IO-pins for PSRAM. + * WARNING: PSRAM shares all but the CS and CLK pins with the flash, so + * these defines hardcode the flash pins as well, making this code + * incompatible with either a setup that has the flash on non-standard + * pins or ESP32s with built-in flash. + */ + +#define FLASH_CLK_IO SPI_CLK_GPIO_NUM +#define FLASH_CS_IO SPI_CS0_GPIO_NUM + +/* PSRAM clock and cs IO should be configured based on hardware design. */ + +#define PSRAM_CLK_IO CONFIG_ESP32S3_DEFAULT_PSRAM_CLK_IO /* Default value is 30 */ +#define PSRAM_CS_IO CONFIG_ESP32S3_DEFAULT_PSRAM_CS_IO /* Default value is 26 */ +#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM +#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM +#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM +#define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM + +#define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M +#define CS_FLASH_SEL SPI_MEM_CS0_DIS_M + +#define SPI1_NUM 1 +#define SPI0_NUM 0 + +typedef enum +{ + PSRAM_CMD_QPI, + PSRAM_CMD_SPI, +} psram_cmd_mode_e; + +uint32_t g_psram_id; +uint32_t g_psram_size; /* physical psram size in bytes */ + +static void config_psram_spi_phases(void); + +static uint8_t g_psram_cs_io = UINT8_MAX; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +uint8_t psram_get_cs_io(void) +{ + return g_psram_cs_io; +} + +static void psram_set_op_mode(int spi_num, int mode) +{ + if (mode == PSRAM_CMD_QPI) + { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE); + SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M); + } + else if (mode == PSRAM_CMD_SPI) + { + esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE); + } +} + +static void _psram_exec_cmd(int spi_num, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, uint8_t *mosi_data, + int mosi_bit_len, uint8_t *miso_data, + int miso_bit_len) +{ + esp_rom_spi_cmd_t conf; + uint32_t _addr = addr; + conf.addr = &_addr; + conf.addr_bit_len = addr_bit_len; + conf.cmd = cmd; + conf.cmd_bit_len = cmd_bit_len; + conf.dummy_bit_len = dummy_bits; /* There is a hw approach on chip723 */ + conf.tx_data = (uint32_t *) mosi_data; + conf.tx_data_bit_len = mosi_bit_len; + conf.rx_data = (uint32_t *) miso_data; + conf.rx_data_bit_len = miso_bit_len; + esp_rom_spi_cmd_config(spi_num, &conf); +} + +void psram_exec_cmd(int spi_num, int mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, uint8_t *mosi_data, + int mosi_bit_len, uint8_t *miso_data, + int miso_bit_len, uint32_t cs_mask, + bool is_write_erase_operation) +{ + uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); + uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num)); + uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num)); + uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num)); + + psram_set_op_mode(spi_num, mode); + _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, + addr_bit_len, dummy_bits, mosi_data, + mosi_bit_len, miso_data, miso_bit_len); + + esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, + cs_mask, is_write_erase_operation); + + WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); + WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); + WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); + WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); +} + +/* exit QPI mode(set back to SPI mode) */ + +static void psram_disable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_QPI, + PSRAM_EXIT_QMODE, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* switch psram burst length(32 bytes or 1024 bytes) + * datasheet says it should be 1024 bytes by default + */ + +static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_e mode) +{ + psram_exec_cmd(spi_num, mode, + PSRAM_SET_BURST_LEN, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* send reset command to psram, in spi mode */ + +static void psram_reset_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET_EN, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ + + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_RESET, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int psram_enable_wrap(uint32_t wrap_size) +{ + static uint32_t current_wrap_size; + + if (current_wrap_size == wrap_size) + { + return OK; + } + + switch (wrap_size) + { + case 32: + case 0: + psram_set_wrap_burst_length(1, PSRAM_CMD_QPI); + current_wrap_size = wrap_size; + return OK; + case 16: + case 64: + default: + return -EFAULT; + } +} + +bool psram_support_wrap_size(uint32_t wrap_size) +{ + switch (wrap_size) + { + case 0: + case 32: + return true; + case 16: + case 64: + default: + return false; + } +} + +/* Read ID operation only supports SPI CMD and mode, should issue + * `psram_disable_qio_mode` before calling this + */ + +static void psram_read_id(int spi_num, uint32_t *dev_id) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_DEVICE_ID, 8, /* command and command bit len */ + 0, 24, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + (uint8_t *) dev_id, 24, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +/* enter QPI mode */ + +static void psram_enable_qio_mode(int spi_num) +{ + psram_exec_cmd(spi_num, PSRAM_CMD_SPI, + PSRAM_ENTER_QMODE, 8, /* command and command bit len */ + 0, 0, /* address and address bit len */ + 0, /* dummy bit len */ + NULL, 0, /* tx data and tx bit len */ + NULL, 0, /* rx data and rx bit len */ + CS_PSRAM_SEL, /* cs bit mask */ + false); /* whether is program/erase operation */ +} + +static void psram_set_cs_timing(void) +{ + /* SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time + * registers for PSRAM, so we only need to set SPI0 related registers here + */ + + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), + SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, + SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), + SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, + SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), + SPI_MEM_SPI_SMEM_CS_HOLD_M | + SPI_MEM_SPI_SMEM_CS_SETUP_M); +} + +static void psram_gpio_config(void) +{ + /* WP HD */ + + uint8_t wp_io = PSRAM_SPIWP_SD3_IO; + + /* CS1 */ + + uint8_t cs1_io = PSRAM_CS_IO; + + if (cs1_io == SPI_CS1_GPIO_NUM) + { + esp32s3_gpio_matrix_out(cs1_io, SPICS1_OUT_IDX, 0, 0); + } + else + { + esp32s3_configgpio(cs1_io, OUTPUT); + esp32s3_gpio_matrix_out(cs1_io, SIG_GPIO_OUT_IDX, 0, 0); + } + + g_psram_cs_io = cs1_io; + + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) + { + /* MSPI pins (except wp / hd) are all configured via IO_MUX in 1st + * bootloader. + */ + } + else + { + /* MSPI pins (except wp / hd) are all configured via GPIO matrix in + * 1st bootloader. + */ + + wp_io = esp_rom_efuse_get_flash_wp_gpio(); + } + + /* This ROM function will init both WP and HD pins. */ + + esp_rom_spiflash_select_qio_pins(wp_io, spiconfig); +} + +/* Psram mode init will overwrite original flash speed mode, so that it is + * possible to change psram and flash speed after OTA. + * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. + * It is decided by bootloader, OTA can not change this mode. + */ + +int psram_enable(int mode, int vaddrmode) +{ + assert(mode < PSRAM_CACHE_MAX && \ + "we don't support any other mode for now."); + + psram_gpio_config(); + psram_set_cs_timing(); + + /* enter MSPI slow mode to init PSRAM device registers */ + + /* FIXME: spi_timing_enter_mspi_low_speed_mode(true); */ + + /* We use SPI1 to init PSRAM */ + + psram_disable_qio_mode(SPI1_NUM); + psram_read_id(SPI1_NUM, &g_psram_id); + + if (!PSRAM_IS_VALID(g_psram_id)) + { + /* 16Mbit psram ID read error workaround: + * treat the first read id as a dummy one as the pre-condition, + * Send Read ID command again + */ + + psram_read_id(SPI1_NUM, &g_psram_id); + if (!PSRAM_IS_VALID(g_psram_id)) + { + merr("PSRAM ID read error: 0x%08x", g_psram_id); + return -EFAULT; + } + } + + if (PSRAM_IS_64MBIT_TRIAL(g_psram_id)) + { + g_psram_size = PSRAM_SIZE_8MB; + } + else + { + uint8_t density = PSRAM_SIZE_ID(g_psram_id); + + switch (density) + { + case 0x0: + g_psram_size = PSRAM_SIZE_2MB; + break; + case 0x1: + g_psram_size = PSRAM_SIZE_4MB; + break; + case 0x2: + g_psram_size = PSRAM_SIZE_8MB; + break; + default: + g_psram_size = 0; + } + } + + /* SPI1: send psram reset command */ + + psram_reset_mode(SPI1_NUM); + + /* SPI1: send QPI enable command */ + + psram_enable_qio_mode(SPI1_NUM); + + /* Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 + * PSRAM timing related registers accordingly + */ + + /* FIXME: spi_timing_psram_tuning(); */ + + /* Configure SPI0 PSRAM related SPI Phases */ + + config_psram_spi_phases(); + + /* Back to the high speed mode. Flash/PSRAM clocks are set to the clock + * that user selected. SPI0/1 registers are all set correctly + */ + + /* FIXME: spi_timing_enter_mspi_high_speed_mode(true); */ + + return OK; +} + +/* Configure PSRAM SPI0 phase related registers here according + * to the PSRAM chip requirement + */ + +static void config_psram_spi_phases(void) +{ + /* Config CMD phase */ + + /* Disable dio mode for cache command */ + + CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); + + /* Enable qio mode for cache command */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); + + /* Enable cache read command */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_CACHE_SRAM_USR_RCMD_M); + + /* Enable cache write command */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_CACHE_SRAM_USR_WCMD_M); + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, + SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S); + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, + PSRAM_QUAD_WRITE, + SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); /* 0x38 */ + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, + SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S); + + SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, + PSRAM_FAST_READ_QUAD, + SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); /* 0xEB */ + + /* Config ADDR phase */ + + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_SRAM_ADDR_BITLEN_V, 23, + SPI_MEM_SRAM_ADDR_BITLEN_S); + + /* We set the PSRAM chip required dummy here. If timing tuning is needed, + * the dummy length will be updated in spi_timing_enter_mspi_hs_mode() + */ + + /* Enable cache read dummy */ + + SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_USR_RD_SRAM_DUMMY_M); + + SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), + SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, + (PSRAM_FAST_READ_QUAD_DUMMY - 1), + SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); + + /* ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM */ + + CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); +} + +int psram_get_physical_size(uint32_t *out_size_bytes) +{ + *out_size_bytes = g_psram_size; + return g_psram_size > 0 ? OK : -EINVAL; +} + +/* This function is to get the available physical psram size in bytes. + * + * When ECC is enabled, the available size will be reduced. + * On S3 Quad PSRAM, ECC is not enabled for now. + */ + +int psram_get_available_size(uint32_t *out_size_bytes) +{ + *out_size_bytes = g_psram_size; + return (g_psram_size ? OK : -EINVAL); +} + diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram.h b/arch/xtensa/src/esp32s3/esp32s3_psram.h new file mode 100644 index 0000000000..0c4d381d8f --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_psram.h @@ -0,0 +1,130 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_psram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H +#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H + +#define PSRAM_SIZE_2MB (2 * 1024 * 1024) +#define PSRAM_SIZE_4MB (4 * 1024 * 1024) +#define PSRAM_SIZE_8MB (8 * 1024 * 1024) +#define PSRAM_SIZE_16MB (16 * 1024 * 1024) +#define PSRAM_SIZE_32MB (32 * 1024 * 1024) + +#define PSRAM_CACHE_S80M 1 +#define PSRAM_CACHE_S40M 2 +#define PSRAM_CACHE_MAX 3 + +#define SPIRAM_WRAP_MODE_16B 0 +#define SPIRAM_WRAP_MODE_32B 1 +#define SPIRAM_WRAP_MODE_64B 2 +#define SPIRAM_WRAP_MODE_DISABLE 3 + +/* See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the + * definitions of these modes. Important is that NORMAL works with the app + * CPU cache disabled, but gives huge cache coherency issues when both app + * and pro CPU are enabled. LOWHIGH and EVENODD do not have these coherency + * issues but cannot be used when the app CPU cache is disabled. + */ + +#define PSRAM_VADDR_MODE_NORMAL 0 /* App and Pro CPU use their own flash + * cache for external RAM access + */ + +#define PSRAM_VADDR_MODE_LOWHIGH 1 /* App and Pro CPU share external RAM caches: + * pro CPU has low 2M, app CPU has high 2M + */ + +#define PSRAM_VADDR_MODE_EVENODD 2 /* App and Pro CPU share external RAM caches: + * pro CPU does even 32yte ranges, app does + * odd ones. + */ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: psram_get_physical_size + * + * Description: + * Get the physical psram size in bytes. + * + ****************************************************************************/ + +int psram_get_physical_size(uint32_t *out_size_bytes); + +/**************************************************************************** + * Name: psram_get_available_size + * + * Description: + * Get the available physical psram size in bytes. + * + * If ECC is enabled, available PSRAM size will be 15/16 times its + * physical size. If not, it equals to the physical psram size. + * Note: For now ECC is only enabled on ESP32S3 Octal PSRAM + * + * Input Parameters: + * out_size_bytes - availabe physical psram size in bytes. + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +int psram_get_available_size(uint32_t *out_size_bytes); + +/**************************************************************************** + * Name: psram_get_available_size + * + * Description: + * Enable psram cache + * + * Esp-idf uses this to initialize cache for psram, mapping it into the + * main memory address space. + * + * Input Parameters: + * mode - SPI mode to access psram in. + * vaddrmode - Mode the psram cache works in. + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +int psram_enable(int mode, int vaddrmode); + +/**************************************************************************** + * Name: psram_get_cs_io + * + * Description: + * Get the psram CS IO + * + * Returned Value: + * The psram CS IO pin. + * + ****************************************************************************/ + +uint8_t psram_get_cs_io(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PSRAM_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.c b/arch/xtensa/src/esp32s3/esp32s3_spiram.c new file mode 100644 index 0000000000..0704f33535 --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.c @@ -0,0 +1,383 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_spiram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" +#include "esp32s3_psram.h" +#include "esp32s3_spiram.h" +#include "hardware/esp32s3_soc.h" +#include "hardware/esp32s3_cache_memory.h" +#include "hardware/esp32s3_extmem.h" +#include "hardware/esp32s3_iomux.h" + +#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL + +#if defined(CONFIG_ESP32S3_SPIRAM) + +#if defined(CONFIG_ESP32S3_SPIRAM_SPEED_40M) +# define PSRAM_SPEED PSRAM_CACHE_S40M +#else /* #if CONFIG_ESP32S3_SPIRAM_SPEED_80M */ +# define PSRAM_SPEED PSRAM_CACHE_S80M +#endif + +static bool g_spiram_inited; + +/* These variables are in bytes */ + +static uint32_t g_allocable_vaddr_start; +static uint32_t g_allocable_vaddr_end; +static DRAM_ATTR uint32_t g_mapped_vaddr_start; + +/* Let's export g_mapped_size to export heap */ + +DRAM_ATTR uint32_t g_mapped_size; + +static uint32_t g_instruction_in_spiram; +static uint32_t g_rodata_in_spiram; + +#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS) +static int g_instr_flash2spiram_offs; +static uint32_t g_instr_start_page; +static uint32_t g_instr_end_page; +#endif + +#if defined(CONFIG_ESP32S3_SPIRAM_RODATA) +static int g_rodata_flash2spiram_offs; +static uint32_t g_rodata_start_page; +static uint32_t g_rodata_end_page; +#endif + +#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS) || \ + defined(CONFIG_ES32S3_SPIRAM_RODATA) +static uint32_t page0_mapped; +static uint32_t page0_page = INVALID_PHY_PAGE; +#endif + +/**************************************************************************** + * ROM Function Prototypes + ****************************************************************************/ + +extern void cache_writeback_all(void); +extern uint32_t cache_suspend_dcache(void); +extern void cache_resume_dcache(uint32_t val); +extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, + uint32_t paddr, uint32_t psize, + uint32_t num, uint32_t fixed); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Initially map all psram physical address to virtual address. + * If psram physical size is larger than virtual address range, then only + * map the virtual address range. + */ + +void IRAM_ATTR esp_spiram_init_cache(void) +{ + uint32_t regval; + int ret = psram_get_available_size(&g_mapped_size); + + if (ret != OK) + { + abort(); + } + + merr("Mapped size = %d\n", g_mapped_size); + + if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) < g_mapped_size) + { + /* Decide these logics when there's a real PSRAM with larger size */ + + merr("Virtual address not enough for PSRAM!"); + abort(); + } + + g_mapped_vaddr_start = SOC_EXTRAM_DATA_HIGH - g_mapped_size; + + /* Suspend DRAM Case during configuration */ + + cache_suspend_dcache(); + + cache_dbus_mmu_set(MMU_ACCESS_SPIRAM, g_mapped_vaddr_start, + 0, 64, g_mapped_size >> 16, 0); + + regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); + regval &= ~EXTMEM_DCACHE_SHUT_CORE0_BUS; + putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); + +#if defined(CONFIG_SMP) + regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); + regval &= ~EXTMEM_DCACHE_SHUT_CORE1_BUS; + putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); +#endif + + cache_resume_dcache(0); + + /* Currently no non-heap stuff on ESP32S3 */ + + g_allocable_vaddr_start = g_mapped_vaddr_start; + g_allocable_vaddr_end = SOC_EXTRAM_DATA_HIGH; +} + +/* Simple RAM test. Writes a word every 32 bytes. Takes about a second + * to complete for 4MiB. Returns true when RAM seems OK, false when test + * fails. WARNING: Do not run this before the 2nd cpu has been initialized + * (in a two-core system) or after the heap allocator has taken ownership + * of the memory. + */ + +bool esp_spiram_test(void) +{ + volatile int *spiram = (volatile int *)g_mapped_vaddr_start; + + size_t s = g_mapped_size; + size_t p; + int errct = 0; + int initial_err = -1; + + for (p = 0; p < (s / sizeof(int)); p += 8) + { + spiram[p] = p ^ 0xaaaaaaaa; + } + + for (p = 0; p < (s / sizeof(int)); p += 8) + { + if (spiram[p] != (p ^ 0xaaaaaaaa)) + { + errct++; + if (errct == 1) + { + initial_err = p * sizeof(int); + } + + if (errct < 4) + { + merr("SPI SRAM error@%08x:%08x/%08x \n", &spiram[p], spiram[p], + p ^ 0xaaaaaaaa); + } + } + } + + if (errct != 0) + { + merr("SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", + errct, s / 32, initial_err + SOC_EXTRAM_DATA_LOW); + return false; + } + else + { + minfo("SPI SRAM memory test OK!"); + return true; + } +} + +uint32_t esp_spiram_instruction_access_enabled(void) +{ + return g_instruction_in_spiram; +} + +uint32_t esp_spiram_rodata_access_enabled(void) +{ + return g_rodata_in_spiram; +} + +#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS) +int esp_spiram_enable_instruction_access(void) +{ + /* `pages_for_flash` will be overwritten, however it influences the psram + * size to be added to the heap allocator. + */ + + abort(); +} +#endif + +#if defined(CONFIG_ESP32S3_SPIRAM_RODATA) +int esp_spiram_enable_rodata_access(void) +{ + /* `pages_for_flash` will be overwritten, however it influences the psram + * size to be added to the heap allocator. + */ + + abort(); +} +#endif + +#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS) +void instruction_flash_page_info_init(void) +{ + uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - + SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / + MMU_PAGE_SIZE; + + g_instr_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + + CACHE_IROM_MMU_START); + g_instr_start_page &= MMU_ADDRESS_MASK; + g_instr_end_page = g_instr_start_page + instr_page_cnt - 1; +} + +uint32_t IRAM_ATTR instruction_flash_start_page_get(void) +{ + return g_instr_start_page; +} + +uint32_t IRAM_ATTR instruction_flash_end_page_get(void) +{ + return g_instr_end_page; +} + +int IRAM_ATTR instruction_flash2spiram_offset(void) +{ + return g_instr_flash2spiram_offs; +} +#endif + +#if defined(CONFIG_ESP32_SPIRAM_RODATA) +void rodata_flash_page_info_init(void) +{ + uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - + ((uint32_t)&_rodata_reserved_start & + ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / + MMU_PAGE_SIZE; + + g_rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + + CACHE_DROM_MMU_START); + g_rodata_start_page &= MMU_ADDRESS_MASK; + g_rodata_end_page = g_rodata_start_page + rodata_page_cnt - 1; +} + +uint32_t IRAM_ATTR rodata_flash_start_page_get(void) +{ + return g_rodata_start_page; +} + +uint32_t IRAM_ATTR rodata_flash_end_page_get(void) +{ + return g_rodata_end_page; +} + +int IRAM_ATTR g_rodata_flash2spiram_offset(void) +{ + return g_rodata_flash2spiram_offs; +} +#endif + +int esp_spiram_init(void) +{ + int r; + uint32_t psram_physical_size = 0; + + r = psram_enable(PSRAM_SPEED, PSRAM_MODE); + if (r != OK) + { + merr("SPI RAM enabled but initialization failed. Bailing out.\n"); + return r; + } + + g_spiram_inited = true; + + r = psram_get_physical_size(&psram_physical_size); + if (r != OK) + { + abort(); + } + +#if defined(CONFIG_ESP32S3_SPIRAM_SIZE) && (CONFIG_ESP32S3_SPIRAM_SIZE != -1) + if (psram_physical_size != CONFIG_ESP32S3_SPIRAM_SIZE) + { + merr("Expected %dMB chip but found %dMB chip. Bailing out..", + (CONFIG_ESP32S3_SPIRAM_SIZE / 1024 / 1024), + (psram_physical_size / 1024 / 1024)); + return ; + } +#endif + + minfo("Found %dMB SPI RAM device\n", psram_physical_size / (1024 * 1024)); + minfo("Speed: %dMHz\n", CONFIG_ESP32S3_SPIRAM_SPEED); + minfo("Initialized, cache is in %s mode.\n", + (PSRAM_MODE == PSRAM_VADDR_MODE_EVENODD) ? + "even/odd (2-core)" : + (PSRAM_MODE == PSRAM_VADDR_MODE_LOWHIGH) ? + "low/high (2-core)" : + (PSRAM_MODE == PSRAM_VADDR_MODE_NORMAL) ? + "normal (1-core)" : "ERROR"); + return OK; +} + +size_t esp_spiram_get_size(void) +{ + if (!g_spiram_inited) + { + merr("SPI RAM not initialized"); + abort(); + } + + uint32_t size = 0; /* in bytes */ + int ret = psram_get_available_size(&size); + + return ret == OK ? size : 0; +} + +/* Before flushing the cache, if psram is enabled as a memory-mapped thing, + * we need to write back the data in the cache to the psram first, otherwise + * it will get lost. For now, we just read 64/128K of random PSRAM memory to + * do this. + */ + +void IRAM_ATTR esp_spiram_writeback_cache(void) +{ + cache_writeback_all(); +} + +/** + * @brief If SPI RAM(PSRAM) has been initialized + * + * @return true SPI RAM has been initialized successfully + * @return false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void) +{ + return g_spiram_inited; +} + +uint8_t esp_spiram_get_cs_io(void) +{ + return psram_get_cs_io(); +} + +#endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.h b/arch/xtensa/src/esp32s3/esp32s3_spiram.h new file mode 100644 index 0000000000..b628adb19f --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_spiram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPIRAM_H +#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_SPIRAM_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* @brief Initialize spiram interface/hardware. Normally called from + * cpu_start.c. + * + * @return ESP_OK on success + */ + +int esp_spiram_init(void); + +/** + * @brief Configure Cache/MMU for access to external SPI RAM. + * + * Normally this function is called from cpu_start, if + * CONFIG_SPIRAM_BOOT_INIT option is enabled. Applications which need to + * enable SPI RAM at run time can disable CONFIG_SPIRAM_BOOT_INIT, and + * call this function later. + * + * @attention this function must be called with flash cache disabled. + */ + +void esp_spiram_init_cache(void); + +/** + * @brief Memory test for SPI RAM. Should be called after SPI RAM is + * initialized and (in case of a dual-core system) the app CPU is online. + * This test overwrites the memory with crap, so do not call after e.g. the + * heap allocator has stored important stuff in SPI RAM. + * + * @return true on success, false on failed memory test + */ + +bool esp_spiram_test(void); + +/** + * @brief Add the initialized SPI RAM to the heap allocator. + */ + +int esp_spiram_add_to_heapalloc(void); + +/** + * @brief Get the available physical size of the attached SPI RAM chip + * + * @note If ECC is enabled, the available physical size would be smaller + * than the physical size. See `CONFIG_SPIRAM_ECC_ENABLE` + * + * @return Size in bytes, or 0 if no external RAM chip support compiled in. + */ + +size_t esp_spiram_get_size(void); + +/** + * @brief Force a writeback of the data in the SPI RAM cache. This is to be + * called whenever cache is disabled, because disabling cache on the ESP32 + * discards the data in the SPI RAM cache. + * + * This is meant for use from within the SPI flash code. + */ + +void esp_spiram_writeback_cache(void); + +/** + * @brief If SPI RAM(PSRAM) has been initialized + * + * @return + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void); + +/** + * @brief get psram CS IO + * + * This interface should be called after PSRAM is enabled, otherwise it will + * return an invalid value -1/0xff. + * + * @return psram CS IO or -1/0xff if psram not enabled + */ + +uint8_t esp_spiram_get_cs_io(void); + +/** + * @brief Reserve a pool of internal memory for specific DMA/internal + * allocations + * + * @param size Size of reserved pool in bytes + * + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM when no memory available for pool + */ + +int esp_spiram_reserve_dma_pool(size_t size); + +/** + * @brief If SPI RAM(PSRAM) has been initialized + * + * @return + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void); + +#if defined(CONFIG_ESP32S3_SPIRAM_FETCH_INSTRUCTIONS) + +extern int _instruction_reserved_start; +extern int _instruction_reserved_end; + +/** + * @brief Get the start page number of the instruction in SPI flash + * + * @return start page number + */ + +uint32_t instruction_flash_start_page_get(void); + +/** + * @brief Get the end page number of the instruction in SPI flash + * + * @return end page number + */ + +uint32_t instruction_flash_end_page_get(void); + +/** + * @brief Get the offset of instruction from SPI flash to SPI RAM + * + * @return instruction offset + */ + +int instruction_flash2spiram_offset(void); + +#endif + +#if defined(CONFIG_SPIRAM_RODATA) + +extern int _rodata_reserved_start; +extern int _rodata_reserved_end; + +/** + * @brief Get the start page number of the rodata in SPI flash + * + * @return start page number + */ + +uint32_t rodata_flash_start_page_get(void); + +/** + * @brief Get the end page number of the rodata in SPI flash + * + * @return end page number + */ + +uint32_t rodata_flash_end_page_get(void); + +/** + * @brief Get the offset number of rodata from SPI flash to SPI RAM + * + * @return rodata offset + */ + +int rodata_flash2spiram_offset(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c index 5bec851c52..0e43d14bcf 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_start.c +++ b/arch/xtensa/src/esp32s3/esp32s3_start.c @@ -37,6 +37,7 @@ #include "esp32s3_lowputc.h" #include "esp32s3_clockconfig.h" #include "esp32s3_region.h" +#include "esp32s3_spiram.h" #include "esp32s3_wdt.h" #include "hardware/esp32s3_cache_memory.h" #include "hardware/esp32s3_system.h" @@ -285,6 +286,22 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void) showprogress('A'); +#if defined(CONFIG_ESP32S3_SPIRAM_BOOT_INIT) + if (esp_spiram_init() != OK) + { +# if defined(ESP32S3_SPIRAM_IGNORE_NOTFOUND) + mwarn("SPIRAM Initialization failed!\n"); +# else + PANIC(); +# endif + } + else + { + esp_spiram_init_cache(); + esp_spiram_test(); + } +#endif + /* Initialize onboard resources */ esp32s3_board_initialize(); diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h new file mode 100644 index 0000000000..d80a847c2a --- /dev/null +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h @@ -0,0 +1,3584 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) + +/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: Read flash enable. Read flash operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_READ (BIT(31)) +#define SPI_MEM_FLASH_READ_M (BIT(31)) +#define SPI_MEM_FLASH_READ_V 0x1 +#define SPI_MEM_FLASH_READ_S 31 + +/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Write flash enable. Write enable command will be sent when + * the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_WREN (BIT(30)) +#define SPI_MEM_FLASH_WREN_M (BIT(30)) +#define SPI_MEM_FLASH_WREN_V 0x1 +#define SPI_MEM_FLASH_WREN_S 30 + +/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Write flash disable. Write disable command will be sent when + * the bit is set. The bit will be cleared once the operation done. 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_WRDI (BIT(29)) +#define SPI_MEM_FLASH_WRDI_M (BIT(29)) +#define SPI_MEM_FLASH_WRDI_V 0x1 +#define SPI_MEM_FLASH_WRDI_S 29 + +/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Read JEDEC ID . Read ID command will be sent when the bit is + * set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_RDID (BIT(28)) +#define SPI_MEM_FLASH_RDID_M (BIT(28)) +#define SPI_MEM_FLASH_RDID_V 0x1 +#define SPI_MEM_FLASH_RDID_S 28 + +/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Read status register-1. Read status operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_RDSR (BIT(27)) +#define SPI_MEM_FLASH_RDSR_M (BIT(27)) +#define SPI_MEM_FLASH_RDSR_V 0x1 +#define SPI_MEM_FLASH_RDSR_S 27 + +/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: Write status register enable. Write status operation will + * be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0:disable. + */ + +#define SPI_MEM_FLASH_WRSR (BIT(26)) +#define SPI_MEM_FLASH_WRSR_M (BIT(26)) +#define SPI_MEM_FLASH_WRSR_V 0x1 +#define SPI_MEM_FLASH_WRSR_S 26 + +/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: Page program enable(1 byte ~64 bytes data to be programmed). + * Page program operation will be triggered when the bit is set. The bit + * will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_PP (BIT(25)) +#define SPI_MEM_FLASH_PP_M (BIT(25)) +#define SPI_MEM_FLASH_PP_V 0x1 +#define SPI_MEM_FLASH_PP_S 25 + +/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: Sector erase enable(4KB). Sector erase operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_SE (BIT(24)) +#define SPI_MEM_FLASH_SE_M (BIT(24)) +#define SPI_MEM_FLASH_SE_V 0x1 +#define SPI_MEM_FLASH_SE_S 24 + +/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: Block erase enable(32KB) . Block erase operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_BE (BIT(23)) +#define SPI_MEM_FLASH_BE_M (BIT(23)) +#define SPI_MEM_FLASH_BE_V 0x1 +#define SPI_MEM_FLASH_BE_S 23 + +/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: Chip erase enable. Chip erase operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_CE (BIT(22)) +#define SPI_MEM_FLASH_CE_M (BIT(22)) +#define SPI_MEM_FLASH_CE_V 0x1 +#define SPI_MEM_FLASH_CE_S 22 + +/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: Drive Flash into power down. An operation will be triggered + * when the bit is set. The bit will be cleared once the operation done.1: + * enable 0: disable. + */ + +#define SPI_MEM_FLASH_DP (BIT(21)) +#define SPI_MEM_FLASH_DP_M (BIT(21)) +#define SPI_MEM_FLASH_DP_V 0x1 +#define SPI_MEM_FLASH_DP_S 21 + +/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: This bit combined with SPI_MEM_RESANDRES bit releases Flash + * from the power-down state or high performance mode and obtains the devices + * ID. The bit will be cleared once the operation done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_RES (BIT(20)) +#define SPI_MEM_FLASH_RES_M (BIT(20)) +#define SPI_MEM_FLASH_RES_V 0x1 +#define SPI_MEM_FLASH_RES_S 20 + +/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: Drive Flash into high performance mode. The bit will be + * cleared once the operation done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_HPM (BIT(19)) +#define SPI_MEM_FLASH_HPM_M (BIT(19)) +#define SPI_MEM_FLASH_HPM_V 0x1 +#define SPI_MEM_FLASH_HPM_S 19 + +/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: User define command enable. An operation will be triggered + * when the bit is set. The bit will be cleared once the operation done.1: + * enable 0: disable. + */ + +#define SPI_MEM_USR (BIT(18)) +#define SPI_MEM_USR_M (BIT(18)) +#define SPI_MEM_USR_V 0x1 +#define SPI_MEM_USR_S 18 + +/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: In user mode, it is set to indicate that program/erase + * operation will be triggered. The bit is combined with SPI_MEM_USR bit. The + * bit will be cleared once the operation done.1: enable 0: disable. + */ + +#define SPI_MEM_FLASH_PE (BIT(17)) +#define SPI_MEM_FLASH_PE_M (BIT(17)) +#define SPI_MEM_FLASH_PE_V 0x1 +#define SPI_MEM_FLASH_PE_S 17 + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) + +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: In user mode, it is the memory address. other then the + * bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a + * transfer. + */ + +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) + +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: In hardware 0xEB read operation, ADDR phase and DIN phase + * apply 4 signals(4-bit-mode). + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 + +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: In hardware 0xBB read operation, ADDR phase and DIN phase + * apply 2 signals(2-bit-mode). + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 + +/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: Two bytes data will be written to status register when it is + * set. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_WRSR_2B (BIT(22)) +#define SPI_MEM_WRSR_2B_M (BIT(22)) +#define SPI_MEM_WRSR_2B_V 0x1 +#define SPI_MEM_WRSR_2B_S 22 + +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ + +/* Description: Write protect signal output when SPI is idle. + * 1: output high, + * 0: output low. + */ + +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 + +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: In hardware 0x6B read operation, DIN phase apply 4 + * signals(4-bit-mode). + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 + +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ + +/* Description: The bit is used to set MOSI line polarity, + * 1: high + * 0: low + */ + +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 + +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ + +/* Description: The bit is used to set MISO line polarity + * 1: high + * 0: low + */ + +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 + +/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ + +/* Description: The Device ID is read out to SPI_MEM_RD_STATUS register, this + * bit combine with spi_mem_flash_res bit. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_RESANDRES (BIT(15)) +#define SPI_MEM_RESANDRES_M (BIT(15)) +#define SPI_MEM_RESANDRES_V 0x1 +#define SPI_MEM_RESANDRES_S 15 + +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: In hardware 0x3B read operation, DIN phase apply 2 signals. + * 1: enable + * 0: disable + */ + +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 + +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ + +/* Description: This bit should be set when SPI_MEM_FREAD_QIO, + * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. + */ + +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 + +/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: For SPI1, enable crc32 when writing encrypted data to flash. + * 1: enable + * 0:disable + */ + +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 + +/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: For SPI1, initialize crc32 module before writing encrypted + * data to flash. Active low. + */ + +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 + +/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase. */ + +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 + +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase. */ + +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 + +/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase. */ + +#define SPI_MEM_FCMD_DUAL (BIT(7)) +#define SPI_MEM_FCMD_DUAL_M (BIT(7)) +#define SPI_MEM_FCMD_DUAL_V 0x1 +#define SPI_MEM_FCMD_DUAL_S 7 + +/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. */ + +#define SPI_MEM_FADDR_OCT (BIT(6)) #define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 #define SPI_MEM_FADDR_OCT_S 6 + +/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase. */ + +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 + +/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. */ + +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 + +/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: In the DUMMY phase the signal level of SPI bus is output by + * the SPI0 controller. + */ + +#define SPI_MEM_FDUMMY_OUT (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_V 0x1 +#define SPI_MEM_FDUMMY_OUT_S 3 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) + +/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: SPI0 RX FIFO reset signal. Set this bit and clear it before + * SPI0 transfer starts. + */ + +#define SPI_MEM_RXFIFO_RST (BIT(30)) +#define SPI_MEM_RXFIFO_RST_M (BIT(30)) +#define SPI_MEM_RXFIFO_RST_V 0x1 +#define SPI_MEM_RXFIFO_RST_S 30 + +/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ + +/* Description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits + * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. + */ + +#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF +#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) +#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF +#define SPI_MEM_CS_HOLD_DLY_RES_S 2 + +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) + * is off when CS inactive + * 1: SPI_CLK is delayed one cycle after SPI_CS inactive + * 2: SPI_CLK isdelayed two cycles after SPI_CS inactive + * 3: SPI_CLK is always on. + */ + +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) + +/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: The FSM will be reset. */ + +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 + +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ + +/* Description: These bits are used to set the minimum CS high time tSHSL + * between SPI burst transfer when accesses to flash. tSHSL is + * (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + */ + +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 + +/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC + * bytes mode when accesses flash. + */ + +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 + +/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */ + +/* Description: 1: MSPI skips page corner when accesses flash. 0: Not skip + * page corner when accesses flash. + */ + +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 + +/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ + +/* Description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS + * hold cycle in ECC mode when accessed flash. + */ + +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 + +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ + +/* Description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus + * clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits + * are combined with SPI_MEM_CS_HOLD bit. + */ + +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 + +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ + +/* Description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS + * setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + */ + +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) + +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: When SPI1 access to flash or Ext_RAM, set this bit in + * 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. + */ + +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 + +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = + * f_MSPI_CORE_CLK/(SPI_MEM_CLK_CNT_N + 1) + */ + +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 + +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ + +/* Description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). */ + +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 + +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ + +/* Description: It must equal to the value of SPI_MEM_CLKCNT_N. */ + +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) + +/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +/* Description: Set this bit to enable enable the CMD phase of an + * operation. + */ + +#define SPI_MEM_USR_COMMAND (BIT(31)) +#define SPI_MEM_USR_COMMAND_M (BIT(31)) +#define SPI_MEM_USR_COMMAND_V 0x1 +#define SPI_MEM_USR_COMMAND_S 31 + +/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable enable the ADDR phase of an operation. + */ + +#define SPI_MEM_USR_ADDR (BIT(30)) +#define SPI_MEM_USR_ADDR_M (BIT(30)) +#define SPI_MEM_USR_ADDR_V 0x1 +#define SPI_MEM_USR_ADDR_S 30 + +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable enable the DUMMY phase of an + * operation. + */ + +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 + +/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable enable the DIN phase of a read-data + * operation. + */ + +#define SPI_MEM_USR_MISO (BIT(28)) +#define SPI_MEM_USR_MISO_M (BIT(28)) +#define SPI_MEM_USR_MISO_V 0x1 +#define SPI_MEM_USR_MISO_S 28 + +/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the DOUT phase of an write-data + * operation. + */ + +#define SPI_MEM_USR_MOSI (BIT(27)) +#define SPI_MEM_USR_MOSI_M (BIT(27)) +#define SPI_MEM_USR_MOSI_V 0x1 +#define SPI_MEM_USR_MOSI_S 27 + +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the + * bit is enable. + */ + +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 + +/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: DOUT phase only access to high-part of the buffer + * SPI_MEM_W8_REG~SPI_MEM_W15_REG. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 +#define SPI_MEM_USR_MOSI_HIGHPART_S 25 + +/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: DIN phase only access to high-part of the buffer + * SPI_MEM_W8_REG~SPI_MEM_W15_REG. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 +#define SPI_MEM_USR_MISO_HIGHPART_S 24 + +/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT + * phase in SPI1 write operation. + */ + +#define SPI_MEM_FWRITE_QIO (BIT(15)) +#define SPI_MEM_FWRITE_QIO_M (BIT(15)) +#define SPI_MEM_FWRITE_QIO_V 0x1 +#define SPI_MEM_FWRITE_QIO_S 15 + +/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 + * write operation. + */ + +#define SPI_MEM_FWRITE_DIO (BIT(14)) +#define SPI_MEM_FWRITE_DIO_M (BIT(14)) +#define SPI_MEM_FWRITE_DIO_V 0x1 +#define SPI_MEM_FWRITE_DIO_S 14 + +/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 4-bm in DOUT phase in SPI1 write + * operation. + */ + +#define SPI_MEM_FWRITE_QUAD (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) +#define SPI_MEM_FWRITE_QUAD_V 0x1 +#define SPI_MEM_FWRITE_QUAD_S 13 + +/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable 2-bm in DOUT phase in SPI1 write + * operation. + */ + +#define SPI_MEM_FWRITE_DUAL (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) +#define SPI_MEM_FWRITE_DUAL_V 0x1 +#define SPI_MEM_FWRITE_DUAL_S 12 + +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to + * change the clock mode 0~3 of SPI_CLK. + */ + +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 + +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ + +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 + +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ + +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) + +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ + +/* Description: The length in bits of ADDR phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 + +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ + +/* Description: The SPI_CLK cycle length minus 1 of DUMMY phase. */ + +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) + +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ + +/* Description: The length in bits of CMD phase. The register value shall be + * (bit_num-1) + */ + +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 + +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ + +/* Description: The value of user defined(USR) command. */ + +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) + +/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ + +/* Description: The length in bits of DOUT phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF +#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) +#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MOSI_DBITLEN_S 0 + +#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) + +/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ + +/* Description: The length in bits of DIN phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF +#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) +#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF +#define SPI_MEM_USR_MISO_DBITLEN_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) + +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ + +/* Description: Mode bits in the flash fast read mode it is combined with + * SPI_MEM_FASTRD_MODE bit. + */ + +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 + +/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ + +/* Description: The value is stored when set SPI_MEM_FLASH_RDSR bit and + * SPI_MEM_FLASH_RES bit. + */ + +#define SPI_MEM_STATUS 0x0000FFFF +#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) +#define SPI_MEM_STATUS_V 0xFFFF +#define SPI_MEM_STATUS_S 0 + +#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x30) + +/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The register are the higher 32bits in the 64 bits address + * mode. + */ + +#define SPI_MEM_EXT_ADDR 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S)) +#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) + +/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable auto PER function. Hardware will sent + * out PER command if PES command is sent. + */ + +#define SPI_MEM_AUTO_PER (BIT(11)) +#define SPI_MEM_AUTO_PER_M (BIT(11)) +#define SPI_MEM_AUTO_PER_V 0x1 +#define SPI_MEM_AUTO_PER_S 11 + +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: SPI_CS line keep low when the bit is set. */ + +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 + +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: + * 1: SPI_CLK line is high when MSPI is idle. + * 0: SPI_CLK line is low when MSPI is idle. + */ + +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 + +/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: Ext_RAM is connected to SPI SUBPIN bus. */ + +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 + +/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Flash is connected to SPI SUBPIN bus. */ + +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 + +/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +/* Description: Set this bit to raise high SPI_CS1 pin, which means that the + * SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 + * transfer starts. + */ + +#define SPI_MEM_CS1_DIS (BIT(1)) +#define SPI_MEM_CS1_DIS_M (BIT(1)) +#define SPI_MEM_CS1_DIS_V 0x1 +#define SPI_MEM_CS1_DIS_S 1 + +/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to raise high SPI_CS pin, which means that the + * SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer + * starts. + */ + +#define SPI_MEM_CS0_DIS (BIT(0)) +#define SPI_MEM_CS0_DIS_M (BIT(0)) +#define SPI_MEM_CS0_DIS_V 0x1 +#define SPI_MEM_CS0_DIS_S 0 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) + +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ + +/* Description: For SPI1, the value of crc32. */ + +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) + +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 4-bm in ADDR phase. + */ + +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 + +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 4-bm in DOUT phase. + */ + +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 + +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 4-bm in DIN phase. + */ + +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 + +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 2-bm in ADDR phase. + */ + +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 + +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 2-bm in DOUT phase. + */ + +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 + +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to + * enable 2-bm in DIN phase. + */ + +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 + +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: + * 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. + * 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, + * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and + * SPI_MEM_FASTRD_MODE bits. + */ + +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 + +/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: + * Set this bit to enable SPI1 transfer with 32 bits address. The value of + * SPI_MEM_USR_ADDR_BITLEN should be 31. + */ + +#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 + +/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable Cache's access and SPI0's transfer. */ + +#define SPI_MEM_CACHE_REQ_EN (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_V 0x1 +#define SPI_MEM_CACHE_REQ_EN_S 0 + +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) + +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus + * 1 of DUMMY phase in write data transfer. + */ + +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 + +/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable OPI mode in all SPI0 Ext_RAM + * transfer. + */ + +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 + +/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ + +/* Description: + * 1: The command value of SPI0 write Ext_RAM is + * SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. + * 0: The value is 0x3. + */ + +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 + +/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, it is the length in bits of + * ADDR phase. The register value shall be (bit_num-1). + */ + +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 + +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus + * 1 of DUMMY phase in read data transfer. + */ + +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 + +/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ + +/* Description: + * 1: The command value of SPI0 read Ext_RAM is + * SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. + * 0: The value is 0x2. + */ + +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 + +/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY + * phase in read operations. + */ + +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 + +/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY + * phase in write operations. + */ + +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 + +/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + */ + +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 + +/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM + * transfer. + */ + +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 + +/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable SPI0 read Ext_RAM with 32 bits + * address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + */ + +#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 + +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) + +/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal + * level of SPI bus is output by the SPI0 controller. + */ + +#define SPI_MEM_SDUMMY_OUT (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_V 0x1 +#define SPI_MEM_SDUMMY_OUT_S 22 + +/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * CMD phase. + */ + +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 + +/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * ADDR phase. + */ + +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 + +/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * DOUT phase. + */ + +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 + +/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in + * DIN phase. + */ + +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 + +/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * CMD phase. + */ + +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 + +/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * ADDR phase. + */ + +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 + +/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * DOUT phase. + */ + +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 + +/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in + * DIN phase. + */ + +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 + +/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * CMD phase. + */ + +#define SPI_MEM_SCMD_DUAL (BIT(13)) +#define SPI_MEM_SCMD_DUAL_M (BIT(13)) +#define SPI_MEM_SCMD_DUAL_V 0x1 +#define SPI_MEM_SCMD_DUAL_S 13 + +/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * ADDR phase. + */ + +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 + +/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * DOUT phase. + */ + +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 + +/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in + * DIN phase. + */ + +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 + +/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ + +/* Description: Mode bits when SPI0 accesses to Ext_RAM. */ + +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 + +/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ + +/* Description: SPI_CLK mode bits when SPI0 accesses to Ext_RAM. + * 0: SPI_CLK is off when CS inactive + * 1: SPI_CLK is delayed one cycle after CS inactive + * 2: SPI_CLK is delayed two cycles after CS inactive + * 3: SPI_CLK is always on. + */ + +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 + +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) + +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ + +/* Description: When SPI0 reads Ext_RAM, it is the length in bits of CMD + * phase. The register value shall be (bit_num-1). + */ + +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE: R/W;bitpos:[15:0];default:16'h0; */ + +/* Description: When SPI0 reads Ext_RAM, it is the command value of + * CMD phase. + */ + +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) + +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ + +/* Description: When SPI0 writes Ext_RAM, it is the length in bits of CMD + * phase. The register value shall be (bit_num-1). + */ + +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE: R/W;bitpos:[15:0];default: 16'h0; */ + +/* Description: When SPI0 writes Ext_RAM, it is the command value of + * CMD phase. + */ + +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) + +/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, set this bit in 1-division + * mode, f_SPI_CLK = f_MSPI_CORE_CLK. + */ + +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 + +/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ + +/* Description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = + * f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) + */ + +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 + +/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ + +/* Description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). */ + +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 + +/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ + +/* Description: It must equal to the value of SPI_MEM_SCLKCNT_N. */ + +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) + +/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ + +/* Description: The status of SPI1 state machine. + * 0: idle state(IDLE), + * 1: preparation state(PREP), + * 2: send command state(CMD), + * 3: send address state(ADDR), + * 4: red data state(DIN), + * 5:write data state(DOUT), + * 6: wait state(DUMMY), + * 7: done state(DONE). + */ + +#define SPI_MEM_ST 0x00000007 +#define SPI_MEM_ST_M ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S)) +#define SPI_MEM_ST_V 0x7 +#define SPI_MEM_ST_S 0 + +#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) + +/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF0 0xFFFFFFFF +#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) +#define SPI_MEM_BUF0_V 0xFFFFFFFF +#define SPI_MEM_BUF0_S 0 + +#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) + +/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF1 0xFFFFFFFF +#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) +#define SPI_MEM_BUF1_V 0xFFFFFFFF +#define SPI_MEM_BUF1_S 0 + +#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) + +/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF2 0xFFFFFFFF +#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) +#define SPI_MEM_BUF2_V 0xFFFFFFFF +#define SPI_MEM_BUF2_S 0 + +#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) + +/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF3 0xFFFFFFFF +#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) +#define SPI_MEM_BUF3_V 0xFFFFFFFF +#define SPI_MEM_BUF3_S 0 + +#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) + +/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF4 0xFFFFFFFF +#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) +#define SPI_MEM_BUF4_V 0xFFFFFFFF +#define SPI_MEM_BUF4_S 0 + +#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) + +/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF5 0xFFFFFFFF +#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) +#define SPI_MEM_BUF5_V 0xFFFFFFFF +#define SPI_MEM_BUF5_S 0 + +#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) + +/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF6 0xFFFFFFFF +#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) +#define SPI_MEM_BUF6_V 0xFFFFFFFF +#define SPI_MEM_BUF6_S 0 + +#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) + +/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF7 0xFFFFFFFF +#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) +#define SPI_MEM_BUF7_V 0xFFFFFFFF +#define SPI_MEM_BUF7_S 0 + +#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) + +/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF8 0xFFFFFFFF +#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) +#define SPI_MEM_BUF8_V 0xFFFFFFFF +#define SPI_MEM_BUF8_S 0 + +#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) + +/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF9 0xFFFFFFFF +#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) +#define SPI_MEM_BUF9_V 0xFFFFFFFF +#define SPI_MEM_BUF9_S 0 + +#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) + +/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF10 0xFFFFFFFF +#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) +#define SPI_MEM_BUF10_V 0xFFFFFFFF +#define SPI_MEM_BUF10_S 0 + +#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) + +/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF11 0xFFFFFFFF +#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) +#define SPI_MEM_BUF11_V 0xFFFFFFFF +#define SPI_MEM_BUF11_S 0 + +#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) + +/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF12 0xFFFFFFFF +#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) +#define SPI_MEM_BUF12_V 0xFFFFFFFF +#define SPI_MEM_BUF12_S 0 + +#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) + +/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF13 0xFFFFFFFF +#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) +#define SPI_MEM_BUF13_V 0xFFFFFFFF +#define SPI_MEM_BUF13_S 0 + +#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) + +/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF14 0xFFFFFFFF +#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) +#define SPI_MEM_BUF14_V 0xFFFFFFFF +#define SPI_MEM_BUF14_S 0 + +#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) + +/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_MEM_BUF15 0xFFFFFFFF +#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) +#define SPI_MEM_BUF15_V 0xFFFFFFFF +#define SPI_MEM_BUF15_S 0 + +#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) + +/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ + +/* Description: The dummy cycle length when wait flash idle(RDSR). */ + +#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 + +/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */ + +/* Description: The command value of auto wait flash idle transfer(RDSR). */ + +#define SPI_MEM_WAITI_CMD 0x000000FF +#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) +#define SPI_MEM_WAITI_CMD_V 0xFF +#define SPI_MEM_WAITI_CMD_S 2 + +/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable DUMMY phase in auto wait flash idle + * transfer(RDSR). + */ + +#define SPI_MEM_WAITI_DUMMY (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) +#define SPI_MEM_WAITI_DUMMY_V 0x1 +#define SPI_MEM_WAITI_DUMMY_S 1 + +/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable auto-waiting flash idle operation when + * PP/SE/BE/CE/WRSR/PES command is sent. + */ + +#define SPI_MEM_WAITI_EN (BIT(0)) +#define SPI_MEM_WAITI_EN_M (BIT(0)) +#define SPI_MEM_WAITI_EN_V 0x1 +#define SPI_MEM_WAITI_EN_S 0 + +#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) + +/* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: + * 1: Separate PER flash wait idle and PES flash wait idle. + * 0: Not separate. + */ + +#define SPI_MEM_PESR_IDLE_EN (BIT(5)) +#define SPI_MEM_PESR_IDLE_EN_M (BIT(5)) +#define SPI_MEM_PESR_IDLE_EN_V 0x1 +#define SPI_MEM_PESR_IDLE_EN_S 5 + +/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable PES transfer trigger PES transfer + * option. + */ + +#define SPI_MEM_PES_PER_EN (BIT(4)) +#define SPI_MEM_PES_PER_EN_M (BIT(4)) +#define SPI_MEM_PES_PER_EN_V 0x1 +#define SPI_MEM_PES_PER_EN_S 4 + +/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: Set this bit to add delay time after program erase + * suspend(PES) command is sent. + */ + +#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) +#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 + +/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set this bit to add delay time after program erase resume + * (PER) is sent. + */ + +#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) +#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 +#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 + +/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: program erase suspend bit, program erase suspend operation + * will be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0:disable. + */ + +#define SPI_MEM_FLASH_PES (BIT(1)) +#define SPI_MEM_FLASH_PES_M (BIT(1)) +#define SPI_MEM_FLASH_PES_V 0x1 +#define SPI_MEM_FLASH_PES_S 1 + +/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: program erase resume bit, program erase suspend operation + * will be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_MEM_FLASH_PER (BIT(0)) +#define SPI_MEM_FLASH_PER_M (BIT(0)) +#define SPI_MEM_FLASH_PER_V 0x1 +#define SPI_MEM_FLASH_PER_S 0 + +#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) + +/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */ + +/* Description: Program/Erase suspend command value. */ + +#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) +#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PES_COMMAND_S 9 + +/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */ + +/* Description: Program/Erase resume command value. */ + +#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF +#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) +#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF +#define SPI_MEM_FLASH_PER_COMMAND_S 1 + +/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable auto-suspend function. */ + +#define SPI_MEM_FLASH_PES_EN (BIT(0)) +#define SPI_MEM_FLASH_PES_EN_M (BIT(0)) +#define SPI_MEM_FLASH_PES_EN_V 0x1 +#define SPI_MEM_FLASH_PES_EN_S 0 + +#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) + +/* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) + * SPI_CLK cycles after PES command is sent. + * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after + * PES command is sent. + */ + +#define SPI_MEM_FLASH_PES_DLY_256 (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_256_M (BIT(6)) +#define SPI_MEM_FLASH_PES_DLY_256_V 0x1 +#define SPI_MEM_FLASH_PES_DLY_256_S 6 + +/* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after + * PER command is sent. + * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after + * PER command is sent. + */ + +#define SPI_MEM_FLASH_PER_DLY_256 (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_256_M (BIT(5)) +#define SPI_MEM_FLASH_PER_DLY_256_V 0x1 +#define SPI_MEM_FLASH_PER_DLY_256_S 5 + +/* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK + * cycles after DP command is sent. + * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP + * command is sent. + */ + +#define SPI_MEM_FLASH_DP_DLY_256 (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_256_M (BIT(4)) +#define SPI_MEM_FLASH_DP_DLY_256_V 0x1 +#define SPI_MEM_FLASH_DP_DLY_256_S 4 + +/* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK + * cycles after RES command is sent. + * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after + * RES command is sent. + */ + +#define SPI_MEM_FLASH_RES_DLY_256 (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_256_M (BIT(3)) +#define SPI_MEM_FLASH_RES_DLY_256_V 0x1 +#define SPI_MEM_FLASH_RES_DLY_256_S 3 + +/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: + * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK + * cycles after HPM command is sent. + * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after + * HPM command is sent. + */ + +#define SPI_MEM_FLASH_HPM_DLY_256 (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_256_M (BIT(2)) +#define SPI_MEM_FLASH_HPM_DLY_256_V 0x1 +#define SPI_MEM_FLASH_HPM_DLY_256_S 2 + +/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: The status of flash suspend. This bit is set when PES command + * is sent, and cleared when PER is sent. Only used in SPI1. + */ + +#define SPI_MEM_FLASH_SUS (BIT(0)) +#define SPI_MEM_FLASH_SUS_M (BIT(0)) +#define SPI_MEM_FLASH_SUS_V 0x1 +#define SPI_MEM_FLASH_SUS_S 0 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xA8) + +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ + +/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing + * compensation. Active when SPI_MEM_TIMING_CALI bit is set. + */ + +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for + * all reading operations. + */ + +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 + +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to power on HCLK. When PLL is powered on, the + * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals + * to that of XTAL. + */ + +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xAC) + +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ + +/* Description: SPI_DQS input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) + * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DINS_MODE 0x00000007 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x7 +#define SPI_MEM_DINS_MODE_S 24 + +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ + +/* Description: SPI_IO7 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN7_MODE 0x00000007 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x7 +#define SPI_MEM_DIN7_MODE_S 21 + +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: SPI_IO6 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN6_MODE 0x00000007 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x7 +#define SPI_MEM_DIN6_MODE_S 18 + +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ + +/* Description: SPI_IO5 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. 3: Delay for + * (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative + * edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN5_MODE 0x00000007 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x7 +#define SPI_MEM_DIN5_MODE_S 15 + +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ + +/* Description: SPI_IO4 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN4_MODE 0x00000007 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x7 +#define SPI_MEM_DIN4_MODE_S 12 + +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ + +/* Description: SPI_HD input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) + * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN3_MODE 0x00000007 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x7 +#define SPI_MEM_DIN3_MODE_S 9 + +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ + +/* Description: SPI_WP input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN2_MODE 0x00000007 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x7 +#define SPI_MEM_DIN2_MODE_S 6 + +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ + +/* Description: SPI_Q input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN1_MODE 0x00000007 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x7 +#define SPI_MEM_DIN1_MODE_S 3 + +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ + +/* Description: SPI_D input delay mode. + * 0: No delay. + * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK nega tive edge. + * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o ne + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DIN0_MODE 0x00000007 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x7 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xB0) + +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: SPI_DQS input delay number. */ + +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 + +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ + +/* Description: SPI_IO7 input delay number. */ + +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 + +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ + +/* Description: SPI_IO6 input delay number. */ + +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 + +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ + +/* Description: SPI_IO5 input delay number. */ + +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 + +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ + +/* Description: SPI_IO4 input delay number. */ + +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 + +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ + +/* Description: SPI_HD input delay number. */ + +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 + +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ + +/* Description: SPI_WP input delay number. */ + +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 + +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ + +/* Description: SPI_Q input delay number. */ + +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 + +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: SPI_D input delay number. */ + +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xB4) + +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +/* Description: SPI_DQS output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_DOUTS_MODE_S 8 + +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ + +/* Description: SPI_IO7 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 + +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +/* Description: SPI_IO6 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 + +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +/* Description: SPI_IO5 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 + +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ + +/* Description: SPI_IO4 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 + +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ + +/* Description: SPI_HD output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 + +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +/* Description: SPI_WP output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 + +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ + +/* Description: SPI_Q output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 + +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: SPI_D output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xBC) + +/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN: R/W ;bitpos:[4:2]; default: 3'd0; */ + +/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing + * compensation, when SPI0 accesses to Ext_RAM. Active when + * SPI_SMEM_TIMING_CALI bit is set. + */ + +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 + +/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for + * all reading operations. + */ + +#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 + +/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to power on HCLK. When PLL is powered on, the + * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals + * to that of XTAL. + */ + +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) + +/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ + +/* Description: SPI_DQS input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 + +/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ + +/* Description: SPI_IO7 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 + +/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: SPI_IO6 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (S PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 + +/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ + +/* Description: SPI_IO5 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 + +/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ + +/* Description: SPI_IO4 input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+ 1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 + +/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ + +/* Description: SPI_HD input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 + +/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ + +/* Description: SPI_WP input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 + +/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ + +/* Description: SPI_Q input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 + +/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ + +/* Description: SPI_D input delay mode. + * 0: No delay. + * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. + * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one + * cycle at MSPI_CORE_CLK negative edge. + * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK positive edge. + * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one + * cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) + +/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: SPI_DQS input delay number. */ + +#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 + +/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ + +/* Description: SPI_IO7 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 + +/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ + +/* Description: SPI_IO6 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 + +/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ + +/* Description: SPI_IO5 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 + +/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ + +/* Description: SPI_IO4 input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 + +/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ + +/* Description: SPI_HD input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 + +/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ + +/* Description: SPI_WP input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 + +/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ + +/* Description: SPI_Q input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 + +/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +/* Description: SPI_D input delay number. */ + +#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) + +/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +/* Description: SPI_DQS output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 + +/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ + +/* Description: SPI_IO7 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 + +/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +/* Description: SPI_IO6 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 + +/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +/* Description: SPI_IO5 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 + +/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ + +/* Description: SPI_IO4 output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 + +/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ + +/* Description: SPI_HD output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 + +/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +/* Description: SPI_WP output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 + +/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ + +/* Description: SPI_Q output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 + +/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: SPI_D output delay mode. + * 0: No delay. + * 1: Delay one cycle at MSPI_CORE_CLK negative edge. + */ + +#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 + +#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) + +/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: Set this bit to calculate the error times of MSPI ECC read + * when accesses to flash. + */ + +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN (BIT(8)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M (BIT(8)) +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S 8 + +/* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ + +/* Description: Set the error times of MSPI ECC read to generate MSPI + * SPI_MEM_ECC_ERR_INT interrupt. + */ + +#define SPI_MEM_ECC_ERR_INT_NUM 0x000000FF +#define SPI_MEM_ECC_ERR_INT_NUM_M ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S)) +#define SPI_MEM_ECC_ERR_INT_NUM_V 0xFF +#define SPI_MEM_ECC_ERR_INT_NUM_S 0 + +#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD0) + +/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: These bits show the first MSPI ECC error address when + * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to + * flash/Ext_RAM, including ECC byte error and data error. It is cleared by + * when SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + +#define SPI_MEM_ECC_ERR_ADDR 0xFFFFFFFF +#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) +#define SPI_MEM_ECC_ERR_ADDR_V 0xFFFFFFFF +#define SPI_MEM_ECC_ERR_ADDR_S 0 + +#define SPI_MEM_ECC_ERR_BIT_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) + +/* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */ + +/* Description: This bits show the error times of MSPI ECC read, including + * ECC byte error and data byte error. It is cleared by when + * SPI_MEM_ECC_ERR_INT_CLR bit is set. + */ + +#define SPI_MEM_ECC_ERR_CNT 0x000000FF +#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) +#define SPI_MEM_ECC_ERR_CNT_V 0xFF +#define SPI_MEM_ECC_ERR_CNT_S 17 + +/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */ + +/* Description: It records the first ECC byte error when + * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to + * flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + */ + +#define SPI_MEM_ECC_BYTE_ERR (BIT(16)) +#define SPI_MEM_ECC_BYTE_ERR_M (BIT(16)) +#define SPI_MEM_ECC_BYTE_ERR_V 0x1 +#define SPI_MEM_ECC_BYTE_ERR_S 16 + +/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */ + +/* Description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error + * bit number of ECC byte. + */ + +#define SPI_MEM_ECC_CHK_ERR_BIT 0x00000007 +#define SPI_MEM_ECC_CHK_ERR_BIT_M ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S)) +#define SPI_MEM_ECC_CHK_ERR_BIT_V 0x7 +#define SPI_MEM_ECC_CHK_ERR_BIT_S 13 + +/* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */ + +/* Description: It records the first ECC data error bit number when + * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to + * flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit + * number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + */ + +#define SPI_MEM_ECC_DATA_ERR_BIT 0x0000007F +#define SPI_MEM_ECC_DATA_ERR_BIT_M ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S)) +#define SPI_MEM_ECC_DATA_ERR_BIT_V 0x7F +#define SPI_MEM_ECC_DATA_ERR_BIT_S 6 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0xDC) + +/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ + +/* Description: These bits are used to set the minimum CS high time tSHSL + * between SPI burst transfer when accesses to external RAM. tSHSL is + * (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. + */ + +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 + +/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: Set this bit to calculate the error times of MSPI ECC read + * when accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(24)) +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 24 + +/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC + * bytes mode when accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 + +/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER: R/W;bitpos:[15];default:1'b1 ; */ + +/* Description: + * 1: MSPI skips page corner when accesses to external RAM. + * 0: Not skip page corner when accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 + +/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ + +/* Description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI + * CS hold cycles in ECC mode when accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 + +/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */ + +/* Description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus + * clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits + * are combined with SPI_MEM_CS_HOLD bit. + */ + +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 + +/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */ + +/* Description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS + * setup time. These bits are combined with SPI_MEM_CS_SETUP bit. + */ + +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 + +/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ + +#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 + +/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ + +#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE0) + +/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable HyperRAM address out when accesses to + * flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, + * spi_usr_addr_value[3:1]}. + */ + +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 + +/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable octa_ram address out when accesses to + * flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, + * spi_usr_addr_value[3:1],1'b0}. + */ + +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 + +/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Set this bit to invert SPI_DIFF when accesses to flash. */ + +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 + +/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the vary dummy function in SPI + * HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. + */ + +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 + +/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the input of SPI_DQS signal in SPI + * phases of CMD and ADDR. + */ + +#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 + +/* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the SPI HyperBus mode. */ + +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE (BIT(25)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M (BIT(25)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S 25 + +/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the differential SPI_CLK#. */ + +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 + +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, + * 1: Use internal SPI_CLK as data strobe. + * 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not + * active. + */ + +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE (BIT(22)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 + +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: + * 1: Use internal signal as data strobe, the strobe can not be delayed by + * input timing module. + * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be + * delayed by input timing module + */ + +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 + +/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ + +/* Description: The delay number of data strobe which from memory based on + * SPI_CLK. + */ + +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 + +/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ + +/* Description: Set this bit to mask the first or the last byte in MSPI ECC + * DDR read mode, when accesses to flash. + */ + +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 + +/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ + +/* Description: Set this bit to mask the first or the last byte in MSPI ECC + * DDR write mode, when accesses to flash. + */ + +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 + +/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ + +/* Description: It is the minimum output data length in the panda device. */ + +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 + +/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: the bit is used to disable dual edge in command phase when + * DDR mode. + */ + +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 + +/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder TX data of the word in DDR mode. */ + +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 + +/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder RX data of the word in DDR mode. */ + +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 + +/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable variable dummy cycle in DDRmode. */ + +#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 + +/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: 1: in DDR mode, 0: in SDR mode. */ + +#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE4) + +/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable HyperRAM address out when accesses to + * external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], + * 13'd0, spi_usr_addr_value[3:1]}. + */ + +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 + +/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable octa_ram address out when accesses to + * external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], + * 6'd0, spi_usr_addr_value[3:1], 1'b0}. + */ + +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 + +/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Set this bit to invert SPI_DIFF when accesses to external RAM + */ + +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 + +/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the vary dummy function in SPI + * HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or + * sram. + */ + +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 + +/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the input of SPI_DQS signal in SPI + * phases of CMD and ADDR. + */ + +#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 + +/* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the SPI HyperBus mode. */ + +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE (BIT(25)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M (BIT(25)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S 25 + +/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: Set this bit to enable the differential SPI_CLK#. */ + +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 + +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, + * 1: Use internal SPI_CLK as data strobe. + * 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not + * active. + */ + +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE (BIT(22)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 + +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: + * 1: Use internal signal as data strobe, the strobe can not be delayed by + * input timing module. + * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be + * delayed by input timing module + */ + +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 + +/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ + +/* Description: The delay number of data strobe which from memory based on + * SPI_CLK. + */ + +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 + +/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ + +/* Description: Set this bit to mask the first or the last byte in MSPI ECC + * DDR read mode, when accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 + +/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ + +/* Description: Set this bit to mask the first or the last byte in MSPI ECC + * DDR write mode, when accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 + +/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ + +/* Description: It is the minimum output data length in the ddr psram. */ + +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 + +/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: the bit is used to disable dual edge in CMD phase when ddr + * mode. + */ + +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 + +/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder tx data of the word in spi ddr mode. */ + +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 + +/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: Set the bit to reorder rx data of the word in spi ddr mode. */ + +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 + +/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable variable dummy cycle in spi ddr mode. */ + +#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 + +/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: 1: in ddr mode, 0 in sdr mode */ + +#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0xE8) + +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +/* Description: Register clock gate enable signal. 1: Enable. 0: Disable. */ + +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0xEC) + +/* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ + +/* Description: When the digital system clock selects PLL clock and the + * frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: + * 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. + * 1: MSPI_CORE_CLK is 120MHz. + * 2: MSPI_CORE_CLK is 160MHz. + * 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL + * clock and the frequency of PLL clock is 320MHz, the value of + * SPI_MEM_CORE_CLK_SEL: + * 0: MSPI_CORE_CLK is 80MHz. + * 1: MSPI_CORE_CLK is 80MHz. + * 2: MSPI_CORE_CLK 160MHz. + * 3: Not used. + */ + +#define SPI_MEM_CORE_CLK_SEL 0x00000003 +#define SPI_MEM_CORE_CLK_SEL_M ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S)) +#define SPI_MEM_CORE_CLK_SEL_V 0x3 +#define SPI_MEM_CORE_CLK_SEL_S 0 + +#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xF0) + +/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ + +#define SPI_MEM_ECC_ERR_INT_ENA (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ENA_S 4 + +/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. */ + +#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ENA_S 3 + +/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ + +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S 2 + +/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The enable bit for SPI_MEM_PES_END_INT interrupt. */ + +#define SPI_MEM_PES_END_INT_ENA (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ENA_V 0x1 +#define SPI_MEM_PES_END_INT_ENA_S 1 + +/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The enable bit for SPI_MEM_PER_END_INT interrupt. */ + +#define SPI_MEM_PER_END_INT_ENA (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ENA_V 0x1 +#define SPI_MEM_PER_END_INT_ENA_S 0 + +#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xF4) + +/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + * SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse + * of this bit. + */ + +#define SPI_MEM_ECC_ERR_INT_CLR (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 +#define SPI_MEM_ECC_ERR_INT_CLR_S 4 + +/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ + +#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_CLR_S 3 + +/* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ + +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S 2 + +/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The clear bit for SPI_MEM_PES_END_INT interrupt. */ + +#define SPI_MEM_PES_END_INT_CLR (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) +#define SPI_MEM_PES_END_INT_CLR_V 0x1 +#define SPI_MEM_PES_END_INT_CLR_S 1 + +/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The clear bit for SPI_MEM_PER_END_INT interrupt. */ + +#define SPI_MEM_PER_END_INT_CLR (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) +#define SPI_MEM_PER_END_INT_CLR_V 0x1 +#define SPI_MEM_PER_END_INT_CLR_S 0 + +#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xF8) + +/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When + * APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, + * this bit is triggered when the error times of SPI0/1 ECC read flash are + * equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. + * When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN + * is set, this bit is triggered when the error times of SPI0/1 ECC read + * external RAM are equal or bigger than + * APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and + * APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total + * error times of SPI0/1 ECC read external RAM and flash are equal or bigger + * than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and + * APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. + */ + +#define SPI_MEM_ECC_ERR_INT_RAW (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 +#define SPI_MEM_ECC_ERR_INT_RAW_S 4 + +/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. + * 1: Triggered condition is that chip is loosing power and RTC module sends + * out brown out close flash request to SPI1. After SPI1 sends out suspend + * command to flash, this interrupt is triggered and MSPI returns to idle + * state. + * 0: Others. + */ + +#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_RAW_S 3 + +/* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + * 1: Triggered when SPI1 transfer is done and flash is already idle. When + * WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when + * WRSR/PP/SE/BE/CE is success. + * 0: Others. + */ + +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S 2 + +/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The raw bit for SPI_MEM_PES_END_INT interrupt. + * 1: Triggered when Auto Suspend command (0x75) is sent and flash is + * suspended successfully. + * 0: Others. + */ + +#define SPI_MEM_PES_END_INT_RAW (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) +#define SPI_MEM_PES_END_INT_RAW_V 0x1 +#define SPI_MEM_PES_END_INT_RAW_S 1 + +/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The raw bit for SPI_MEM_PER_END_INT interrupt. + * 1: Triggered when Auto Resume command (0x7A) is sent and flash is + * resumed successfully. + * 0: Others. + */ + +#define SPI_MEM_PER_END_INT_RAW (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) +#define SPI_MEM_PER_END_INT_RAW_V 0x1 +#define SPI_MEM_PER_END_INT_RAW_S 0 + +#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xFC) + +/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ + +#define SPI_MEM_ECC_ERR_INT_ST (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(4)) +#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 +#define SPI_MEM_ECC_ERR_INT_ST_S 4 + +/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ + +#define SPI_MEM_BROWN_OUT_INT_ST (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(3)) +#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 +#define SPI_MEM_BROWN_OUT_INT_ST_S 3 + +/* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ + +#define SPI_MEM_TOTAL_TRANS_END_INT_ST (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ST_M (BIT(2)) +#define SPI_MEM_TOTAL_TRANS_END_INT_ST_V 0x1 +#define SPI_MEM_TOTAL_TRANS_END_INT_ST_S 2 + +/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The status bit for SPI_MEM_PES_END_INT interrupt. */ + +#define SPI_MEM_PES_END_INT_ST (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) +#define SPI_MEM_PES_END_INT_ST_V 0x1 +#define SPI_MEM_PES_END_INT_ST_S 1 + +/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The status bit for SPI_MEM_PER_END_INT interrupt. */ + +#define SPI_MEM_PER_END_INT_ST (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) +#define SPI_MEM_PER_END_INT_ST_V 0x1 +#define SPI_MEM_PER_END_INT_ST_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) + +/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */ + +/* Description: SPI register version. */ + +#define SPI_MEM_DATE 0x007FFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0x7FFFFF +#define SPI_MEM_DATE_S 5 + +/* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: SPI_CLK PAD driver control signal. + * 1: The driver of SPI_CLK PAD is controlled by the bits + * SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. + * 0: The driver of SPI_CLK PAD is controlled by the bits + * IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. + */ + +#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN (BIT(4)) +#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M (BIT(4)) +#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V 0x1 +#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S 4 + +/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ + +/* Description: The driver of SPI_CLK PAD is controlled by the bits + * SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN + * is set and MSPI accesses to flash. + */ + +#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV 0x00000003 +#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V) << \ + (SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S)) +#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V 0x3 +#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S 2 + +/* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ + +/* Description: The driver of SPI_CLK PAD is controlled by the bits + * SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN + * is set and MSPI accesses to external RAM. + */ + +#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV 0x00000003 +#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S)) +#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V 0x3 +#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S 0 + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H */ diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h new file mode 100644 index 0000000000..e8e2919b0f --- /dev/null +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h @@ -0,0 +1,378 @@ +/***************************************************************************** + * arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H +#define __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef struct +{ + uint8_t mode; + uint8_t cmd_bit_len; + uint16_t cmd; + uint32_t addr; + uint8_t addr_bit_len; + uint8_t dummy_bit_len; + uint8_t data_bit_len; + uint8_t cs_sel: 4; + uint8_t is_pe: 4; +} esp_rom_opiflash_cmd_t; + +typedef struct +{ + uint8_t addr_bit_len; + uint8_t dummy_bit_len; + uint16_t cmd; + uint8_t cmd_bit_len; + uint8_t var_dummy_en; +} esp_rom_opiflash_spi0rd_t; + +typedef struct +{ + esp_rom_opiflash_cmd_t rdid; + esp_rom_opiflash_cmd_t rdsr; + esp_rom_opiflash_cmd_t wren; + esp_rom_opiflash_cmd_t se; + esp_rom_opiflash_cmd_t be64k; + esp_rom_opiflash_cmd_t read; + esp_rom_opiflash_cmd_t pp; + esp_rom_opiflash_spi0rd_t cache_rd_cmd; +} esp_rom_opiflash_def_t; + +typedef struct +{ + uint16_t cmd; /* !< Command value */ + uint16_t cmd_bit_len; /* !< Command byte length */ + uint32_t *addr; /* !< Point to address value */ + uint32_t addr_bit_len; /* !< Address byte length */ + uint32_t *tx_data; /* !< Point to send data buffer */ + uint32_t tx_data_bit_len; /* !< Send data byte length. */ + uint32_t *rx_data; /* !< Point to recevie data buffer */ + uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */ + uint32_t dummy_bit_len; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +/* Definition of MX25UM25645G Octa Flash + * SPI status register + */ + +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | ESP_ROM_SPIFLASH_BP1 | ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +/* FLASH commands */ + +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +/* Definitions for GigaDevice GD25LX256E Flash */ + +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def; + +/** + * @brief init legacy driver for Octal Flash + */ + +void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t + *flash_cmd_def); + +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ + +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase + * operation, since the CPU would check permission + */ + +void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, + uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ + +void esp_rom_opiflash_pin_config(void); + +/** + * @brief Set SPI read/write operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ + +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ + +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ + +void esp_rom_opiflash_mode_reset(int spi_num); + +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase + * flash operation + */ + +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t *mosi_data, int mosi_bit_len, + uint8_t *miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ + +void esp_rom_opiflash_soft_reset(int spi_num, + esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash ID + * @note command format would be defined in initialization + * @param[out] out_id buffer to accept id + * @return flash operation result + */ + +esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id); + +/** + * @brief to read opi flash status register + * @note command format would be defined in initialization + * @return opi flash status value + */ + +uint8_t esp_rom_opiflash_rdsr(void); + +/** + * @brief wait opi flash status register to be idle + * @note command format would be defined in initialization + * @return flash operation result + */ + +esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void); + +/** + * @brief to erase flash sector + * @note command format would be defined in initialization + * @param sector_num the sector to be erased + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_erase_sector(uint32_t sector_num); + +/** + * @brief to erase flash block + * @note command format would be defined in initialization + * @param block_num the block to be erased + * @return flash operation result + */ + +esp_rom_spiflash_result_t +esp_rom_opiflash_erase_block_64k(uint32_t block_num); + +/** + * @brief to erase a flash area define by start address and length + * @note command format would be defined in initialization + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @return flash operation result + */ + +esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, + uint32_t area_len); + +/** + * @brief to read data from opi flash + * @note command format would be defined in initialization + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ + +esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, + void *data_addr, + int len); + +/** + * @brief to write data to opi flash + * @note command format would be defined in initialization + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ + +esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, + const uint32_t *data_addr, + int len); + +/** + * @brief send WREN command + * @note command format would be defined in initialization + * @param arg not used, set to NULL + * @return flash operation result + */ + +esp_rom_spiflash_result_t esp_rom_opiflash_wren(void *arg); + +/** + * @brief to configure SPI0 read flash command format for cache + * @note command format would be defined in initialization + * + */ + +void +esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, + const esp_rom_opiflash_spi0rd_t *cache); + +esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, + uint8_t *buf, int len); + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H */ diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld index 8b418aa778..5ff5fb3887 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld +++ b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld @@ -384,7 +384,7 @@ PROVIDE( Cache_WriteBack_Addr = 0x400016c8 ); PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 ); PROVIDE( cache_invalidate_dcache_all = 0x400016e0 ); PROVIDE( Cache_Clean_All = 0x400016ec ); -PROVIDE( Cache_WriteBack_All = 0x400016f8 ); +PROVIDE( cache_writeback_all = 0x400016f8 ); PROVIDE( Cache_Mask_All = 0x40001704 ); PROVIDE( Cache_UnMask_Dram0 = 0x40001710 ); PROVIDE( Cache_Suspend_ICache_Autoload = 0x4000171c ); @@ -442,7 +442,7 @@ PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40001980 ); PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c ); PROVIDE( Cache_MMU_Init = 0x40001998 ); PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 ); -PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 ); +PROVIDE( cache_dbus_mmu_set = 0x400019b0 ); PROVIDE( Cache_Count_Flash_Pages = 0x400019bc ); PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 ); PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 );