mpfs/spi: adapt to sysreg define changes
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3e6b19dfc5
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dc54ba924e
@ -1332,25 +1332,21 @@ static void mpfs_spi_init(struct spi_dev_s *dev)
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if (priv->id == 0)
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if (priv->id == 0)
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{
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{
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0,
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0, SYSREG_SOFT_RESET_CR_SPI0);
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(1 << SYSREG_SOFT_RESET_CR_SPI0));
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, SYSREG_SOFT_RESET_CR_SPI0, 0);
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(1 << SYSREG_SOFT_RESET_CR_SPI0), 0);
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
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(1 << SYSREG_SUBBLK_CLOCK_CR_SPI0));
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SYSREG_SUBBLK_CLOCK_CR_SPI0);
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}
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}
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else
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else
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{
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{
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0,
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, 0, SYSREG_SOFT_RESET_CR_SPI1);
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(1 << SYSREG_SOFT_RESET_CR_SPI1));
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR,
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modifyreg32(MPFS_SYSREG_SOFT_RESET_CR, SYSREG_SOFT_RESET_CR_SPI1, 0);
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(1 << SYSREG_SOFT_RESET_CR_SPI1), 0);
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR, 0,
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(1 << SYSREG_SUBBLK_CLOCK_CR_SPI1));
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SYSREG_SUBBLK_CLOCK_CR_SPI1);
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}
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}
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/* Reset the device */
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/* Reset the device */
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@ -1399,14 +1395,12 @@ static void mpfs_spi_deinit(struct spi_dev_s *dev)
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if (priv->id == 0)
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if (priv->id == 0)
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{
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{
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR,
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR,
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(1 << SYSREG_SUBBLK_CLOCK_CR_SPI0),
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SYSREG_SUBBLK_CLOCK_CR_SPI0, 0);
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0);
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}
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}
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else
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else
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{
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{
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR,
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modifyreg32(MPFS_SYSREG_SUBBLK_CLOCK_CR,
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(1 << SYSREG_SUBBLK_CLOCK_CR_SPI1),
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SYSREG_SUBBLK_CLOCK_CR_SPI1, 0);
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0);
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}
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}
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priv->frequency = 0;
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priv->frequency = 0;
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