Add SAM3U interrupt vector logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2475 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -1,4 +1,4 @@
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/****************************************************************************
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/****************************************************************************************
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* arch/arm/include/sam3u/irq.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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@ -31,7 +31,7 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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****************************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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@ -40,33 +40,119 @@
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#ifndef __ARCH_ARM_INCLUDE_SAM3U_IRQ_H
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#define __ARCH_ARM_INCLUDE_SAM3U_IRQ_H
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/****************************************************************************
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/****************************************************************************************
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* Included Files
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****************************************************************************/
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****************************************************************************************/
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/****************************************************************************
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/****************************************************************************************
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* Definitions
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****************************************************************************/
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****************************************************************************************/
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/* SAM3U Interrupts */
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/* SAM3U Peripheral Identifiers */
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#define NR_IRQS (0) /* For now *.
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#define SAM3U_PID_SUPC (0) /* Supply Controller */
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#define SAM3U_PID_RSTC (1) /* Reset Controller */
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#define SAM3U_PID_RTC (2) /* Real Time Clock */
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#define SAM3U_PID_RTT (3) /* Real Time Timer */
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#define SAM3U_PID_WDT (4) /* Watchdog Timer */
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#define SAM3U_PID_PMC (5) /* Power Management Controller */
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#define SAM3U_PID_EEFC0 (6) /* Enhanced Embedded Flash Controller 0 */
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#define SAM3U_PID_EEFC1 (7) /* Enhanced Embedded Flash Controller 1 */
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#define SAM3U_PID_UART (8) /* Universal Asynchronous Receiver Transmitter */
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#define SAM3U_PID_SMC (9) /* Static Memory Controller */
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#define SAM3U_PID_PIOA (10) /* Parallel I/O Controller A */
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#define SAM3U_PID_PIOB (11) /* Parallel I/O Controller B */
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#define SAM3U_PID_PIOC (12) /* Parallel I/O Controller C */
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#define SAM3U_PID_USART0 (13) /* USART 0 */
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#define SAM3U_PID_USART1 (14) /* USART 1 */
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#define SAM3U_PID_USART2 (15) /* USART 2 */
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#define SAM3U_PID_USART3 (16) /* USART 3 */
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#define SAM3U_PID_HSMCI (17) /* High Speed Multimedia Card Interface */
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#define SAM3U_PID_TWI0 (18) /* Two-Wire Interface 0 */
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#define SAM3U_PID_TWI1 (19) /* Two-Wire Interface 1 */
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#define SAM3U_PID_SPI (20) /* Serial Peripheral Interface */
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#define SAM3U_PID_SSC (21) /* Synchronous Serial Controller */
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#define SAM3U_PID_TC0 (22) /* Timer Counter 0 */
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#define SAM3U_PID_TC1 (23) /* Timer Counter 1 */
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#define SAM3U_PID_TC2 (24) /* Timer Counter 2 */
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#define SAM3U_PID_PWM (25) /* Pulse Width Modulation Controller */
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#define SAM3U_PID_ADC12B (26) /* 12-bit ADC Controller */
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#define SAM3U_PID_ADC (27) /* 10-bit ADC Controller */
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#define SAM3U_PID_DMAC (28) /* DMA Controller */
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#define SAM3U_PID_UDPHS (29) /* USB Device High Speed */
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#define NR_PIDS (30) /* Number of peripheral identifiers */
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/****************************************************************************
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define SAM3U_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define SAM3U_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define SAM3U_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define SAM3U_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */
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#define SAM3U_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define SAM3U_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define SAM3U_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define SAM3U_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define SAM3U_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define SAM3U_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16) */
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#define SAM3U_IRQ_EXTINT (16)
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#define SAM3U_IRQ_SUPC (SAM3U_IRQ_EXTINT+SAM3U_PID_SUPC) /* Supply Controller */
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#define SAM3U_IRQ_RSTC (SAM3U_IRQ_EXTINT+SAM3U_PID_RSTC) /* Reset Controller */
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#define SAM3U_IRQ_RTC (SAM3U_IRQ_EXTINT+SAM3U_PID_RTC) /* Real Time Clock */
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#define SAM3U_IRQ_RTT (SAM3U_IRQ_EXTINT+SAM3U_PID_RTT) /* Real Time Timer */
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#define SAM3U_IRQ_WDT (SAM3U_IRQ_EXTINT+SAM3U_PID_WDT) /* Watchdog Timer */
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#define SAM3U_IRQ_PMC (SAM3U_IRQ_EXTINT+SAM3U_PID_PMC) /* Power Management Controller */
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#define SAM3U_IRQ_EEFC0 (SAM3U_IRQ_EXTINT+SAM3U_PID_EEFC0) /* Enhanced Embedded Flash Controller 0 */
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#define SAM3U_IRQ_EEFC1 (SAM3U_IRQ_EXTINT+SAM3U_PID_EEFC1) /* Enhanced Embedded Flash Controller 1 */
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#define SAM3U_IRQ_UART (SAM3U_IRQ_EXTINT+SAM3U_PID_UART) /* Universal Asynchronous Receiver Transmitter */
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#define SAM3U_IRQ_SMC (SAM3U_IRQ_EXTINT+SAM3U_PID_SMC) /* Static Memory Controller */
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#define SAM3U_IRQ_PIOA (SAM3U_IRQ_EXTINT+SAM3U_PID_PIOA) /* Parallel I/O Controller A */
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#define SAM3U_IRQ_PIOB (SAM3U_IRQ_EXTINT+SAM3U_PID_PIOB) /* Parallel I/O Controller B */
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#define SAM3U_IRQ_PIOC (SAM3U_IRQ_EXTINT+SAM3U_PID_PIOC) /* Parallel I/O Controller C */
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#define SAM3U_IRQ_USART0 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART0) /* USART 0 */
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#define SAM3U_IRQ_USART1 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART1) /* USART 1 */
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#define SAM3U_IRQ_USART2 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART2) /* USART 2 */
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#define SAM3U_IRQ_USART3 (SAM3U_IRQ_EXTINT+SAM3U_PID_USART3) /* USART 3 */
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#define SAM3U_IRQ_HSMCI (SAM3U_IRQ_EXTINT+SAM3U_PID_HSMCI) /* High Speed Multimedia Card Interface */
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#define SAM3U_IRQ_TWI0 (SAM3U_IRQ_EXTINT+SAM3U_PID_TWI0) /* Two-Wire Interface 0 */
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#define SAM3U_IRQ_TWI1 (SAM3U_IRQ_EXTINT+SAM3U_PID_TWI1) /* Two-Wire Interface 1 */
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#define SAM3U_IRQ_SPI (SAM3U_IRQ_EXTINT+SAM3U_PID_SPI) /* Serial Peripheral Interface */
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#define SAM3U_IRQ_SSC (SAM3U_IRQ_EXTINT+SAM3U_PID_SSC) /* Synchronous Serial Controller */
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#define SAM3U_IRQ_TC0 (SAM3U_IRQ_EXTINT+SAM3U_PID_TC0) /* Timer Counter 0 */
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#define SAM3U_IRQ_TC1 (SAM3U_IRQ_EXTINT+SAM3U_PID_TC1) /* Timer Counter 1 */
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#define SAM3U_IRQ_TC2 (SAM3U_IRQ_EXTINT+SAM3U_PID_TC2) /* Timer Counter 2 */
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#define SAM3U_IRQ_PWM (SAM3U_IRQ_EXTINT+SAM3U_PID_PWM) /* Pulse Width Modulation Controller */
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#define SAM3U_IRQ_ADC12B (SAM3U_IRQ_EXTINT+SAM3U_PID_ADC12B) /* 12-bit ADC Controller */
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#define SAM3U_IRQ_ADC (SAM3U_IRQ_EXTINT+SAM3U_PID_ADC) /* 10-bit ADC Controller */
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#define SAM3U_IRQ_DMAC (SAM3U_IRQ_EXTINT+SAM3U_PID_DMAC) /* DMA Controller */
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#define SAM3U_IRQ_UDPHS (SAM3U_IRQ_EXTINT+SAM3U_PID_UDPHS) /* USB Device High Speed */
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#define NR_IRQS (SAM3U_IRQ_EXTINT+NR_PIDS) /* Total number of IRQ numbers */
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/****************************************************************************************
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* Public Types
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****************************************************************************/
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****************************************************************************************/
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/****************************************************************************
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/****************************************************************************************
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* Inline functions
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****************************************************************************/
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****************************************************************************************/
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/****************************************************************************
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/****************************************************************************************
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* Public Variables
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****************************************************************************/
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****************************************************************************************/
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/****************************************************************************
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/****************************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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****************************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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@ -33,7 +33,7 @@
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#
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############################################################################
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HEAD_ASRC =
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HEAD_ASRC = sam3u_vectors.S
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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@ -56,30 +56,30 @@
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#define SAM3U_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
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# define SAM3U_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: SRAM0 */
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# define SAM3U_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: SRAM1 */
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# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NFC (SRAM) */
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# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: UDPHS (DMA) */
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# define SAM3U_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x207fffff: NAND FLASH controller (SRAM) */
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# define SAM3U_UDPHPSDMS_BASE 0x20180000 /* 0x20180000-0x201fffff: USB Device High Speed (DMA) */
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/* 0x20200000-0x2fffffff: Undefined */
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# define SAM3U_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
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/* 0x24000000-0x3fffffff: Undefined */
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#define SAM3U_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
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# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: MCI */
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# define SAM3U_SSC_BASE 0x40000400 /* 0x40000400-0x400007ff: SSC */
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# define SAM3U_SPI_BASE 0x40000800 /* 0x40000800-0x40000bff: SPI */
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# define SAM3U_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
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# define SAM3U_SSC_BASE 0x40000400 /* 0x40000400-0x400007ff: Synchronous Serial Controller */
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# define SAM3U_SPI_BASE 0x40000800 /* 0x40000800-0x40000bff: Serial Peripheral Interface */
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/* 0x40000c00-0x4007ffff: Reserved */
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# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: TC0 */
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# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: TC1 */
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# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: TC2 */
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# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: TWI0 */
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# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: TWI1 */
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# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: PWM */
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# define SAM3U_TC0_BASE 0x40080000 /* 0x40080000-0x4008003f: Timer Counter 0 */
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# define SAM3U_TC1_BASE 0x40080040 /* 0x40080040-0x4008007f: Timer Counter 1 */
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# define SAM3U_TC2_BASE 0x40080080 /* 0x40080080-0x400800bf: Timer Counter 2 */
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# define SAM3U_TWI0_BASE 0x40084000 /* 0x40084000-0x40087fff: Two-Wire Interface 0 */
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# define SAM3U_TWI1_BASE 0x40088000 /* 0x40088000-0x4008bfff: Two-Wire Interface 1 */
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# define SAM3U_PWM_BASE 0x4008c000 /* 0x4008c000-0x4008ffff: Pulse Width Modulation Controller */
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# define SAM3U_USART0_BASE 0x40090000 /* 0x40090000-0x40093fff: USART0 */
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# define SAM3U_USART1_BASE 0x40094000 /* 0x40094000-0x40097fff: USART1 */
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# define SAM3U_USART2_BASE 0x40098000 /* 0x40098000-0x4009bfff: USART2 */
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# define SAM3U_USART3_BASE 0x4009c000 /* 0x4009c000-0x4009ffff: USART3 */
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/* 0x400a0000-0x400a3fff: Reserved */
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# define SAM3U_UDPHPS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: UDPHS */
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# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: ADC 12-bit */
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# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: ADC */
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# define SAM3U_UDPHPS_BASE 0x400a4000 /* 0x400a4000-0x400a7fff: USB Device High Speed */
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# define SAM3U_ADC12B_BASE 0x400a8000 /* 0x400a8000-0x400abfff: 12-bit ADC Controller */
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# define SAM3U_ADC_BASE 0x400ac000 /* 0x400ac000-0x400affff: 10-bit ADC Controller */
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# define SAM3U_DMAC_BASE 0x400b0000 /* 0x400b0000-0x400b3fff: DMA controller */
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/* 0x400b4000-0x400dffff: Reserved */
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# define SAM3U_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e25ff: System controller */
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@ -93,28 +93,28 @@
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# define SAM3U_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
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# define SAM3U_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
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/* 0x64000000-0x67ffffff: Reserved */
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# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NFC */
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# define SAM3U_NFC_BASE 0x68000000 /* 0x68000000-0x68ffffff: NAND FLASH controller */
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/* 0x69000000-0x9fffffff: Reserved */
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/* 0xa0000000-0xdfffffff: Reserved */
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#define SAM3U_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
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/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
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#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: SMC */
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#define SAM3U_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
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#define SAM3U_MATRIX_BASE 0x400e0000 /* 0x400e0200-0x400e03ff: MATRIX */
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#define SAM3U_PMC_BASE 0x400e0000 /* 0x400e0400-0x400e05ff: PMC */
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#define SAM3U_PMC_BASE 0x400e0000 /* 0x400e0400-0x400e05ff: Power Management Controller */
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#define SAM3U_UART_BASE 0x400e0000 /* 0x400e0600-0x400e073f: UART */
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#define SAM3U_CHIPID_BASE 0x400e0000 /* 0x400e0740-0x400e07ff: CHIP ID */
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#define SAM3U_EFC0_BASE 0x400e0000 /* 0x400e0800-0x400e09ff: EFC0 */
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#define SAM3U_EFC1_BASE 0x400e0000 /* 0x400e0a00-0x400e0bff: EFC1 */
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#define SAM3U_PIOA_BASE 0x400e0000 /* 0x400e0c00-0x400e0dff: PIOA */
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#define SAM3U_PIOB_BASE 0x400e0000 /* 0x400e0e00-0x400e0fff: PIOB */
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#define SAM3U_PIOC_BASE 0x400e0000 /* 0x400e1000-0x400e11ff: PIOC */
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#define SAM3U_RSTC_BASE 0x400e0000 /* 0x400e1200-0x400e120f: RSTC */
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#define SAM3U_SUPC_BASE 0x400e0000 /* 0x400e1210-0x400e122f: SUPC */
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#define SAM3U_RTT_BASE 0x400e0000 /* 0x400e1230-0x400e124f: RTT */
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#define SAM3U_WDT_BASE 0x400e0000 /* 0x400e1250-0x400e125f: WDT */
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#define SAM3U_RTC_BASE 0x400e0000 /* 0x400e1260-0x400e128f: RTD */
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#define SAM3U_EFC0_BASE 0x400e0000 /* 0x400e0800-0x400e09ff: Enhanced Embedded Flash Controller 0 */
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#define SAM3U_EFC1_BASE 0x400e0000 /* 0x400e0a00-0x400e0bff: Enhanced Embedded Flash Controller 1 */
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#define SAM3U_PIOA_BASE 0x400e0000 /* 0x400e0c00-0x400e0dff: Parallel I/O Controller A */
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#define SAM3U_PIOB_BASE 0x400e0000 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller B */
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#define SAM3U_PIOC_BASE 0x400e0000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller C */
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#define SAM3U_RSTC_BASE 0x400e0000 /* 0x400e1200-0x400e120f: Reset Controller */
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#define SAM3U_SUPC_BASE 0x400e0000 /* 0x400e1210-0x400e122f: Supply Controller */
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#define SAM3U_RTT_BASE 0x400e0000 /* 0x400e1230-0x400e124f: Real Time Timer */
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#define SAM3U_WDT_BASE 0x400e0000 /* 0x400e1250-0x400e125f: Watchdog Timer */
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#define SAM3U_RTC_BASE 0x400e0000 /* 0x400e1260-0x400e128f: Real Time Clock */
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#define SAM3U_GPBR_BASE 0x400e0000 /* 0x400e1290-0x400e13ff: GPBR */
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/* 0x490e1400-0x4007ffff: Reserved */
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339
arch/arm/src/sam3u/sam3u_vectors.S
Executable file
339
arch/arm/src/sam3u/sam3u_vectors.S
Executable file
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/************************************************************************************************
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* arch/arm/src/sam3u/sam3u_vectors.S
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* arch/arm/src/chip/sam3u_vectors.S
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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/************************************************************************************************
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* Preprocessor Definitions
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************************************************************************************************/
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|
||||
/* Memory Map:
|
||||
*
|
||||
* 0x0800:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
|
||||
* Mapped to address 0x0000:0000 at boot time.
|
||||
* 0x0800:3000 - Address of vectors if using bootloader
|
||||
* 0x0803:ffff - End of flash
|
||||
* 0x2000:0000 - Start of SRAM and start of .data (_sdata)
|
||||
* - End of .data (_edata) abd start of .bss (_sbss)
|
||||
* - End of .bss (_ebss) and bottom of idle stack
|
||||
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
|
||||
* 0x2000:ffff - End of SRAM and end of heap
|
||||
*/
|
||||
|
||||
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
|
||||
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
|
||||
|
||||
/* The Cortex-M3 return from interrupt is unusual. We provide the following special
|
||||
* address to the BX instruction. The particular value also forces a return to
|
||||
* thread mode and covers state from the main stack point, the MSP (vs. the MSP).
|
||||
*/
|
||||
|
||||
#define EXC_RETURN 0xfffffff9
|
||||
|
||||
/************************************************************************************************
|
||||
* Global Symbols
|
||||
************************************************************************************************/
|
||||
|
||||
.globl __start
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
.file "sam3u_vectors.S"
|
||||
|
||||
/************************************************************************************************
|
||||
* Macros
|
||||
************************************************************************************************/
|
||||
|
||||
/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
|
||||
* registers on the stack, then branches to an instantantiation of the following
|
||||
* macro. This macro simply loads the IRQ number into R0, then jumps to the common
|
||||
* IRQ handling logic.
|
||||
*/
|
||||
|
||||
.macro HANDLER, label, irqno
|
||||
.thumb_func
|
||||
\label:
|
||||
mov r0, #\irqno
|
||||
b sam3u_common
|
||||
.endm
|
||||
|
||||
/************************************************************************************************
|
||||
* Vectors
|
||||
************************************************************************************************/
|
||||
|
||||
.section .vectors, "ax"
|
||||
.code 16
|
||||
.align 2
|
||||
.globl sam3u_vectors
|
||||
.type sam3u_vectors, function
|
||||
|
||||
sam3u_vectors:
|
||||
|
||||
/* Processor Exceptions */
|
||||
|
||||
.word IDLE_STACK /* Vector 0: Reset stack pointer */
|
||||
.word __start /* Vector 1: Reset vector */
|
||||
.word sam3u_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
.word sam3u_hardfault /* Vector 3: Hard fault */
|
||||
.word sam3u_mpu /* Vector 4: Memory management (MPU) */
|
||||
.word sam3u_busfault /* Vector 5: Bus fault */
|
||||
.word sam3u_usagefault /* Vector 6: Usage fault */
|
||||
.word sam3u_reserved /* Vector 7: Reserved */
|
||||
.word sam3u_reserved /* Vector 8: Reserved */
|
||||
.word sam3u_reserved /* Vector 9: Reserved */
|
||||
.word sam3u_reserved /* Vector 10: Reserved */
|
||||
.word sam3u_svcall /* Vector 11: SVC call */
|
||||
.word sam3u_dbgmonitor /* Vector 12: Debug monitor */
|
||||
.word sam3u_reserved /* Vector 13: Reserved */
|
||||
.word sam3u_pendsv /* Vector 14: Pendable system service request */
|
||||
.word sam3u_systick /* Vector 15: System tick */
|
||||
|
||||
/* External Interrupts */
|
||||
|
||||
.word sam3u_supc /* Vector 16+0: Supply Controller */
|
||||
.word sam3u_rstc /* Vector 16+1: Reset Controller */
|
||||
.word sam3u_rtc /* Vector 16+2: Real Time Clock */
|
||||
.word sam3u_rtt /* Vector 16+3: Real Time Timer */
|
||||
.word sam3u_wdt /* Vector 16+4: Watchdog Timer */
|
||||
.word sam3u_pmc /* Vector 16+5: Power Management Controller */
|
||||
.word sam3u_eefc0 /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
|
||||
.word sam3u_eefc1 /* Vector 16+7: Enhanced Embedded Flash Controller 1 */
|
||||
.word sam3u_uart /* Vector 16+8: Universal Asynchronous Receiver Transmitter */
|
||||
.word sam3u_smc /* Vector 16+9: Static Memory Controller */
|
||||
.word sam3u_pioa /* Vector 16+10: Parallel I/O Controller A */
|
||||
.word sam3u_piob /* Vector 16+11: Parallel I/O Controller B */
|
||||
.word sam3u_pioc /* Vector 16+12: Parallel I/O Controller C */
|
||||
.word sam3u_usart0 /* Vector 16+13: USART 0 */
|
||||
.word sam3u_usart1 /* Vector 16+14: USART 1 */
|
||||
.word sam3u_usart2 /* Vector 16+15: USART 2 */
|
||||
.word sam3u_usart3 /* Vector 16+16: USART 3 */
|
||||
.word sam3u_hsmci /* Vector 16+17: High Speed Multimedia Card Interface */
|
||||
.word sam3u_twi0 /* Vector 16+18: Two-Wire Interface 0 */
|
||||
.word sam3u_twi1 /* Vector 16+19: Two-Wire Interface 1 */
|
||||
.word sam3u_spi /* Vector 16+20: Serial Peripheral Interface */
|
||||
.word sam3u_ssc /* Vector 16+21: Synchronous Serial Controller */
|
||||
.word sam3u_tc0 /* Vector 16+22: Timer Counter 0 */
|
||||
.word sam3u_tc1 /* Vector 16+23: Timer Counter 1 */
|
||||
.word sam3u_tc2 /* Vector 16+24: Timer Counter 2 */
|
||||
.word sam3u_pwm /* Vector 16+25: Pulse Width Modulation Controller */
|
||||
.word sam3u_adc12b /* Vector 16+26: 12-bit ADC Controller */
|
||||
.word sam3u_adc /* Vector 16+27: 10-bit ADC Controller */
|
||||
.word sam3u_dmac /* Vector 16+28: DMA Controller */
|
||||
.word sam3u_udphs /* Vector 16+29: USB Device High Speed */
|
||||
.size sam3u_vectors, .-sam3u_vectors
|
||||
|
||||
/************************************************************************************************
|
||||
* .text
|
||||
************************************************************************************************/
|
||||
|
||||
.text
|
||||
.type handlers, function
|
||||
.thumb_func
|
||||
handlers:
|
||||
HANDLER sam3u_reserved, SAM3U_IRQ_RESERVED /* Unexpected/reserved vector */
|
||||
HANDLER sam3u_nmi, SAM3U_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
HANDLER sam3u_hardfault, SAM3U_IRQ_HARDFAULT /* Vector 3: Hard fault */
|
||||
HANDLER sam3u_mpu, SAM3U_IRQ_MPU /* Vector 4: Memory management (MPU) */
|
||||
HANDLER sam3u_busfault, SAM3U_IRQ_BUSFAULT /* Vector 5: Bus fault */
|
||||
HANDLER sam3u_usagefault, SAM3U_IRQ_USAGEFAULT /* Vector 6: Usage fault */
|
||||
HANDLER sam3u_svcall, SAM3U_IRQ_SVCALL /* Vector 11: SVC call */
|
||||
HANDLER sam3u_dbgmonitor, SAM3U_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
|
||||
HANDLER sam3u_pendsv, SAM3U_IRQ_PENDSV /* Vector 14: Penable system service request */
|
||||
HANDLER sam3u_systick, SAM3U_IRQ_SYSTICK /* Vector 15: System tick */
|
||||
|
||||
HANDLER sam3u_supc, SAM3U_IRQ_SUPC /* Vector 16+0: Supply Controller */
|
||||
HANDLER sam3u_rstc, SAM3U_IRQ_RSTC /* Vector 16+1: Reset Controller */
|
||||
HANDLER sam3u_rtc, SAM3U_IRQ_RTC /* Vector 16+2: Real Time Clock */
|
||||
HANDLER sam3u_rtt, SAM3U_IRQ_RTT /* Vector 16+3: Real Time Timer */
|
||||
HANDLER sam3u_wdt, SAM3U_IRQ_WDT /* Vector 16+4: Watchdog Timer */
|
||||
HANDLER sam3u_pmc, SAM3U_IRQ_PMC /* Vector 16+5: Power Management Controller */
|
||||
HANDLER sam3u_eefc0, SAM3U_IRQ_EEFC0 /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
|
||||
HANDLER sam3u_eefc1, SAM3U_IRQ_EEFC1 /* Vector 16+7: Enhanced Embedded Flash Controller 1 */
|
||||
HANDLER sam3u_uart, SAM3U_IRQ_UART /* Vector 16+8: Universal Asynchronous Receiver Transmitter */
|
||||
HANDLER sam3u_smc, SAM3U_IRQ_SMC /* Vector 16+9: Static Memory Controller */
|
||||
HANDLER sam3u_pioa, SAM3U_IRQ_PIOA /* Vector 16+10: Parallel I/O Controller A */
|
||||
HANDLER sam3u_piob, SAM3U_IRQ_PIOB /* Vector 16+11: Parallel I/O Controller B */
|
||||
HANDLER sam3u_pioc, SAM3U_IRQ_PIOC /* Vector 16+12: Parallel I/O Controller C */
|
||||
HANDLER sam3u_usart0, SAM3U_IRQ_USART0 /* Vector 16+13: USART 0 */
|
||||
HANDLER sam3u_usart1, SAM3U_IRQ_USART1 /* Vector 16+14: USART 1 */
|
||||
HANDLER sam3u_usart2, SAM3U_IRQ_USART2 /* Vector 16+15: USART 2 */
|
||||
HANDLER sam3u_usart3, SAM3U_IRQ_USART3 /* Vector 16+16: USART 3 */
|
||||
HANDLER sam3u_hsmci, SAM3U_IRQ_HSMCI /* Vector 16+17: High Speed Multimedia Card Interface */
|
||||
HANDLER sam3u_twi0, SAM3U_IRQ_TWI0 /* Vector 16+18: Two-Wire Interface 0 */
|
||||
HANDLER sam3u_twi1, SAM3U_IRQ_TWI1 /* Vector 16+19: Two-Wire Interface 1 */
|
||||
HANDLER sam3u_spi, SAM3U_IRQ_SPI /* Vector 16+20: Serial Peripheral Interface */
|
||||
HANDLER sam3u_ssc, SAM3U_IRQ_SSC /* Vector 16+21: Synchronous Serial Controller */
|
||||
HANDLER sam3u_tc0, SAM3U_IRQ_TC0 /* Vector 16+22: Timer Counter 0 */
|
||||
HANDLER sam3u_tc1, SAM3U_IRQ_TC1 /* Vector 16+23: Timer Counter 1 */
|
||||
HANDLER sam3u_tc2, SAM3U_IRQ_TC2 /* Vector 16+24: Timer Counter 2 */
|
||||
HANDLER sam3u_pwm, SAM3U_IRQ_PWM /* Vector 16+25: Pulse Width Modulation Controller */
|
||||
HANDLER sam3u_adc12b, SAM3U_IRQ_ADC12B /* Vector 16+26: 12-bit ADC Controller */
|
||||
HANDLER sam3u_adc, SAM3U_IRQ_ADC /* Vector 16+27: 10-bit ADC Controller */
|
||||
HANDLER sam3u_dmac, SAM3U_IRQ_DMAC /* Vector 16+28: DMA Controller */
|
||||
HANDLER sam3u_udphs, SAM3U_IRQ_UDPHS /* Vector 16+29: USB Device High Speed */
|
||||
|
||||
/* Common IRQ handling logic. On entry here, the stack is like the following:
|
||||
*
|
||||
* REG_XPSR
|
||||
* REG_R15
|
||||
* REG_R14
|
||||
* REG_R12
|
||||
* REG_R3
|
||||
* REG_R2
|
||||
* REG_R1
|
||||
* MSP->REG_R0
|
||||
*
|
||||
* and R0 contains the IRQ number
|
||||
*/
|
||||
|
||||
sam3u_common:
|
||||
|
||||
/* Complete the context save */
|
||||
|
||||
mrs r1, msp /* R1=The main stack pointer */
|
||||
mov r2, r1 /* R2=Copy of the main stack pointer */
|
||||
add r2, #HW_XCPT_SIZE /* R2=MSP before the interrupt was taken */
|
||||
mrs r3, primask /* R3=Current PRIMASK setting */
|
||||
stmdb r1!, {r2-r11} /* Save the remaining registers plus the SP value */
|
||||
|
||||
/* Disable interrupts, select the stack to use for interrupt handling
|
||||
* and call up_doirq to handle the interrupt
|
||||
*/
|
||||
|
||||
cpsid i /* Disable further interrupts */
|
||||
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will use a special interrupt
|
||||
* stack pointer. The way that this is done here prohibits nested interrupts!
|
||||
* Otherwise, we will re-use the main stack for interrupt level processing.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_INTERRUPTSTACK
|
||||
ld sp, #up_interruptstack_base
|
||||
str r1, [sp, #-4]! /* Save the MSP on the interrupt stack */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
ldr r1, [sp, #+4]! /* Recover R1=main stack pointer */
|
||||
#else
|
||||
mov sp, r1 /* We are using the main stack pointer */
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, sp /* Recover R1=main stack pointer */
|
||||
#endif
|
||||
|
||||
/* On return from up_doirq, R0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
||||
cmp r0, r1 /* Context switch? */
|
||||
beq 1f /* Branch if no context switch */
|
||||
|
||||
/* We are returning with a pending context switch. This case is different
|
||||
* because in this case, the register save structure does not lie on the
|
||||
* stack but, rather, are within a TCB structure. We'll have to copy some
|
||||
* values to the stack.
|
||||
*/
|
||||
|
||||
add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
|
||||
ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
|
||||
ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
|
||||
stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
|
||||
ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
|
||||
b 2f /* Re-join common logic */
|
||||
|
||||
/* We are returning with no context switch. We simply need to "unwind"
|
||||
* the same stack frame that we created
|
||||
*/
|
||||
1:
|
||||
ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */
|
||||
2:
|
||||
msr msp, r1 /* Recover the return MSP value */
|
||||
|
||||
/* Do we need to restore interrupts? */
|
||||
|
||||
tst r3, #1 /* PRIMASK bit 1=1 means that interrupts are masked */
|
||||
bne 3f
|
||||
cpsie i /* Restore interrupts */
|
||||
|
||||
/* Always return with R14 containing the special value that will: (1)
|
||||
* return to thread mode, and (2) continue to use the MSP
|
||||
*/
|
||||
3:
|
||||
ldr r14, =EXC_RETURN /* Load the special value */
|
||||
bx r14 /* And return */
|
||||
.size handlers, .-handlers
|
||||
|
||||
/************************************************************************************************
|
||||
* Name: up_interruptstack/g_userstack
|
||||
*
|
||||
* Description:
|
||||
* Shouldn't happen
|
||||
*
|
||||
************************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.bss
|
||||
.align 4
|
||||
up_interruptstack:
|
||||
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~3)
|
||||
up_interruptstack_base:
|
||||
.size up_interruptstack, .-up_interruptstack
|
||||
#endif
|
||||
|
||||
/************************************************************************************************
|
||||
* .rodata
|
||||
************************************************************************************************/
|
||||
|
||||
.section .rodata, "a"
|
||||
|
||||
/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
|
||||
* of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
|
||||
* and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that
|
||||
* the system boots on and, eventually, becomes the idle, do nothing task that runs
|
||||
* only when there is nothing else to run. The heap continues from there until the
|
||||
* end of memory. See g_heapbase below.
|
||||
*/
|
||||
|
||||
.globl g_heapbase
|
||||
.type g_heapbase, object
|
||||
g_heapbase:
|
||||
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE
|
||||
.size g_heapbase, .-g_heapbase
|
||||
|
||||
.end
|
||||
Loading…
Reference in New Issue
Block a user