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For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and cache broadcasts. Does not fix SMP cache problem.

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This commit is contained in:
Gregory Nutt 2016-12-07 09:06:41 -06:00
parent b9be0279b1
commit dc79e35d65
3 changed files with 27 additions and 3 deletions
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16
arch/arm/src/armv7-a/arm_scu.c
View File

@ -44,6 +44,7 @@
#include "up_arch.h"
#include "cp15_cacheops.h"
#include "sctlr.h"
#include "cache.h"
#include "scu.h"
#ifdef CONFIG_SMP
@ -174,6 +175,7 @@ void arm_enable_smp(int cpu)
*/
cp15_invalidate_dcache_all();
ARM_DSB();
/* Invalidate the L2C-310 -- Missing logic. */
@ -193,16 +195,28 @@ void arm_enable_smp(int cpu)
*/
cp15_invalidate_dcache_all();
ARM_DSB();
/* Wait for the SCU to be enabled by the primary processor -- should
* not be necessary.
*/
}
/* Enable the data cache, set the SMP mode with ACTLR.SMP=1. */
/* Enable the data cache, set the SMP mode with ACTLR.SMP=1.
*
* SMP - Sgnals if the Cortex-A9 processor is taking part in coherency
* or not.
*
* Cortex-A9 also needs ACTLR.FW=1
*
* FW - Cache and TLB maintenance broadcast.
*/
regval = arm_get_actlr();
regval |= ACTLR_SMP;
#ifdef CONFIG_ARCH_CORTEXA9
regval |= ACTLR_FW;
#endif
arm_set_actlr(regval);
regval = arm_get_sctlr();

10
arch/arm/src/armv7-a/cache.h
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@ -50,6 +50,16 @@
* Pre-processor Definitions
************************************************************************************/
/* Intrinsics are used in these inline functions */
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/************************************************************************************
* Inline Functions
************************************************************************************/

4
arch/arm/src/armv7-r/cache.h
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@ -51,7 +51,7 @@
* Pre-processor Definitions
************************************************************************************/
/* intrinsics are used in these inline functions */
/* Intrinsics are used in these inline functions */
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
@ -61,7 +61,7 @@
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/************************************************************************************
/************************************************************************************
* Inline Functions
************************************************************************************/