From dc93c309b563c40ba0c8bd001e2ada378138c29d Mon Sep 17 00:00:00 2001 From: Richard Tucker Date: Thu, 24 Mar 2022 15:41:01 +1100 Subject: [PATCH] boards/risc-v/litex/arty_a7: update README to include building in LITESDCARD peripheral --- boards/risc-v/litex/arty_a7/README.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/boards/risc-v/litex/arty_a7/README.txt b/boards/risc-v/litex/arty_a7/README.txt index 03d5540390..1e20876b71 100644 --- a/boards/risc-v/litex/arty_a7/README.txt +++ b/boards/risc-v/litex/arty_a7/README.txt @@ -5,6 +5,9 @@ 2. Follow instruction on https://github.com/enjoy-digital/litex to build the vexriscv softcore fpga gateware and flash to arty_a7 board + $ cd litex-boards/litex_boards/targets + $ ./digilent_arty.py --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv --cpu-variant=secure --build --load --flash + 3. Configure and build NuttX $ mkdir ./nuttx; cd ./nuttx