Make size of LPC1766 EMAC RAM configurable
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3142 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -57,6 +57,7 @@
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****************************************************************************/
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/* Configuration ************************************************************/
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/* The configured RAM start address must be the beginning of CPU SRAM */
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#if CONFIG_DRAM_START != LPC17_SRAM_BASE
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# warning "CONFIG_DRAM_START is not at LPC17_SRAM_BASE"
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@ -66,6 +67,8 @@
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# define CONFIG_DRAM_END (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
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#endif
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/* The configured RAM size must be less then or equal to the CPU SRAM size */
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#if CONFIG_DRAM_SIZE > LPC17_CPUSRAM_SIZE
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# warning "CONFIG_DRAM_SIZE is larger than the size of CPU SRAM"
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# undef CONFIG_DRAM_SIZE
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@ -76,13 +79,25 @@
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# warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used"
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#endif
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/* Sanity checking */
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#ifdef LPC17_HAVE_BANK0
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# if CONFIG_MM_REGIONS < 2
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# warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
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# if defined(LPC17_BANK0_HEAPSIZE) || defined(LPC17_HAVE_BANK1)
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# if CONFIG_MM_REGIONS < 2
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# warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
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# endif
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# if CONFIG_MM_REGIONS > 2
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# warning "CONFIG_MM_REGIONS > 2: Additional regions handled by application?"
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# endif
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# else
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# if CONFIG_MM_REGIONS > 1
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# warning "CONFIG_MM_REGIONS > 1: This MCU has no available AHB SRAM Bank0/1"
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# endif
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# endif
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#else
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# if CONFIG_MM_REGIONS > 1
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# warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0/1"
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# warning " Other memory regions handled by application?"
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# endif
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#endif
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@ -131,22 +146,44 @@ void up_addregion(void)
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/* Banks 0 and 1 are each 16Kb. If both are present, they occupy a
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* contiguous 32Kb memory region.
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*
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* If Ethernet is enabled, it will take all of bank 0 for packet
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* If Ethernet is enabled, it will take some or all of bank 0 for packet
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* buffering and descriptor tables.
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*/
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#ifdef LPC17_HAVE_BANK0
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# if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && defined(LPC17_NETHCONTROLLERS)
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# ifdef LPC17_HAVE_BANK1
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mm_addregion((FAR void*)LPC17_SRAM_BANK1, LPC17_BANK1_SIZE);
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# endif
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/* We have BANK0 (and, hence, possibly Bank1). Is Bank0 all used for
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* Ethernet packet buffering? Or is there any part of Bank0 available for
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* the heap.
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*/
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# ifdef LPC17_BANK0_HEAPSIZE
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/* Some or all of Bank0 is available for the heap. Is Bank1 present? */
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# ifdef LPC17_HAVE_BANK1
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/* Yes... the heap space available is the unused memory at the end of
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* Bank0 plus all of Bank1.
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*/
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mm_addregion((FAR void*)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE+LPC17_BANK1_SIZE);
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# else
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# ifdef LPC17_HAVE_BANK1
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mm_addregion((FAR void*)LPC17_SRAM_BANK0, LPC17_BANK0_SIZE+LPC17_BANK1_SIZE);
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# else
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mm_addregion((FAR void*)LPC17_SRAM_BANK0, LPC17_BANK0_SIZE);
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# endif
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/* No... only the unused memory at the end of Bank0 is available for the
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* heap/
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*/
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mm_addregion((FAR void*)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE);
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# endif
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# else
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/* Nothing is available in Bank0. Is Bank1 available? */
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# ifdef LPC17_HAVE_BANK1
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mm_addregion((FAR void*)LPC17_SRAM_BANK1, LPC17_BANK1_SIZE);
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# endif
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# endif
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#endif
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}
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#endif
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@ -41,20 +41,36 @@
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************************************************************************************/
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#include <nuttx/config.h>
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#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET)
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#include "chip.h"
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#include "lpc17_memorymap.h"
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/* Does this chip have and ethernet controller? */
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#if LPC17_NETHCONTROLLERS > 0
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Default, no-EMAC Case ************************************************************/
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/* Assume that all of AHB SRAM will be available for heap. If this is not true, then
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* LPC17_BANK0_HEAPSIZE will be undefined and redefined below.
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*/
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/* Configuration ********************************************************************/
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#undef LPC17_BANK0_HEAPBASE
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#undef LPC17_BANK0_HEAPSIZE
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#ifdef LPC17_HAVE_BANK0
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# define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0
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# define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE
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#endif
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/* Is networking enabled? Is the LPC17xx Ethernet device enabled? Does this chip have
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* and Ethernet controlloer? Yes... then we will replace the above default definitions.
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*/
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#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0
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/* EMAC RAM Configuration ***********************************************************/
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/* Is AHB SRAM available? */
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#ifndef LPC17_HAVE_BANK0
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# error "AHB SRAM Bank0 is not available for EMAC RAM"
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#endif
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/* Number of Tx descriptors */
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@ -68,12 +84,43 @@
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# define CONFIG_NET_NRXDESC 18
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#endif
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/* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors. */
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/* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC.
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* This size must fit within AHB SRAM Bank 0 and also be a multiple of 32-bit
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* words.
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*/
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#ifndef CONFIG_NET_EMACRAM_SIZE
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# define CONFIG_NET_EMACRAM_SIZE LPC17_BANK0_SIZE
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#endif
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#if CONFIG_NET_EMACRAM_SIZE > LPC17_BANK0_SIZE
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# error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0"
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#endif
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#if (CONFIG_NET_EMACRAM_SIZE & 3) != 0
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# error "EMAC RAM size must be in multiples of 32-bit words"
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#endif
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/* Determine is there is any meaning space left at the end of AHB Bank 0 that
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* could be added to the heap.
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*/
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#undef LPC17_BANK0_HEAPBASE
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#undef LPC17_BANK0_HEAPSIZE
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#if CONFIG_NET_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128)
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# define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_NET_EMACRAM_SIZE)
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# define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_NET_EMACRAM_SIZE)
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#endif
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/* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx
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* descriptors. The position is not controllable, only the size of the region
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* is controllable.
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*/
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#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0
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#define LPC17_EMACRAM_SIZE LPC17_BANK0_SIZE
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#define LPC17_EMACRAM_SIZE CONFIG_NET_EMACRAM_SIZE
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/* Descriptors Memory Layout ********************************************************/
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/* Descriptor Memory Layout *********************************************************/
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/* EMAC DMA RAM and descriptor definitions. The configured number of descriptors
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* will determine the organization and the size of the descriptor and status tables.
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* There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE)
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@ -90,7 +137,7 @@
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*
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* An example with all of the details:
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*
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* NTXDESC=18 NRXDESC=18 CONFIG_NET_BUFSIZE=420:
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* NTXDESC=18 NRXDESC=18 CONFIG_NET_EMACRAM_SIZE=16Kb CONFIG_NET_BUFSIZE=420:
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* LPC17_TXDESCTAB_SIZE = 18*8 = 144
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* LPC17_TXSTATTAB_SIZE = 18*4 = 72
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* LPC17_TXTAB_SIZE = 216
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@ -191,6 +238,5 @@
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* Public Functions
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************************************************************************************/
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#endif /* LPC17_NETHCONTROLLERS > 0 */
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#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET */
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#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */
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