diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c
index 46d5d9e7a3..5bf4827999 100755
--- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c
+++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c
@@ -57,6 +57,7 @@
  ****************************************************************************/
 
 /* Configuration ************************************************************/
+/* The configured RAM start address must be the beginning of CPU SRAM */
 
 #if CONFIG_DRAM_START != LPC17_SRAM_BASE
 #  warning "CONFIG_DRAM_START is not at LPC17_SRAM_BASE"
@@ -66,6 +67,8 @@
 #  define CONFIG_DRAM_END  (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
 #endif
 
+/* The configured RAM size must be less then or equal to the CPU SRAM size */
+
 #if CONFIG_DRAM_SIZE > LPC17_CPUSRAM_SIZE
 #  warning "CONFIG_DRAM_SIZE is larger than the size of CPU SRAM"
 #  undef CONFIG_DRAM_SIZE
@@ -76,13 +79,25 @@
 #  warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used"
 #endif
 
+/* Sanity checking */
+
 #ifdef LPC17_HAVE_BANK0
-#  if CONFIG_MM_REGIONS < 2
-#    warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
+#  if defined(LPC17_BANK0_HEAPSIZE) || defined(LPC17_HAVE_BANK1)
+#    if CONFIG_MM_REGIONS < 2
+#      warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank(s) not included in HEAP"
+#    endif
+#    if CONFIG_MM_REGIONS > 2
+#      warning "CONFIG_MM_REGIONS > 2: Additional regions handled by application?"
+#    endif
+#  else
+#    if CONFIG_MM_REGIONS > 1
+#      warning "CONFIG_MM_REGIONS > 1: This MCU has no available AHB SRAM Bank0/1"
+#    endif
 #  endif
 #else
 #  if CONFIG_MM_REGIONS > 1
 #    warning "CONFIG_MM_REGIONS > 1: This MCU has no AHB SRAM Bank0/1"
+#    warning "                       Other memory regions handled by application?"
 #  endif
 #endif
 
@@ -131,22 +146,44 @@ void up_addregion(void)
   /* Banks 0 and 1 are each 16Kb.  If both are present, they occupy a
    * contiguous 32Kb memory region.
    *
-   * If Ethernet is enabled, it will take all of bank 0 for packet
+   * If Ethernet is enabled, it will take some or all of bank 0 for packet
    * buffering and descriptor tables.
    */
 
 #ifdef LPC17_HAVE_BANK0
-#  if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && defined(LPC17_NETHCONTROLLERS)
-#    ifdef LPC17_HAVE_BANK1
-       mm_addregion((FAR void*)LPC17_SRAM_BANK1, LPC17_BANK1_SIZE);
-#    endif
+
+  /* We have BANK0 (and, hence, possibly Bank1).  Is Bank0 all used for
+   * Ethernet packet buffering?  Or is there any part of Bank0 available for
+   * the heap.
+   */
+
+# ifdef LPC17_BANK0_HEAPSIZE
+
+  /* Some or all of Bank0 is available for the heap.  Is Bank1 present? */
+
+#  ifdef LPC17_HAVE_BANK1
+
+  /* Yes... the heap space available is the unused memory at the end of
+   * Bank0 plus all of Bank1.
+   */
+
+   mm_addregion((FAR void*)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE+LPC17_BANK1_SIZE);
 #  else
-#    ifdef LPC17_HAVE_BANK1
-       mm_addregion((FAR void*)LPC17_SRAM_BANK0, LPC17_BANK0_SIZE+LPC17_BANK1_SIZE);
-#    else
-       mm_addregion((FAR void*)LPC17_SRAM_BANK0, LPC17_BANK0_SIZE);
-#    endif
+
+   /* No... only the unused memory at the end of Bank0 is available for the
+    * heap/
+    */
+
+   mm_addregion((FAR void*)LPC17_BANK0_HEAPBASE, LPC17_BANK0_HEAPSIZE);
 #  endif
+# else
+
+  /* Nothing is available in Bank0.  Is Bank1 available? */
+
+#  ifdef LPC17_HAVE_BANK1
+   mm_addregion((FAR void*)LPC17_SRAM_BANK1, LPC17_BANK1_SIZE);
+#  endif
+# endif
 #endif
 }
 #endif
diff --git a/arch/arm/src/lpc17xx/lpc17_emacram.h b/arch/arm/src/lpc17xx/lpc17_emacram.h
index 75137084e0..3759ccb9ee 100755
--- a/arch/arm/src/lpc17xx/lpc17_emacram.h
+++ b/arch/arm/src/lpc17xx/lpc17_emacram.h
@@ -41,20 +41,36 @@
  ************************************************************************************/
 
 #include <nuttx/config.h>
-#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET)
-
 #include "chip.h"
 #include "lpc17_memorymap.h"
 
-/* Does this chip have and ethernet controller? */
-
-#if LPC17_NETHCONTROLLERS > 0
-
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
+/* Default, no-EMAC Case ************************************************************/
+/* Assume that all of AHB SRAM will be available for heap. If this is not true, then
+ * LPC17_BANK0_HEAPSIZE will be undefined and redefined below.
+ */
 
-/* Configuration ********************************************************************/
+#undef LPC17_BANK0_HEAPBASE
+#undef LPC17_BANK0_HEAPSIZE
+#ifdef LPC17_HAVE_BANK0
+#  define LPC17_BANK0_HEAPBASE LPC17_SRAM_BANK0
+#  define LPC17_BANK0_HEAPSIZE LPC17_BANK0_SIZE
+#endif
+
+/* Is networking enabled?  Is the LPC17xx Ethernet device enabled? Does this chip have
+ * and Ethernet controlloer?  Yes... then we will replace the above default definitions.
+ */
+
+#if defined(CONFIG_NET) && defined(CONFIG_LPC17_ETHERNET) && LPC17_NETHCONTROLLERS > 0
+
+/* EMAC RAM Configuration ***********************************************************/
+/* Is AHB SRAM available? */
+
+#ifndef LPC17_HAVE_BANK0
+#  error "AHB SRAM Bank0 is not available for EMAC RAM"
+#endif
 
 /* Number of Tx descriptors */
 
@@ -68,12 +84,43 @@
 #  define CONFIG_NET_NRXDESC 18
 #endif
 
-/* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors. */
+/* Size of the region at the beginning of AHB SRAM 0 set set aside for the EMAC.
+ * This size must fit within AHB SRAM Bank 0 and also be a multiple of 32-bit
+ * words.
+ */
+
+#ifndef CONFIG_NET_EMACRAM_SIZE
+#  define CONFIG_NET_EMACRAM_SIZE LPC17_BANK0_SIZE
+#endif
+
+#if CONFIG_NET_EMACRAM_SIZE > LPC17_BANK0_SIZE
+#  error "EMAC RAM size cannot exceed the size of AHB SRAM Bank 0"
+#endif
+
+#if (CONFIG_NET_EMACRAM_SIZE & 3) != 0
+#  error "EMAC RAM size must be in multiples of 32-bit words"
+#endif
+
+/* Determine is there is any meaning space left at the end of AHB Bank 0 that
+ * could be added to the heap.
+ */
+
+#undef LPC17_BANK0_HEAPBASE
+#undef LPC17_BANK0_HEAPSIZE
+#if CONFIG_NET_EMACRAM_SIZE < (LPC17_BANK0_SIZE-128)
+#  define LPC17_BANK0_HEAPBASE (LPC17_SRAM_BANK0 + CONFIG_NET_EMACRAM_SIZE)
+#  define LPC17_BANK0_HEAPSIZE (LPC17_BANK0_SIZE - CONFIG_NET_EMACRAM_SIZE)
+#endif
+
+/* Memory at the beginning of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx
+ * descriptors.  The position is not controllable, only the size of the region
+ * is controllable.
+ */
 
 #define LPC17_EMACRAM_BASE   LPC17_SRAM_BANK0
-#define LPC17_EMACRAM_SIZE   LPC17_BANK0_SIZE
+#define LPC17_EMACRAM_SIZE   CONFIG_NET_EMACRAM_SIZE
 
-/* Descriptors Memory Layout ********************************************************/
+/* Descriptor Memory Layout *********************************************************/
 /* EMAC DMA RAM and descriptor definitions.  The configured number of descriptors
  * will determine the organization and the size of the descriptor and status tables.
  * There is a complex interaction between the maximum packet size (CONFIG_NET_BUFSIZE)
@@ -90,7 +137,7 @@
  *
  * An example with all of the details:
  *
- * NTXDESC=18 NRXDESC=18 CONFIG_NET_BUFSIZE=420:
+ * NTXDESC=18 NRXDESC=18 CONFIG_NET_EMACRAM_SIZE=16Kb CONFIG_NET_BUFSIZE=420:
  *   LPC17_TXDESCTAB_SIZE = 18*8 = 144
  *   LPC17_TXSTATTAB_SIZE = 18*4 =  72
  *   LPC17_TXTAB_SIZE     = 216
@@ -191,6 +238,5 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* LPC17_NETHCONTROLLERS > 0 */
-#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET */
+#endif /* CONFIG_NET && CONFIG_LPC17_ETHERNET && LPC17_NETHCONTROLLERS > 0*/
 #endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMACRAM_H */