Kinetis:Extend clockconfig to support SOPT2_PLLFLLSEL and SIM_CLKDIV3

A board.h file can now specify the:
   1) BOARD_SOPT2_PLLFLLSEL to select the output of the SIM_SOPT2 MUX
     from:
       MCGFLLCLK
       MCGPLLCLK
       USB1PFD
       IRC48MHZ

    2) If it defines BOARD_SIM_CLKDIV3_FREQ then it must define
    BOARD_SIM_CLKDIV3_PLLFLLFRAC and BOARD_SIM_CLKDIV3_PLLFLLDIV
    which wil be used to cpnfigure SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV]
This commit is contained in:
David Sidrane 2017-02-23 19:05:24 -10:00
parent 86c9f97f78
commit dd218ffa8c

View File

@ -2,7 +2,8 @@
* arch/arm/src/kinetis/kinetis_clockconfig.c
*
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane<david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -192,7 +193,8 @@ static inline void kinesis_portclocks(void)
void kinetis_pllconfig(void)
{
#if defined(SIM_SCGC4_LLWU)
#if defined(SIM_SCGC4_LLWU) || defined(BOARD_SOPT2_PLLFLLSEL) || \
defined(BOARD_SIM_CLKDIV3_FREQ)
uint32_t regval32;
#endif
uint8_t regval8;
@ -346,6 +348,27 @@ void kinetis_pllconfig(void)
while ((getreg8(KINETIS_MCG_S) & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
/* We are now running in PLL Engaged External (PEE) mode. */
/* Do we have BOARD_SOPT2_PLLFLLSEL */
#if defined(BOARD_SOPT2_PLLFLLSEL)
/* Set up the SOPT2[PLLFLLSEL] */
regval32 = getreg32(KINETIS_SIM_SOPT2);
regval32 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
regval32 |= BOARD_SOPT2_PLLFLLSEL;
putreg32(regval32, KINETIS_SIM_SOPT2);
#endif
#if defined(BOARD_SIM_CLKDIV3_FREQ)
/* Set up the SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV] */
regval32 = getreg32(KINETIS_SIM_CLKDIV3);
regval32 &= ~(SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK);
regval32 |= (SIM_CLKDIV3_PLLFLLFRAC(BOARD_SIM_CLKDIV3_PLLFLLFRAC) |
SIM_CLKDIV3_PLLFLLDIV(BOARD_SIM_CLKDIV3_PLLFLLDIV));
putreg32(regval32, KINETIS_SIM_CLKDIV3);
#endif
}
/****************************************************************************