Kinetis:Extend clockconfig to support SOPT2_PLLFLLSEL and SIM_CLKDIV3
A board.h file can now specify the: 1) BOARD_SOPT2_PLLFLLSEL to select the output of the SIM_SOPT2 MUX from: MCGFLLCLK MCGPLLCLK USB1PFD IRC48MHZ 2) If it defines BOARD_SIM_CLKDIV3_FREQ then it must define BOARD_SIM_CLKDIV3_PLLFLLFRAC and BOARD_SIM_CLKDIV3_PLLFLLDIV which wil be used to cpnfigure SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV]
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@ -2,7 +2,8 @@
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* arch/arm/src/kinetis/kinetis_clockconfig.c
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*
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* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane<david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -192,7 +193,8 @@ static inline void kinesis_portclocks(void)
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void kinetis_pllconfig(void)
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{
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#if defined(SIM_SCGC4_LLWU)
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#if defined(SIM_SCGC4_LLWU) || defined(BOARD_SOPT2_PLLFLLSEL) || \
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defined(BOARD_SIM_CLKDIV3_FREQ)
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uint32_t regval32;
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#endif
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uint8_t regval8;
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@ -346,6 +348,27 @@ void kinetis_pllconfig(void)
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while ((getreg8(KINETIS_MCG_S) & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
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/* We are now running in PLL Engaged External (PEE) mode. */
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/* Do we have BOARD_SOPT2_PLLFLLSEL */
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#if defined(BOARD_SOPT2_PLLFLLSEL)
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/* Set up the SOPT2[PLLFLLSEL] */
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regval32 = getreg32(KINETIS_SIM_SOPT2);
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regval32 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
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regval32 |= BOARD_SOPT2_PLLFLLSEL;
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putreg32(regval32, KINETIS_SIM_SOPT2);
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#endif
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#if defined(BOARD_SIM_CLKDIV3_FREQ)
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/* Set up the SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV] */
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regval32 = getreg32(KINETIS_SIM_CLKDIV3);
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regval32 &= ~(SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK);
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regval32 |= (SIM_CLKDIV3_PLLFLLFRAC(BOARD_SIM_CLKDIV3_PLLFLLFRAC) |
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SIM_CLKDIV3_PLLFLLDIV(BOARD_SIM_CLKDIV3_PLLFLLDIV));
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putreg32(regval32, KINETIS_SIM_CLKDIV3);
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#endif
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}
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/****************************************************************************
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