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ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 serial shutdown routine. The ROM bootloader does not flush the FIFO before handing over to user code, so some of this output is not currently seen when the UART is reconfigured in early stages of startup. And changes the openocd config file's default flash voltage from 1.8V to 3.3V. This is not necessary right now, but may save some hard-to-debug moments down the track (3.3V-only flash running at 1.8V often half-works and does weird things...)

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This commit is contained in:
Angus Gratton 2016-12-14 08:15:03 -06:00 committed by Gregory Nutt
parent f063e4c5ac
commit dd5e47a418
3 changed files with 15 additions and 8 deletions
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13
arch/xtensa/src/esp32/esp32_serial.c
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@ -586,6 +586,19 @@ static int esp32_setup(struct uart_dev_s *dev)
static void esp32_shutdown(struct uart_dev_s *dev)
{
struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv;
uint32_t status;
/* Wait for outgoing FIFO to clear. The ROM bootloader does not flush
* the FIFO before handing over to user code, so some of this output is
* not currently seen when the UART is reconfigured in early stages of
* startup.
*/
do
{
status = esp32_serialin(priv, UART_STATUS_OFFSET);
}
while ((status & UART_TXFIFO_CNT_M) != 0);
/* Disable all UART interrupts */

6
configs/esp32-core/scripts/esp32.cfg
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@ -44,8 +44,6 @@ source [find target/esp32.cfg]
# voltage greatly.
# Enable this for 1.8V SPI flash
esp108 flashbootstrap 1.8
# esp108 flashbootstrap 1.8
# Enable this for 3.3V SPI flash
#esp108 flashbootstrap 3.3
esp108 flashbootstrap 3.3

4
configs/esp32-core/scripts/esp32_iram.ld
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@ -173,10 +173,6 @@ SECTIONS
_sheap = ABSOLUTE(.);
} >dram0_0_seg
.flash.rodata :
{
} >drom0_0_seg
.rtc.text :
{
. = ALIGN(4);