diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c
index f48b06e304..34846e89e8 100644
--- a/arch/xtensa/src/esp32/esp32_serial.c
+++ b/arch/xtensa/src/esp32/esp32_serial.c
@@ -586,6 +586,19 @@ static int esp32_setup(struct uart_dev_s *dev)
 static void esp32_shutdown(struct uart_dev_s *dev)
 {
   struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv;
+  uint32_t status;
+
+  /* Wait for outgoing FIFO to clear.   The ROM bootloader does not flush
+   * the FIFO before handing over to user code, so some of this output is
+   * not currently seen when the UART is reconfigured in early stages of
+   * startup.
+   */
+
+  do
+    {
+      status = esp32_serialin(priv, UART_STATUS_OFFSET);
+    }
+  while ((status & UART_TXFIFO_CNT_M) != 0);
 
   /* Disable all UART interrupts */
 
diff --git a/configs/esp32-core/scripts/esp32.cfg b/configs/esp32-core/scripts/esp32.cfg
index 0bd581f40a..a9f94d37dc 100644
--- a/configs/esp32-core/scripts/esp32.cfg
+++ b/configs/esp32-core/scripts/esp32.cfg
@@ -44,8 +44,6 @@ source [find target/esp32.cfg]
 # voltage greatly.
 
 # Enable this for 1.8V SPI flash
-esp108 flashbootstrap 1.8
+# esp108 flashbootstrap 1.8
 # Enable this for 3.3V SPI flash
-#esp108 flashbootstrap 3.3
-
-
+esp108 flashbootstrap 3.3
diff --git a/configs/esp32-core/scripts/esp32_iram.ld b/configs/esp32-core/scripts/esp32_iram.ld
index 605ea54e5a..62ed31380b 100644
--- a/configs/esp32-core/scripts/esp32_iram.ld
+++ b/configs/esp32-core/scripts/esp32_iram.ld
@@ -173,10 +173,6 @@ SECTIONS
     _sheap = ABSOLUTE(.);
   } >dram0_0_seg
 
-  .flash.rodata :
-  {
-  } >drom0_0_seg
-
   .rtc.text :
   {
     . = ALIGN(4);