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arch/arm/src/sam34: This commit removes support for the dedicated vector handling from the SAM3/4 architecture support. Only common vectors are now supported.

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This commit is contained in:
Gregory Nutt 2018-06-19 18:13:15 -06:00
parent 01b740c66b
commit dd899c0453
38 changed files with 200 additions and 1318 deletions
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1
arch/arm/Kconfig
View File

@ -259,6 +259,7 @@ config ARCH_CHIP_SAM34
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures

2
arch/arm/src/efm32/Make.defs
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@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/efm32/Make.defs
#
# Copyright (C) 2014-2016 Gregory Nutt. All rights reserved.
# Copyright (C) 2014-2016, 2018 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without

2
arch/arm/src/efm32/chip.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/efm32/chip.h
*
* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011-2014, 2018 Gregory Nutt. All rights reserved.
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Pierre-noel Bouteville <pnb990@gmail.com>

5
arch/arm/src/efm32/efm32_start.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_start.c
*
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -68,6 +68,7 @@
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE
* ARM EBI requires 64 bit stack alignment.
*/
#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
@ -149,7 +150,7 @@ static void go_os_start(void *pv, unsigned int nbytes)
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void efm32_fpuconfig(void)

4
arch/arm/src/efm32/efm32_start.h
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_start.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -51,7 +51,7 @@
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/

8
arch/arm/src/sam34/Make.defs
View File

@ -36,11 +36,7 @@
# The start-up, "head", file
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
HEAD_ASRC =
else
HEAD_ASRC = sam_vectors.S
endif
# Common ARM and Cortex-M3 files
@ -108,10 +104,6 @@ CHIP_CSRCS += sam_start.c
# Configuration-dependent SAM3/4 files
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
CHIP_ASRCS += sam_vectors.S
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif

39
arch/arm/src/sam34/chip.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/sam34/chip.h
*
* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010, 2013-2014, 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -49,42 +49,19 @@
#include <arch/sam34/chip.h>
#include "chip/sam_memorymap.h"
/* If the common ARMv7-M vector handling logic is used, then include the required
* vector definitions as well.
*/
/* Include the chip interrupt definition file */
#ifdef CONFIG_ARMV7M_CMNVECTOR
# if defined(CONFIG_ARCH_CHIP_SAM3U)
# include "chip/sam3u_vectors.h"
# elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# include "chip/sam3x_vectors.h"
# elif defined(CONFIG_ARCH_CHIP_SAM4CM)
# include "chip/sam4cm_vectors.h"
# elif defined(CONFIG_ARCH_CHIP_SAM4E)
# include "chip/sam4e_vectors.h"
# elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "chip/sam4l_vectors.h"
# elif defined(CONFIG_ARCH_CHIP_SAM4S)
# include "chip/sam4s_vectors.h"
# else
# error Unrecognized SAM architecture
# endif
#endif
#include <arch/sam34/irq.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as well.
* The definition SAM_IRQ_NEXTINT simply comes from the chip-specific IRQ header
* file included by arch/sam34/irq.h.
*/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#define ARMV7M_PERIPHERAL_INTERRUPTS SAM_IRQ_NEXTINT
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_H */

87
arch/arm/src/sam34/chip/sam3u_vectors.h
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@ -1,87 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam3u_vectors.h
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* This file is included by sam_vectors.S. It provides the macro VECTOR that
* supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
* sam_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 30 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 30
#else
VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */
VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */
VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */
VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */
VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */
VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */
VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */
VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+9: Static Memory Controller */
VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+10: Parallel I/O Controller A */
VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+11: Parallel I/O Controller B */
VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+12: Parallel I/O Controller C */
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+13: USART 0 */
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+14: USART 1 */
VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+15: USART 2 */
VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+16: USART 3 */
VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+17: High Speed Multimedia Card Interface */
VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+18: Two-Wire Interface 0 */
VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+19: Two-Wire Interface 1 */
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+20: Serial Peripheral Interface */
VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+21: Synchronous Serial Controller */
VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+22: Timer Counter 0 */
VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+23: Timer Counter 1 */
VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+24: Timer Counter 2 */
VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+25: Pulse Width Modulation Controller */
VECTOR(sam_adc12b, SAM_IRQ_ADC12B) /* Vector 16+26: 12-bit ADC Controller */
VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+27: 10-bit ADC Controller */
VECTOR(sam_dmac, SAM_IRQ_DMAC) /* Vector 16+28: DMA Controller */
VECTOR(sam_udphs, SAM_IRQ_UDPHS) /* Vector 16+29: USB Device High Speed */
#endif

102
arch/arm/src/sam34/chip/sam3x_vectors.h
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@ -1,102 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam3x_vectors.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* This file is included by sam_vectors.S. It provides the macro VECTOR that
* supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
* sam_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 45 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 45
#else
VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */
VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */
VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */
VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */
VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */
VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */
VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter */
VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+9: Static Memory Controller */
VECTOR(sam_sdramc, SAM_IRQ_SDRAMC) /* Vector 16+10: Synchronous Dynamic RAM Controller */
VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */
VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */
VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+13: Parallel I/O Controller C */
VECTOR(sam_piod, SAM_IRQ_PIOD) /* Vector 16+14: Parallel I/O Controller D */
VECTOR(sam_pioe, SAM_IRQ_PIOE) /* Vector 16+15: Parallel I/O Controller E */
VECTOR(sam_piof, SAM_IRQ_PIOF) /* Vector 16+16: Parallel I/O Controller F */
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+17: USART 0 */
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+18: USART 1 */
VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+19: USART 2 */
VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+20: USART 3 */
VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+21: High Speed Multimedia Card Interface */
VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+22: Two-Wire Interface 0 */
VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+23: Two-Wire Interface 1 */
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+24: Serial Peripheral Interface 0 */
VECTOR(sam_spi1, SAM_IRQ_SPI1) /* Vector 16+25: Serial Peripheral Interface 1 */
VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+26: Synchronous Serial Controller */
VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+27: Timer Counter 0 */
VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+28: Timer Counter 1 */
VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+29: Timer Counter 2 */
VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+30: Timer Counter 3 */
VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+31: Timer Counter 4 */
VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+32: Timer Counter 5 */
VECTOR(sam_tc6, SAM_IRQ_TC6) /* Vector 16+33: Timer Counter 6 */
VECTOR(sam_tc7, SAM_IRQ_TC7) /* Vector 16+34: Timer Counter 7 */
VECTOR(sam_tc8, SAM_IRQ_TC8) /* Vector 16+35: Timer Counter 8 */
VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+36: Pulse Width Modulation Controller */
VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+37: ADC Controller */
VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+38: DAC Controller */
VECTOR(sam_dmac, SAM_IRQ_DMAC) /* Vector 16+39: DMA Controller */
VECTOR(sam_uotghs, SAM_IRQ_UOTGHS) /* Vector 16+40: USB OTG High Speed */
VECTOR(sam_trng, SAM_IRQ_TRNG) /* Vector 16+41: True Random Number Generator */
VECTOR(sam_emac, SAM_IRQ_EMAC) /* Vector 16+42: Ethernet MAC */
VECTOR(sam_can0, SAM_IRQ_CAN0) /* Vector 16+43: CAN Controller 0 */
VECTOR(sam_can1, SAM_IRQ_CAN1) /* Vector 16+44: CAN Controller 1 */
#endif

101
arch/arm/src/sam34/chip/sam4cm_vectors.h
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@ -1,101 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam4cm_vectors.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* This file is included by sam_vectors.S. It provides the macro VECTOR that
* supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
* sam_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 35 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 35
#else
VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */
VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */
VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */
VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */
VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */
VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
UNUSED(SAM_IRQ_RESERVED_7) /* Vector 16+7: Reserved */
VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */
UNUSED(SAM_IRQ_RESERVED_9) /* Vector 16+9: Reserved */
UNUSED(SAM_IRQ_RESERVED_10) /* Vector 16+10: Unused */
VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */
VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */
UNUSED(SAM_IRQ_RESERVED_13) /* Vector 16+13: Reserved */
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */
VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+16: USART 2 */
VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+17: USART 3 */
UNUSED(SAM_IRQ_RESERVED_18) /* Vector 16+18: Reserved */
VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */
VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+21: Serial Peripheral Interface */
UNUSED(SAM_IRQ_RESERVED_22) /* Vector 16+22: Reserved */
VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */
VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */
VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+25: Timer Counter 2 */
VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+26: Timer Counter 3 */
VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+27: Timer Counter 4 */
VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+28: Timer Counter 5 */
VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+29: Analog To Digital Converter */
VECTOR(sam_arm, SAM_IRQ_ARM) /* Vector 16+30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
VECTOR(sam_ipc0, SAM_IRQ_IPC0) /* Vector 16+31: Interprocessor communication 0 */
VECTOR(sam_slcdc, SAM_IRQ_SLCDC) /* Vector 16+32: Segment LCD Controller */
VECTOR(sam_trng, SAM_IRQ_TRNG) /* Vector 16+33: True Random Generator */
VECTOR(sam_icm, SAM_IRQ_ICM) /* Vector 16+34: Integrity Check Module */
VECTOR(sam_cpkcc, SAM_IRQ_CPKCC) /* Vector 16+35: Classical Public Key Cryptography Controller */
VECTOR(sam_aes, SAM_IRQ_AES) /* Vector 16+36: Advanced Enhanced Standard */
VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+37: Parallel I/O Controller C */
VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+38: Universal Asynchronous Receiver Transmitter 1 */
VECTOR(sam_ipc1, SAM_IRQ_IPC1) /* Vector 16+39: Interprocessor communication 1 */
UNUSED(SAM_IRQ_RESERVED_40) /* Vector 16+40: Reserved */
VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+41: Pulse Width Modulation */
//VECTOR(sam_sram, SAM_IRQ_SRAM) /* Vector 16+42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
//VECTOR(sam_smc1, SAM_IRQ_SMC1) /* Vector 16+43: Static Memory Controller 1 */
#endif

103
arch/arm/src/sam34/chip/sam4e_vectors.h
View File

@ -1,103 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam4e_vectors.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* This file is included by sam_vectors.S. It provides the macro VECTOR that supplies each SAM4E
* vector in terms of a (lower-case) ISR label and an (upper-case) IRQ number as defined in
* arch/arm/include/sam/sam3u_irq.h. sam_vectors.S will defined the VECTOR in different ways in
* order to generate the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 35 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 47
#else
VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */
VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */
VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */
VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */
VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */
VECTOR(sam_eefc0, SAM_PID_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller */
VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+7: Universal Asynchronous Receiver Transmitter 0 */
UNUSED(SAM_IRQ_RESERVED_8) /* Vector 16+8: Static Memory Controller (no vector) */
VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+9: Parallel I/O Controller A */
VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+10: Parallel I/O Controller B */
VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+11: Parallel I/O Controller C */
VECTOR(sam_piod, SAM_IRQ_PIOD) /* Vector 16+12: Parallel I/O Controller C */
VECTOR(sam_pioe, SAM_IRQ_PIOE) /* Vector 16+13: Parallel I/O Controller C */
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */
VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+16: High Speed Multimedia Card Interface */
VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+17: Two-Wire Interface 0 */
VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+18: Two-Wire Interface 1 */
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+19: Serial Peripheral Interface */
VECTOR(sam_dmac, SAM_IRQ_DMAC) /* Vector 16+20: DMA controller */
VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+21: Timer Counter 0 */
VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+22: Timer Counter 1 */
VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+23: Timer Counter 2 */
VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+24: Timer Counter 3 */
VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+25: Timer Counter 4 */
VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+26: Timer Counter 5 */
VECTOR(sam_tc6, SAM_IRQ_TC6) /* Vector 16+27: Timer Counter 6 */
VECTOR(sam_tc7, SAM_IRQ_TC7) /* Vector 16+28: Timer Counter 7 */
VECTOR(sam_tc8, SAM_IRQ_TC8) /* Vector 16+29: Timer Counter 8 */
VECTOR(sam_afec0, SAM_IRQ_AFEC0) /* Vector 16+30: Analog Front End 0 */
VECTOR(sam_afec1, SAM_IRQ_AFEC1) /* Vector 16+31: Analog Front End 1 */
VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+32: Digital To Analog Converter */
VECTOR(sam_acc, SAM_IRQ_ACC) /* Vector 16+33: Analog Comparator */
VECTOR(sam_arm, SAM_IRQ_ARM) /* Vector 16+34: FPU signals: FPIXC, FPOFC, FPUFC, FPIOC, FPDZC,FPIDC, FPIXC */
VECTOR(sam_udp, SAM_IRQ_UDP) /* Vector 16+35: USB Device Port */
VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+36: Pulse Width Modulation */
VECTOR(sam_can0, SAM_IRQ_CAN0) /* Vector 16+37: CAN0 */
VECTOR(sam_can1, SAM_IRQ_CAN1) /* Vector 16+38: CAN1 */
VECTOR(sam_aes, SAM_IRQ_AES) /* Vector 16+39: AES */
UNUSED(SAM_IRQ_RESERVED_40) /* Vector 16+40: Reserved */
UNUSED(SAM_IRQ_RESERVED_41) /* Vector 16+41: Reserved */
UNUSED(SAM_IRQ_RESERVED_42) /* Vector 16+42: Reserved */
UNUSED(SAM_IRQ_RESERVED_43) /* Vector 16+43: Reserved */
VECTOR(sam_emac, SAM_IRQ_EMAC) /* Vector 16+44: EMAC */
VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+45: UART1 */
UNUSED(SAM_IRQ_RESERVED_46) /* Vector 16+46: Reserved */
#endif

136
arch/arm/src/sam34/chip/sam4l_vectors.h
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@ -1,136 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam4l_vectors.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* This file is included by sam_vectors.S. It provides the macro VECTOR that
* supplies ach SAM3U vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/sam/sam4l_irq.h.
* sam_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 80 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 80
#else
VECTOR(sam_hflashc, SAM_IRQ_HFLASHC) /* Vector 16+0: Flash Controller */
VECTOR(sam_pdca0, SAM_IRQ_PDCA0) /* Vector 16+1: Peripheral DMA Controller 0 */
VECTOR(sam_pdca1, SAM_IRQ_PDCA1) /* Vector 16+2: Peripheral DMA Controller 1 */
VECTOR(sam_pdca2, SAM_IRQ_PDCA2) /* Vector 16+3: Peripheral DMA Controller 2 */
VECTOR(sam_pdca3, SAM_IRQ_PDCA3) /* Vector 16+4: Peripheral DMA Controller 3 */
VECTOR(sam_pdca4, SAM_IRQ_PDCA4) /* Vector 16+5: Peripheral DMA Controller 4 */
VECTOR(sam_pdca5, SAM_IRQ_PDCA5) /* Vector 16+6: Peripheral DMA Controller 5 */
VECTOR(sam_pdca6, SAM_IRQ_PDCA6) /* Vector 16+7: Peripheral DMA Controller 6 */
VECTOR(sam_pdca7, SAM_IRQ_PDCA7) /* Vector 16+8: Peripheral DMA Controller 7 */
VECTOR(sam_pdca8, SAM_IRQ_PDCA8) /* Vector 16+9: Peripheral DMA Controller 8 */
VECTOR(sam_pdca9, SAM_IRQ_PDCA9) /* Vector 16+10: Peripheral DMA Controller 9 */
VECTOR(sam_pdca10, SAM_IRQ_PDCA10) /* Vector 16+11: Peripheral DMA Controller 10 */
VECTOR(sam_pdca11, SAM_IRQ_PDCA11) /* Vector 16+12: Peripheral DMA Controller 11 */
VECTOR(sam_pdca12, SAM_IRQ_PDCA12) /* Vector 16+13: Peripheral DMA Controller 12 */
VECTOR(sam_pdca13, SAM_IRQ_PDCA13) /* Vector 16+14: Peripheral DMA Controller 13 */
VECTOR(sam_pdca14, SAM_IRQ_PDCA14) /* Vector 16+15: Peripheral DMA Controller 14 */
VECTOR(sam_pdca15, SAM_IRQ_PDCA15) /* Vector 16+16: Peripheral DMA Controller 15 */
VECTOR(sam_crccu, SAM_IRQ_CRCCU) /* Vector 16+17: CRC Calculation Unit */
VECTOR(sam_usbc, SAM_IRQ_USBC) /* Vector 16+18: USB 2.0 Interface */
VECTOR(sam_pevc_tr, SAM_IRQ_PEVC_TR) /* Vector 16+19: Peripheral Event Controller TR */
VECTOR(sam_pevc_ov, SAM_IRQ_PEVC_OV) /* Vector 16+20: Peripheral Event Controller OV */
VECTOR(sam_aesa, SAM_IRQ_AESA) /* Vector 16+21: Advanced Encryption Standard */
VECTOR(sam_pm, SAM_IRQ_PM) /* Vector 16+22: Power Manager */
VECTOR(sam_scif, SAM_IRQ_SCIF) /* Vector 16+23: System Control Interface */
VECTOR(sam_freqm, SAM_IRQ_FREQM) /* Vector 16+24: Frequency Meter */
VECTOR(sam_gpio0, SAM_IRQ_GPIO0) /* Vector 16+25: General-Purpose Input/Output Controller 0 */
VECTOR(sam_gpio1, SAM_IRQ_GPIO1) /* Vector 16+26: General-Purpose Input/Output Controller 1 */
VECTOR(sam_gpio2, SAM_IRQ_GPIO2) /* Vector 16+27: General-Purpose Input/Output Controller 2 */
VECTOR(sam_gpio3, SAM_IRQ_GPIO3) /* Vector 16+28: General-Purpose Input/Output Controller 3 */
VECTOR(sam_gpio4, SAM_IRQ_GPIO4) /* Vector 16+29: General-Purpose Input/Output Controller 4 */
VECTOR(sam_gpio5, SAM_IRQ_GPIO5) /* Vector 16+30: General-Purpose Input/Output Controller 5 */
VECTOR(sam_gpio6, SAM_IRQ_GPIO6) /* Vector 16+31: General-Purpose Input/Output Controller 6 */
VECTOR(sam_gpio7, SAM_IRQ_GPIO7) /* Vector 16+32: General-Purpose Input/Output Controller 7 */
VECTOR(sam_gpio8, SAM_IRQ_GPIO8) /* Vector 16+33: General-Purpose Input/Output Controller 8 */
VECTOR(sam_gpio9, SAM_IRQ_GPIO9) /* Vector 16+34: General-Purpose Input/Output Controller 9 */
VECTOR(sam_gpio10, SAM_IRQ_GPIO10) /* Vector 16+35: General-Purpose Input/Output Controller 10 */
VECTOR(sam_gpio11, SAM_IRQ_GPIO11) /* Vector 16+36: General-Purpose Input/Output Controller 11 */
VECTOR(sam_bpm, SAM_IRQ_BPM) /* Vector 16+37: Backup Power Manager */
VECTOR(sam_bscif, SAM_IRQ_BSCIF) /* Vector 16+38: Backup System Control Interface */
VECTOR(sam_ast_alarm, SAM_IRQ_AST_ALARM) /* Vector 16+39: Asynchronous Timer ALARM */
VECTOR(sam_ast_per, SAM_IRQ_AST_PER) /* Vector 16+40: Asynchronous Timer PER */
VECTOR(sam_ast_ovf, SAM_IRQ_AST_OVF) /* Vector 16+41: Asynchronous Timer OVF */
VECTOR(sam_ast_ready, SAM_IRQ_AST_READY) /* Vector 16+42: Asynchronous Timer READY */
VECTOR(sam_ast_clkready, SAM_IRQ_AST_CLKREADY) /* Vector 16+43: Asynchronous Timer CLKREADY */
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+44: Watchdog Timer */
VECTOR(sam_eic1, SAM_IRQ_EIC1) /* Vector 16+45: External Interrupt Controller 1 */
VECTOR(sam_eic2, SAM_IRQ_EIC2) /* Vector 16+46: External Interrupt Controller 2 */
VECTOR(sam_eic3, SAM_IRQ_EIC3) /* Vector 16+47: External Interrupt Controller 3 */
VECTOR(sam_eic4, SAM_IRQ_EIC4) /* Vector 16+48: External Interrupt Controller 4 */
VECTOR(sam_eic5, SAM_IRQ_EIC5) /* Vector 16+49: External Interrupt Controller 5 */
VECTOR(sam_eic6, SAM_IRQ_EIC6) /* Vector 16+50: External Interrupt Controller 6 */
VECTOR(sam_eic7, SAM_IRQ_EIC7) /* Vector 16+51: External Interrupt Controller 7 */
VECTOR(sam_eic8, SAM_IRQ_EIC8) /* Vector 16+52: External Interrupt Controller 8 */
VECTOR(sam_iisc, SAM_IRQ_IISC) /* Vector 16+53: Inter-IC Sound (I2S) Controller */
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+54: Serial Peripheral Interface */
VECTOR(sam_tc00, SAM_IRQ_TC00) /* Vector 16+55: Timer/Counter 0 */
VECTOR(sam_tc01, SAM_IRQ_TC01) /* Vector 16+56: Timer/Counter 1 */
VECTOR(sam_tc02, SAM_IRQ_TC02) /* Vector 16+57: Timer/Counter 2 */
VECTOR(sam_tc10, SAM_IRQ_TC10) /* Vector 16+58: Timer/Counter 10 */
VECTOR(sam_tc11, SAM_IRQ_TC11) /* Vector 16+59: Timer/Counter 11 */
VECTOR(sam_tc12, SAM_IRQ_TC12) /* Vector 16+60: Timer/Counter 12 */
VECTOR(sam_twim0, SAM_IRQ_TWIM0) /* Vector 16+61: Two-wire Master Interface TWIM0 */
VECTOR(sam_twis0, SAM_IRQ_TWIS0) /* Vector 16+62: Two-wire Slave Interface TWIS0 */
VECTOR(sam_twim1, SAM_IRQ_TWIM1) /* Vector 16+63: Two-wire Master Interface TWIM1 */
VECTOR(sam_twis1, SAM_IRQ_TWIS1) /* Vector 16+64: Two-wire Slave Interface TWIS1 */
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+65: USART0 */
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+66: USART1 */
VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+67: USART2 */
VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+68: USART3 */
VECTOR(sam_adcife, SAM_IRQ_ADCIFE) /* Vector 16+69: ADC controller interface */
VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+70: DAC Controller */
VECTOR(sam_acifc, SAM_IRQ_ACIFC) /* Vector 16+71: Analog Comparator Interface */
VECTOR(sam_abdacb, SAM_IRQ_ABDACB) /* Vector 16+72: Audio Bitstream DAC */
VECTOR(sam_trng, SAM_IRQ_TRNG) /* Vector 16+73: True Random Number Generator */
VECTOR(sam_parc, SAM_IRQ_PARC) /* Vector 16+74: Parallel Capture */
VECTOR(sam_catb, SAM_IRQ_CATB) /* Vector 16+75: Capacitive Touch Module B */
VECTOR(sam_twim2, SAM_IRQ_TWIM2) /* Vector 16+77: Two-wire Master Interface */
VECTOR(sam_twim3, SAM_IRQ_TWIM3) /* Vector 16+78: Two-wire Master Interface */
VECTOR(sam_lcdca, SAM_IRQ_LCDCA) /* Vector 16+79: LCD Controller A */
#endif

92
arch/arm/src/sam34/chip/sam4s_vectors.h
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@ -1,92 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam4s_vectors.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* This file is included by sam_vectors.S. It provides the macro VECTOR that
* supplies ach SAM4S vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h.
* sam_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 35 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 35
#else
VECTOR(sam_supc, SAM_IRQ_SUPC) /* Vector 16+0: Supply Controller */
VECTOR(sam_rstc, SAM_IRQ_RSTC) /* Vector 16+1: Reset Controller */
VECTOR(sam_rtc, SAM_IRQ_RTC) /* Vector 16+2: Real Time Clock */
VECTOR(sam_rtt, SAM_IRQ_RTT) /* Vector 16+3: Real Time Timer */
VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+4: Watchdog Timer */
VECTOR(sam_pmc, SAM_IRQ_PMC) /* Vector 16+5: Power Management Controller */
VECTOR(sam_eefc0, SAM_IRQ_EEFC0) /* Vector 16+6: Enhanced Embedded Flash Controller 0 */
VECTOR(sam_eefc1, SAM_IRQ_EEFC1) /* Vector 16+7: Enhanced Embedded Flash Controller 1 */
VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */
VECTOR(sam_uart1, SAM_IRQ_UART1) /* Vector 16+9: Universal Asynchronous Receiver Transmitter 1 */
VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+10: Static Memory Controller */
VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */
VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */
VECTOR(sam_pioc, SAM_IRQ_PIOC) /* Vector 16+13: Parallel I/O Controller C */
VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+14: USART 0 */
VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+15: USART 1 */
UNUSED(SAM_IRQ_RESERVED_16) /* Vector 16+16: Reserved */
UNUSED(SAM_IRQ_RESERVED_17) /* Vector 16+17: Reserved */
VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+18: High Speed Multimedia Card Interface */
VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */
VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */
VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+21: Serial Peripheral Interface */
VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+22: Synchronous Serial Controller */
VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */
VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */
VECTOR(sam_tc2, SAM_IRQ_TC2) /* Vector 16+25: Timer Counter 2 */
VECTOR(sam_tc3, SAM_IRQ_TC3) /* Vector 16+26: Timer Counter 3 */
VECTOR(sam_tc4, SAM_IRQ_TC4) /* Vector 16+27: Timer Counter 4 */
VECTOR(sam_tc5, SAM_IRQ_TC5) /* Vector 16+28: Timer Counter 5 */
VECTOR(sam_adc, SAM_IRQ_ADC) /* Vector 16+29: Analog To Digital Converter */
VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+30: Digital To Analog Converter */
VECTOR(sam_pwm, SAM_IRQ_PWM) /* Vector 16+31: Pulse Width Modulation */
VECTOR(sam_crccu, SAM_IRQ_CRCCU) /* Vector 16+32: CRC Calculation Unit */
VECTOR(sam_acc, SAM_IRQ_ACC) /* Vector 16+33: Analog Comparator */
VECTOR(sam_udp, SAM_IRQ_UDP) /* Vector 16+34: USB Device Port */
#endif

34
arch/arm/src/sam34/sam_start.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/sam34/sam_start.c
*
* Copyright (C) 2009-2010, 2012-2013, 2015, 2017 Gregory Nutt. All
* Copyright (C) 2009-2010, 2012-2013, 2015, 2017-2018 Gregory Nutt. All
* rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
@ -60,6 +60,36 @@
#include "sam_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EBI requires 64 bit stack alignment.
*/
#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE)
#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
@ -120,7 +150,7 @@ void __start(void) __attribute__ ((no_instrument_function));
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU)
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void sam_fpuconfig(void)
{

18
arch/arm/src/sam34/sam_start.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/sam34/sam_start.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -42,6 +42,22 @@
#include <nuttx/config.h>
/************************************************************************************
* Public Data
************************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
extern const uintptr_t g_idle_topstack;
/************************************************************************************
* Public Function Prototypes
************************************************************************************/

511
arch/arm/src/sam34/sam_vectors.S
View File

@ -1,511 +0,0 @@
/************************************************************************************************
* arch/arm/src/sam34/sam_vectors.S
*
* Copyright (C) 2009-2010, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************/
/************************************************************************************************
* Included Files
************************************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#include "exc_return.h"
/************************************************************************************************
* Pre-processor Definitions
************************************************************************************************/
/* Configuration ********************************************************************************/
#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
/* In kernel mode without an interrupt stack, this interrupt handler will set the MSP to the
* stack pointer of the interrupted thread. If the interrupted thread was a privileged
* thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the
* value of the MSP will be invalid when the interrupt handler returns because it will be a
* pointer to an old position in the unprivileged stack. Then when the high priority
* interrupt occurs and uses this stale MSP, there will most likely be a system failure.
*
* If the interrupt stack is selected, on the other hand, then the interrupt handler will
* always set the MSP to the interrupt stack. So when the high priority interrupt occurs,
* it will either use the MSP of the last privileged thread to run or, in the case of the
* nested interrupt, the interrupt stack if no privileged task has run.
*/
# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
# error Interrupt stack must be used with high priority interrupts in kernel mode
# endif
/* Use the BASEPRI to control interrupts is required if nested, high
* priority interrupts are supported.
*/
# ifndef CONFIG_ARMV7M_USEBASEPRI
# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
# endif
#endif
/* Memory Map ***********************************************************************************/
/*
* 0x0800:0000 - Beginning of FLASH. Address of vectors. Mapped to address 0x0000:0000 at boot
* time.
* 0x0803:ffff - End of flash
* 0x2000:0000 - Start of SRAM and start of .data (_sdata)
* - End of .data (_edata) and start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap. NOTE
* that the ARM uses a decrement before store stack so that the correct initial
* value is the end of the stack + 4;
* 0x2000:bfff - End of SRAM and end of heap
*/
#define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
#define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE)
/************************************************************************************************
* Public Symbols
************************************************************************************************/
.syntax unified
.thumb
.file "sam_vectors.S"
/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.S) */
#ifndef CONFIG_ARMV7M_CMNVECTOR
.globl __start
/************************************************************************************************
* Macros
************************************************************************************************/
/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
* registers on the stack, then branches to an instantantiation of the following
* macro. This macro simply loads the IRQ number into R0, then jumps to the common
* IRQ handling logic.
*/
.macro HANDLER, label, irqno
.thumb_func
\label:
mov r0, #\irqno
b exception_common
.endm
/************************************************************************************************
* Vectors
************************************************************************************************/
.section .vectors, "ax"
.code 16
.align 2
.globl _vectors
.type _vectors, function
_vectors:
/* Processor Exceptions */
.word IDLE_STACK /* Vector 0: Reset stack pointer */
.word __start /* Vector 1: Reset vector */
.word sam_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */
.word sam_hardfault /* Vector 3: Hard fault */
.word sam_mpu /* Vector 4: Memory management (MPU) */
.word sam_busfault /* Vector 5: Bus fault */
.word sam_usagefault /* Vector 6: Usage fault */
.word sam_reserved /* Vector 7: Reserved */
.word sam_reserved /* Vector 8: Reserved */
.word sam_reserved /* Vector 9: Reserved */
.word sam_reserved /* Vector 10: Reserved */
.word sam_svcall /* Vector 11: SVC call */
.word sam_dbgmonitor /* Vector 12: Debug monitor */
.word sam_reserved /* Vector 13: Reserved */
.word sam_pendsv /* Vector 14: Pendable system service request */
.word sam_systick /* Vector 15: System tick */
/* External Interrupts */
#undef VECTOR
#define VECTOR(l,i) .word l
#undef UNUSED
#define UNUSED(i) .word sam_reserved
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# include "chip/sam3u_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# include "chip/sam3x_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
# include "chip/sam4cm_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
# include "chip/sam4e_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "chip/sam4l_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# include "chip/sam4s_vectors.h"
#else
# error Unrecognized SAM architecture
#endif
.size _vectors, .-_vectors
/************************************************************************************************
* .text
************************************************************************************************/
.text
.type handlers, function
.thumb_func
handlers:
HANDLER sam_reserved, SAM_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER sam_nmi, SAM_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER sam_hardfault, SAM_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER sam_mpu, SAM_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER sam_busfault, SAM_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER sam_usagefault, SAM_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER sam_svcall, SAM_IRQ_SVCALL /* Vector 11: SVC call */
HANDLER sam_dbgmonitor, SAM_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
HANDLER sam_pendsv, SAM_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER sam_systick, SAM_IRQ_SYSTICK /* Vector 15: System tick */
#undef VECTOR
#define VECTOR(l,i) HANDLER l, i
#undef UNUSED
#define UNUSED(i)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# include "chip/sam3u_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# include "chip/sam3x_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4CM)
# include "chip/sam4cm_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
# include "chip/sam4e_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "chip/sam4l_vectors.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# include "chip/sam4s_vectors.h"
#else
# error Unrecognized SAM architecture
#endif
/* Common IRQ handling logic. On entry here, the return stack is on either
* the PSP or the MSP and looks like the following:
*
* REG_XPSR
* REG_R15
* REG_R14
* REG_R12
* REG_R3
* REG_R2
* REG_R1
* MSP->REG_R0
*
* And
* R0 contains the IRQ number
* R14 Contains the EXC_RETURN value
* We are in handler mode and the current SP is the MSP
*/
.globl exception_common
.type exception_common, function
exception_common:
/* Complete the context save */
#ifdef CONFIG_BUILD_PROTECTED
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
* (handler mode) if the stack is on the MSP. It can only be on the PSP if
* EXC_RETURN is 0xfffffffd (unprivileged thread)
*/
tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
beq 1f /* Branch if context already on the MSP */
mrs r1, psp /* R1=The process stack pointer (PSP) */
mov sp, r1 /* Set the MSP to the PSP */
1:
#endif
/* r1 holds the value of the stack pointer AFTER the exception handling logic
* pushed the various registers onto the stack. Get r2 = the value of the
* stack pointer BEFORE the interrupt modified it.
*/
mov r2, sp /* R2=Copy of the main/process stack pointer */
add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */
#ifdef CONFIG_ARMV7M_USEBASEPRI
mrs r3, basepri /* R3=Current BASEPRI setting */
#else
mrs r3, primask /* R3=Current PRIMASK setting */
#endif
#ifdef CONFIG_ARCH_FPU
/* Skip over the block of memory reserved for floating pointer register save.
* Lazy FPU register saving is used. FPU registers will be saved in this
* block only if a context switch occurs (this means, of course, that the FPU
* cannot be used in interrupt processing).
*/
sub sp, #(4*SW_FPU_REGS)
#endif
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/
#ifdef CONFIG_BUILD_PROTECTED
stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP value */
#else
stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */
#endif
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
/* Disable interrupts, select the stack to use for interrupt handling
* and call up_doirq to handle the interrupt
*/
cpsid i /* Disable further interrupts */
#else
/* Set the BASEPRI register so that further normal interrupts will be
* masked. Nested, high priority may still occur, however.
*/
mov r2, #NVIC_SYSH_DISABLE_PRIORITY
msr basepri, r2 /* Set the BASEPRI */
#endif
/* There are two arguments to up_doirq:
*
* R0 = The IRQ number
* R1 = The top of the stack points to the saved state
*/
mov r1, sp
/* Also save the top of the stack in a preserved register */
mov r4, sp
#if CONFIG_ARCH_INTERRUPTSTACK > 7
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
* a special special interrupt stack pointer. The way that this is done
* here prohibits nested interrupts without some additional logic!
*/
ldr sp, =g_intstackbase
#else
/* Otherwise, we will re-use the interrupted thread's stack. That may
* mean using either MSP or PSP stack for interrupt level processing (in
* kernel mode).
*/
bic r2, r4, #7 /* Get the stack pointer with 8-byte alignment */
mov sp, r2 /* Instantiate the aligned stack */
#endif
bl up_doirq /* R0=IRQ, R1=register save (msp) */
mov r1, r4 /* Recover R1=main stack pointer */
/* On return from up_doirq, R0 will hold a pointer to register context
* array to use for the interrupt return. If that return value is the same
* as current stack pointer, then things are relatively easy.
*/
cmp r0, r1 /* Context switch? */
beq 2f /* Branch if no context switch */
/* We are returning with a pending context switch.
*
* If the FPU is enabled, then we will need to restore FPU registers.
* This is not done in normal interrupt save/restore because the cost
* is prohibitive. This is only done when switching contexts. A
* consequence of this is that floating point operations may not be
* performed in interrupt handling logic.
*
* Here:
* r0 = Address of the register save area
*
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
#ifdef CONFIG_ARCH_FPU
bl up_restorefpu /* Restore the FPU registers */
#endif
/* We are returning with a pending context switch. This case is different
* because in this case, the register save structure does not lie in the
* stack but, rather, within a TCB structure. We'll have to copy some
* values to the stack.
*/
add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
#ifdef CONFIG_BUILD_PROTECTED
ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
#else
ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
#endif
b 3f /* Re-join common logic */
/* We are returning with no context switch. We simply need to "unwind"
* the same stack frame that we created
*
* Here:
* r1 = Address of the return stack (same as r0)
*/
2:
#ifdef CONFIG_BUILD_PROTECTED
ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
#else
ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */
#endif
#ifdef CONFIG_ARCH_FPU
/* Skip over the block of memory reserved for floating pointer register
* save. Then R1 is the address of the HW save area
*/
add r1, #(4*SW_FPU_REGS)
#endif
/* Set up to return from the exception
*
* Here:
* r1 = Address on the target thread's stack position at the start of
* the registers saved by hardware
* r3 = primask or basepri
* r4-r11 = restored register values
*/
3:
#ifdef CONFIG_BUILD_PROTECTED
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
* (handler mode) if the stack is on the MSP. It can only be on the PSP if
* EXC_RETURN is 0xfffffffd (unprivileged thread)
*/
mrs r2, control /* R2=Contents of the control register */
tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
beq 4f /* Branch if privileged */
orr r2, r2, #1 /* Unprivileged mode */
msr psp, r1 /* R1=The process stack pointer */
b 5f
4:
bic r2, r2, #1 /* Privileged mode */
msr msp, r1 /* R1=The main stack pointer */
5:
msr control, r2 /* Save the updated control register */
#else
msr msp, r1 /* Recover the return MSP value */
/* Preload r14 with the special return value first (so that the return
* actually occurs with interrupts still disabled).
*/
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
#endif
/* Restore the interrupt state */
#ifdef CONFIG_ARMV7M_USEBASEPRI
msr basepri, r3 /* Restore interrupts priority masking */
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
cpsie i /* Re-enable interrupts */
#endif
#else
msr primask, r3 /* Restore interrupts */
#endif
/* Always return with R14 containing the special value that will: (1)
* return to thread mode, and (2) continue to use the MSP
*/
bx r14 /* And return */
.size handlers, .-handlers
/************************************************************************************************
* Name: g_intstackalloc/g_intstackbase
*
* Description:
* Shouldn't happen
*
************************************************************************************************/
#if CONFIG_ARCH_INTERRUPTSTACK > 7
.bss
.global g_intstackalloc
.global g_intstackbase
.align 8
g_intstackalloc:
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
#endif /* CONFIG_ARMV7M_CMNVECTOR */
/************************************************************************************************
* .rodata
************************************************************************************************/
.section .rodata, "a"
/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
* of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
* and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that
* the system boots on and, eventually, becomes the idle, do nothing task that runs
* only when there is nothing else to run. The heap continues from there until the
* end of memory. See g_idle_topstack below.
*/
.globl g_idle_topstack
.type g_idle_topstack, object
g_idle_topstack:
.word HEAP_BASE
.size g_idle_topstack, .-g_idle_topstack
.end

6
configs/arduino-due/nsh/defconfig
View File

@ -1,18 +1,18 @@
# CONFIG_ARCH_RAMFUNCS is not set
CONFIG_ARCH_BOARD_ARDUINO_DUE=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="arduino-due"
CONFIG_ARCH_BOARD_ARDUINO_DUE=y
CONFIG_ARCH_CHIP_ATSAM3X8E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3X=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=6965
CONFIG_BUILTIN=y
CONFIG_CXX_NEWLONG=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y

1
configs/arduino-due/scripts/arduino-due.ld
View File

@ -46,6 +46,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

7
configs/flipnclick-sam3x/nsh/defconfig
View File

@ -1,16 +1,16 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_SAM34_UART0 is not set
CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="flipnclick-sam3x"
CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y
CONFIG_ARCH_CHIP_ATSAM3X8E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3X=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=6965
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
@ -38,7 +38,6 @@ CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=28
CONFIG_START_MONTH=6
CONFIG_START_YEAR=2013
CONFIG_TASK_NAME_SIZE=31
CONFIG_USART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0

14
configs/flipnclick-sam3x/nxlines/defconfig
View File

@ -1,30 +1,30 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_NX_DISABLE_1BPP is not set
# CONFIG_SAM34_UART0 is not set
CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="flipnclick-sam3x"
CONFIG_ARCH_BOARD_FLIPNCLICK_SAM3X=y
CONFIG_ARCH_CHIP_ATSAM3X8E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3X=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_BOARD_LOOPSPERMSEC=6965
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NXLINES=y
CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4
CONFIG_EXAMPLES_NXLINES_BPP=1
CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4
CONFIG_EXAMPLES_NXLINES=y
CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBB=y
CONFIG_FLIPNCLICK_SAM3X_SSD1306=y
CONFIG_FLIPNCLICK_SAM3X_SSD1306_MBB=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_HOST_WINDOWS=y
CONFIG_LCD=y
CONFIG_LCD_HILETGO=y
CONFIG_LCD_MAXCONTRAST=255
CONFIG_LCD=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=3
@ -36,10 +36,10 @@ CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_IFUPDOWN=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_NX_BLOCKING=y
CONFIG_NX=y
CONFIG_NXFONT_TOM_THUMB_4X6=y
CONFIG_NXTK_BORDERWIDTH=2
CONFIG_NX_BLOCKING=y
CONFIG_PREALLOC_MQ_MSGS=8
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4

1
configs/flipnclick-sam3x/scripts/flash.ld
View File

@ -46,6 +46,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

10
configs/sam3u-ek/knsh/defconfig
View File

@ -1,19 +1,18 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_MMCSD_HAVE_CARDDETECT is not set
# CONFIG_MMCSD_MMCSUPPORT is not set
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam3u-ek"
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM3U4E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3U=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARM_MPU=y
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARM_MPU=y
CONFIG_BOARD_LOOPSPERMSEC=8720
CONFIG_BUILD_PROTECTED=y
CONFIG_DISABLE_POLL=y
@ -21,13 +20,12 @@ CONFIG_EXAMPLES_NSH=y
CONFIG_FS_FAT=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2
CONFIG_MMCSD=y
CONFIG_MM_REGIONS=2
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_DISABLE_DD=y
CONFIG_NSH_DISABLE_LOSETUP=y
CONFIG_NSH_DISABLE_MKFATFS=y
CONFIG_NSH_DISABLE_MKRD=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64

5
configs/sam3u-ek/nsh/defconfig
View File

@ -1,15 +1,14 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam3u-ek"
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM3U4E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3U=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=8720

14
configs/sam3u-ek/nx/defconfig
View File

@ -1,17 +1,17 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NX_PACKEDMSFIRST is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam3u-ek"
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM3U4E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3U=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARMV7M_USEBASEPRI=y
@ -20,28 +20,28 @@ CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_MOUNTPOINT=y
CONFIG_DISABLE_POLL=y
CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_EXAMPLES_NX=y
CONFIG_EXAMPLES_NX_BGCOLOR=0x7b5d
CONFIG_EXAMPLES_NX_BPP=16
CONFIG_EXAMPLES_NX_COLOR1=0xe73f
CONFIG_EXAMPLES_NX_COLOR2=0xdefb
CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000
CONFIG_EXAMPLES_NX_TBCOLOR=0xad55
CONFIG_EXAMPLES_NX=y
CONFIG_LCD=y
CONFIG_LCD_MAXCONTRAST=1
CONFIG_LCD_MAXPOWER=31
CONFIG_LCD_PORTRAIT=y
CONFIG_LCD=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2
CONFIG_MQ_MAXMSGSIZE=64
CONFIG_NFILE_DESCRIPTORS=12
CONFIG_NFILE_STREAMS=12
CONFIG_NX=y
CONFIG_NXFONT_SANS23X27=y
CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_XYINPUT_MOUSE=y
CONFIG_NX=y
CONFIG_NXFONT_SANS23X27=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4

31
configs/sam3u-ek/nxwm/defconfig
View File

@ -2,20 +2,20 @@
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NX_DISABLE_16BPP is not set
CONFIG_ADS7843E_SPIDEV=2
CONFIG_ADS7843E_SWAPXY=y
CONFIG_ADS7843E_THRESHX=51
CONFIG_ADS7843E_THRESHY=39
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam3u-ek"
CONFIG_ARCH_BOARD_SAM3UEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM3U4E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM3U=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=8720
@ -23,12 +23,11 @@ CONFIG_CXX_NEWLONG=y
CONFIG_DISABLE_POLL=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_INPUT_ADS7843E=y
CONFIG_INPUT=y
CONFIG_INPUT_ADS7843E=y
CONFIG_LCD=y
CONFIG_LCD_MAXCONTRAST=1
CONFIG_LCD_MAXPOWER=31
CONFIG_LCD=y
CONFIG_LIB_BOARDCTL=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2
@ -40,29 +39,26 @@ CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LIBRARY=y
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_WRITEONLY=y
CONFIG_NX_XYINPUT_TOUCHSCREEN=y
CONFIG_NX=y
CONFIG_NXFONT_SANS22X29B=y
CONFIG_NXFONT_SANS23X27=y
CONFIG_NXTERM=y
CONFIG_NXTERM_CACHESIZE=32
CONFIG_NXTERM_CURSORCHAR=95
CONFIG_NXTERM_MXCHARS=325
CONFIG_NXTERM_NXKBDIN=y
CONFIG_NXTERM=y
CONFIG_NXWIDGETS=y
CONFIG_NXWIDGETS_BPP=16
CONFIG_NXWIDGETS_LISTENERSTACK=1596
CONFIG_NXWIDGETS_SIZEOFCHAR=1
CONFIG_NXWIDGETS=y
CONFIG_NXWM=y
CONFIG_NXWM_BACKGROUND_IMAGE=""
CONFIG_NXWM_CALIBRATION_LISTENERSTACK=1024
CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y
CONFIG_NXWM_HEXCALCULATOR_FONTID=5
CONFIG_NXWM_KEYBOARD=y
CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100
CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024
CONFIG_NXWM_KEYBOARD=y
CONFIG_NXWM_NXTERM_STACKSIZE=1596
CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596
CONFIG_NXWM_TASKBAR_HSPACING=4
@ -71,7 +67,10 @@ CONFIG_NXWM_TASKBAR_VSPACING=4
CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100
CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596
CONFIG_NXWM_UNITTEST=y
CONFIG_NXWM=y
CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_WRITEONLY=y
CONFIG_NX_XYINPUT_TOUCHSCREEN=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4
CONFIG_PTHREAD_STACK_DEFAULT=1024
@ -79,8 +78,8 @@ CONFIG_RAM_SIZE=32768
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SAM34_GPIO_IRQ=y
CONFIG_SAM34_GPIOA_IRQ=y
CONFIG_SAM34_GPIO_IRQ=y
CONFIG_SAM34_SPI0=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPRIORITY=192
@ -92,6 +91,6 @@ CONFIG_START_MONTH=6
CONFIG_START_YEAR=2013
CONFIG_TASK_NAME_SIZE=0
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nxwm_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_USER_ENTRYPOINT="nxwm_main"
CONFIG_WDOG_INTRESERVE=0

1
configs/sam3u-ek/scripts/kernel-space.ld
View File

@ -38,6 +38,7 @@
*/
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

1
configs/sam3u-ek/scripts/ld.script
View File

@ -49,6 +49,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

1
configs/sam4cmp-db/scripts/sam4cmp-db.ld
View File

@ -44,6 +44,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

37
configs/sam4e-ek/nsh/defconfig
View File

@ -1,16 +1,15 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_SAM4EEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam4e-ek"
CONFIG_ARCH_BOARD_SAM4EEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM4E16E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM4E=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
CONFIG_BOARD_LOOPSPERMSEC=11990
CONFIG_BUILTIN=y
@ -23,26 +22,26 @@ CONFIG_IOB_NBUFFERS=24
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2
CONFIG_MTD_AT25=y
CONFIG_MTD=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMP=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NET_UDP=y
CONFIG_MTD_AT25=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y
@ -59,16 +58,16 @@ CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SAM34_CMCC=y
CONFIG_SAM34_DMAC0=y
CONFIG_SAM34_EMAC=y
CONFIG_SAM34_EMAC_PHYSR=30
CONFIG_SAM34_EMAC_PHYSR_100FD=0x6
CONFIG_SAM34_EMAC_PHYSR_100HD=0x2
CONFIG_SAM34_EMAC_PHYSR_10FD=0x5
CONFIG_SAM34_EMAC_PHYSR_10HD=0x1
CONFIG_SAM34_EMAC_PHYSR_ALTCONFIG=y
CONFIG_SAM34_EMAC_PHYSR_ALTMODE=0x7
CONFIG_SAM34_EMAC_PHYSR=30
CONFIG_SAM34_EMAC=y
CONFIG_SAM34_SPI_DMA=y
CONFIG_SAM34_SPI0=y
CONFIG_SAM34_SPI_DMA=y
CONFIG_SAM34_USART1=y
CONFIG_SAM4EEK_120MHZ=y
CONFIG_SAM4EEK_AT25_BLOCKMOUNT=y

61
configs/sam4e-ek/nxwm/defconfig
View File

@ -2,20 +2,20 @@
# CONFIG_DISABLE_OS_API is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_NX_DISABLE_16BPP is not set
# CONFIG_NXFONTS_DISABLE_16BPP is not set
# CONFIG_NX_DISABLE_16BPP is not set
CONFIG_ADS7843E_SWAPXY=y
CONFIG_ADS7843E_THRESHX=51
CONFIG_ADS7843E_THRESHY=39
CONFIG_ARCH_BOARD_SAM4EEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam4e-ek"
CONFIG_ARCH_BOARD_SAM4EEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM4E16E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM4E=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
CONFIG_BOARD_LOOPSPERMSEC=11990
CONFIG_BUILTIN=y
@ -25,38 +25,37 @@ CONFIG_FAT_LFN=y
CONFIG_FS_FAT=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_INPUT_ADS7843E=y
CONFIG_INPUT=y
CONFIG_INPUT_ADS7843E=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LCD=y
CONFIG_LCD_MAXCONTRAST=1
CONFIG_LCD_MAXPOWER=64
CONFIG_LCD=y
CONFIG_LIB_BOARDCTL=y
CONFIG_LIBC_FLOATINGPOINT=y
CONFIG_LIBM=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2
CONFIG_MQ_MAXMSGSIZE=64
CONFIG_MTD_AT25=y
CONFIG_MTD=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMP=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NET_UDP=y
CONFIG_MTD_AT25=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y
@ -66,22 +65,19 @@ CONFIG_NSH_LIBRARY=y
CONFIG_NSH_LINELEN=64
CONFIG_NSH_NOMAC=y
CONFIG_NSH_READLINE=y
CONFIG_NX_BGCOLOR=0x95fa
CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_XYINPUT_TOUCHSCREEN=y
CONFIG_NX=y
CONFIG_NXFONT_SANS22X29B=y
CONFIG_NXFONT_SANS23X27=y
CONFIG_NXTERM=y
CONFIG_NXTERM_CACHESIZE=32
CONFIG_NXTERM_CURSORCHAR=95
CONFIG_NXTERM_MXCHARS=396
CONFIG_NXTERM_NXKBDIN=y
CONFIG_NXTERM=y
CONFIG_NXWIDGETS=y
CONFIG_NXWIDGETS_BPP=16
CONFIG_NXWIDGETS_LISTENERSTACK=1596
CONFIG_NXWIDGETS_SIZEOFCHAR=1
CONFIG_NXWIDGETS=y
CONFIG_NXWM=y
CONFIG_NXWM_CALIBRATION_AVERAGE=y
CONFIG_NXWM_CALIBRATION_CUSTOM_FONTID=y
CONFIG_NXWM_CALIBRATION_FONTID=5
@ -90,8 +86,8 @@ CONFIG_NXWM_CALIBRATION_MESSAGES=y
CONFIG_NXWM_CALIBRATION_NSAMPLES=2
CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y
CONFIG_NXWM_HEXCALCULATOR_FONTID=5
CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024
CONFIG_NXWM_KEYBOARD=y
CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024
CONFIG_NXWM_NXTERM_STACKSIZE=1596
CONFIG_NXWM_TASKBAR_HSPACING=4
CONFIG_NXWM_TASKBAR_LEFT=y
@ -100,7 +96,10 @@ CONFIG_NXWM_TOOLBAR_CUSTOM_FONTID=y
CONFIG_NXWM_TOOLBAR_FONTID=5
CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596
CONFIG_NXWM_UNITTEST=y
CONFIG_NXWM=y
CONFIG_NX_BGCOLOR=0x95fa
CONFIG_NX_BLOCKING=y
CONFIG_NX_KBD=y
CONFIG_NX_XYINPUT_TOUCHSCREEN=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_STACK_DEFAULT=1024
CONFIG_RAM_SIZE=131072
@ -109,19 +108,19 @@ CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SAM34_CMCC=y
CONFIG_SAM34_DMAC0=y
CONFIG_SAM34_EMAC=y
CONFIG_SAM34_EMAC_PHYSR=30
CONFIG_SAM34_EMAC_PHYSR_100FD=0x6
CONFIG_SAM34_EMAC_PHYSR_100HD=0x2
CONFIG_SAM34_EMAC_PHYSR_10FD=0x5
CONFIG_SAM34_EMAC_PHYSR_10HD=0x1
CONFIG_SAM34_EMAC_PHYSR_ALTCONFIG=y
CONFIG_SAM34_EMAC_PHYSR_ALTMODE=0x7
CONFIG_SAM34_EMAC_PHYSR=30
CONFIG_SAM34_EMAC=y
CONFIG_SAM34_GPIO_IRQ=y
CONFIG_SAM34_GPIOA_IRQ=y
CONFIG_SAM34_GPIO_IRQ=y
CONFIG_SAM34_SMC=y
CONFIG_SAM34_SPI_DMA=y
CONFIG_SAM34_SPI0=y
CONFIG_SAM34_SPI_DMA=y
CONFIG_SAM34_USART1=y
CONFIG_SAM4EEK_120MHZ=y
CONFIG_SAM4EEK_AT25_BLOCKMOUNT=y
@ -138,5 +137,5 @@ CONFIG_START_YEAR=2014
CONFIG_SYSTEM_PING=y
CONFIG_TASK_NAME_SIZE=0
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nxwm_main"
CONFIG_USERMAIN_STACKSIZE=1024
CONFIG_USER_ENTRYPOINT="nxwm_main"

1
configs/sam4e-ek/scripts/flash.ld
View File

@ -47,6 +47,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

37
configs/sam4e-ek/usbnsh/defconfig
View File

@ -1,27 +1,26 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_DEV_CONSOLE is not set
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_SAM4EEK=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam4e-ek"
CONFIG_ARCH_BOARD_SAM4EEK=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM4E16E=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM4E=y
CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=11990
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_LOOPSPERMSEC=11990
CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_CONSOLE=y
CONFIG_CDCACM_EPBULKIN=3
CONFIG_CDCACM_EPBULKOUT=2
CONFIG_CDCACM_RXBUFSIZE=256
CONFIG_CDCACM_TXBUFSIZE=256
CONFIG_CDCACM=y
CONFIG_ETH0_PHY_KSZ8051=y
CONFIG_EXAMPLES_NSH=y
CONFIG_FAT_LCNAMES=y
@ -31,24 +30,24 @@ CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MM_REGIONS=2
CONFIG_MTD_AT25=y
CONFIG_MTD=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMP=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NET_UDP=y
CONFIG_MTD_AT25=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDB_DNSSERVER_NOADDR=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=16
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_CONNS=16
CONFIG_NET_UDP=y
CONFIG_NET_UDP_CHECKSUMS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y
@ -65,16 +64,16 @@ CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SAM34_CMCC=y
CONFIG_SAM34_DMAC0=y
CONFIG_SAM34_EMAC=y
CONFIG_SAM34_EMAC_PHYSR=30
CONFIG_SAM34_EMAC_PHYSR_100FD=0x6
CONFIG_SAM34_EMAC_PHYSR_100HD=0x2
CONFIG_SAM34_EMAC_PHYSR_10FD=0x5
CONFIG_SAM34_EMAC_PHYSR_10HD=0x1
CONFIG_SAM34_EMAC_PHYSR_ALTCONFIG=y
CONFIG_SAM34_EMAC_PHYSR_ALTMODE=0x7
CONFIG_SAM34_EMAC_PHYSR=30
CONFIG_SAM34_EMAC=y
CONFIG_SAM34_SPI_DMA=y
CONFIG_SAM34_SPI0=y
CONFIG_SAM34_SPI_DMA=y
CONFIG_SAM34_UDP=y
CONFIG_SAM34_USART1=y
CONFIG_SAM4EEK_120MHZ=y

9
configs/sam4l-xplained/nsh/defconfig
View File

@ -1,14 +1,13 @@
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
CONFIG_ARCH_BOARD_SAM4L_XPLAINED=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam4l-xplained"
CONFIG_ARCH_BOARD_SAM4L_XPLAINED=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM4LC4C=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM4L=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=3410
@ -16,8 +15,8 @@ CONFIG_BUILTIN=y
CONFIG_CXX_NEWLONG=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_MAX_TASKS=16
@ -46,6 +45,6 @@ CONFIG_START_YEAR=2013
CONFIG_TASK_NAME_SIZE=0
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
CONFIG_USART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=1536
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WDOG_INTRESERVE=0

1
configs/sam4l-xplained/scripts/sam4l-xplained.ld
View File

@ -44,6 +44,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

26
configs/sam4s-xplained-pro/nsh/defconfig
View File

@ -1,36 +1,36 @@
# CONFIG_ARCH_RAMFUNCS is not set
# CONFIG_EXAMPLES_SERIALRX_BUFFERED is not set
CONFIG_ARCH_BOARD_SAM4S_XPLAINED_PRO=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam4s-xplained-pro"
CONFIG_ARCH_BOARD_SAM4S_XPLAINED_PRO=y
CONFIG_ARCH_CHIP_ATSAM4SD32C=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM4S=y
CONFIG_ARCH_INTERRUPTSTACK=1024
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARM_MPU=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_ARM_MPU=y
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BOARD_INITIALIZE=y
CONFIG_BOARD_LOOPSPERMSEC=9186
CONFIG_BOARDCTL_USBDEVCTRL=y
CONFIG_BUILTIN=y
CONFIG_CDCACM=y
CONFIG_CDCACM_BULKIN_REQLEN=250
CONFIG_CDCACM_RXBUFSIZE=1024
CONFIG_CDCACM_TXBUFSIZE=1024
CONFIG_CDCACM=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEV_ZERO=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_CPUHOG=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_SERIALBLASTER=y
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_EXAMPLES_SERIALRX_BUFSIZE=4096
CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y
CONFIG_EXAMPLES_SERIALRX=y
CONFIG_FS_FAT=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
@ -38,15 +38,13 @@ CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_INTELHEX_BINARY=y
CONFIG_JULIAN_TIME=y
CONFIG_LIBC_STRERROR_SHORT=y
CONFIG_LIBC_STRERROR=y
CONFIG_LIBC_STRERROR_SHORT=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_MMCSD_SDIO=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_DISABLE_ADDROUTE=y
CONFIG_NSH_DISABLE_DELROUTE=y
CONFIG_NSH_DISABLE_IFCONFIG=y
CONFIG_NSH_DISABLE_LOSETUP=y
CONFIG_NSH_FILEIOSIZE=2048
@ -61,14 +59,14 @@ CONFIG_RAM_SIZE=163840
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=50
CONFIG_RTC=y
CONFIG_RTC_ALARM=y
CONFIG_RTC_FREQUENCY=32768
CONFIG_RTC_HIRES=y
CONFIG_RTC=y
CONFIG_SAM34_EXTNAND=y
CONFIG_SAM34_EXTNANDSIZE=268435456
CONFIG_SAM34_GPIO_IRQ=y
CONFIG_SAM34_GPIOC_IRQ=y
CONFIG_SAM34_GPIO_IRQ=y
CONFIG_SAM34_HSMCI=y
CONFIG_SAM34_PDCA=y
CONFIG_SAM34_RTC=y
@ -80,9 +78,9 @@ CONFIG_SAM34_UART1=y
CONFIG_SAM34_UDP=y
CONFIG_SAM34_USART1=y
CONFIG_SAM34_WDT=y
CONFIG_SCHED_CPULOAD=y
CONFIG_SCHED_CPULOAD_EXTCLK=y
CONFIG_SCHED_CPULOAD_TICKSPERSEC=222
CONFIG_SCHED_CPULOAD=y
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
@ -92,8 +90,8 @@ CONFIG_SYSTEMTICK_EXTCLK=y
CONFIG_TASK_NAME_SIZE=15
CONFIG_UART1_SERIAL_CONSOLE=y
CONFIG_USBDEV=y
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_USERMAIN_STACKSIZE=4096
CONFIG_USER_ENTRYPOINT="nsh_main"
CONFIG_WATCHDOG=y
CONFIG_WDT_ENABLED_ON_RESET=y
CONFIG_WDT_THREAD_STACKSIZE=512

1
configs/sam4s-xplained-pro/scripts/sam4s-xplained-pro.ld
View File

@ -49,6 +49,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{

7
configs/sam4s-xplained/nsh/defconfig
View File

@ -1,15 +1,14 @@
# CONFIG_NSH_CMDOPT_DF_H is not set
# CONFIG_NSH_DISABLE_IFCONFIG is not set
# CONFIG_NSH_DISABLE_PS is not set
# CONFIG_SAM34_UART0 is not set
CONFIG_ARCH_BOARD_SAM4S_XPLAINED=y
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="sam4s-xplained"
CONFIG_ARCH_BOARD_SAM4S_XPLAINED=y
CONFIG_ARCH_BUTTONS=y
CONFIG_ARCH_CHIP_ATSAM4S16C=y
CONFIG_ARCH_CHIP_SAM34=y
CONFIG_ARCH_CHIP_SAM4S=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH="arm"
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_BOARD_LOOPSPERMSEC=9186
@ -18,8 +17,8 @@ CONFIG_CXX_NEWLONG=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_MOUNTPOINT=y
CONFIG_DISABLE_POLL=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_EXAMPLES_NSH=y
CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_MAX_TASKS=16

1
configs/sam4s-xplained/scripts/sam4s-xplained.ld
View File

@ -44,6 +44,7 @@ MEMORY
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(_stext)
SECTIONS
{