TM4C129X: A small step toward understanding new Tiva clocking
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@ -46,6 +46,18 @@
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* Pre-processor Definitions
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************************************************************************************/
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/* Helpers for use with the TM4C129 version of tiva_clockconfig() */
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# define M2PLLFREQ0(mint,mfrac) \
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((uint32_t)((mint) << SYSCON_PLLFREQ0_MINT_SHIFT) | \
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(uint32_t)((mfrac) << SYSCON_PLLFREQ0_MFRAC_SHIFT))
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# define QN2PLLFREQ1(q,n) \
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((uint32_t)(((n) - 1) << SYSCON_PLLFREQ1_N_SHIFT) | \
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(uint32_t)(((q) - 1) << SYSCON_PLLFREQ1_Q_SHIFT))
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -69,6 +81,38 @@ extern "C"
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* Public Function Prototypes
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****************************************************************************/
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/****************************************************************************
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* Name: tiva_clockconfig
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*
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* Description:
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* Called to change to new clock based on desired pllfreq0, pllfreq1, and
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* sysdiv settings. This is use to set up the initial clocking but can be
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* used later to support slow clocked, low power consumption modes.
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*
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* The pllfreq0 and pllfreq1 settings derive from the PLL M, N, and Q
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* values to generate Fvco like:
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*
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* Fin = Fxtal / (Q + 1 )(N + 1) -OR- Fpiosc / (Q + 1)(N + 1)
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* Mdiv = Mint + (MFrac / 1024)
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* Fvco = Fin * Mdiv
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*
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* When the PLL is active, the system clock frequency (SysClk) is calculated
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* using the following equation:
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*
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* SysClk = Fvco/ (sysdiv + 1)
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*
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* See the helper macros M2PLLFREQ0(mint,mfrac) and QN2PLLFREQ1(q,n).
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*
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* NOTE: The input clock to the PLL may be either the external crystal
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* (Fxtal) or PIOSC (Fpiosc). This logic supports only the external
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* crystal as the PLL source clock.
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*
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****************************************************************************/
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void tiva_clockconfig(uint32_t pllfreq0, uint32_t pllfreq1, uint32_t sysdiv);
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#else
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/****************************************************************************
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* Name: tiva_clockconfig
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*
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@ -80,6 +124,7 @@ extern "C"
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****************************************************************************/
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void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2);
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#endif
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/****************************************************************************
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* Name: up_clockconfig
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@ -150,13 +150,31 @@ static inline void tiva_pll_lock(void)
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* Name: tiva_clockconfig
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*
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* Description:
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* Called to change to new clock based on desired rcc and rcc2 settings.
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* This is use to set up the initial clocking but can be used later to
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* support slow clocked, low power consumption modes.
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* Called to change to new clock based on desired pllfreq0, pllfreq1, and
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* sysdiv settings. This is use to set up the initial clocking but can be
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* used later to support slow clocked, low power consumption modes.
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*
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* The pllfreq0 and pllfreq1 settings derive from the PLL M, N, and Q
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* values to generate Fvco like:
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*
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* Fin = Fxtal / (Q + 1 )(N + 1) -OR- Fpiosc / (Q + 1)(N + 1)
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* Mdiv = Mint + (MFrac / 1024)
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* Fvco = Fin * Mdiv
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*
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* When the PLL is active, the system clock frequency (SysClk) is calculated
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* using the following equation:
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*
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* SysClk = Fvco/ (sysdiv + 1)
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*
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* See the helper macros M2PLLFREQ0(mint,mfrac) and QN2PLLFREQ1(q,n).
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*
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* NOTE: The input clock to the PLL may be either the external crystal
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* (Fxtal) or PIOSC (Fpiosc). This logic supports only the external
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* crystal as the PLL source clock.
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*
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****************************************************************************/
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void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
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void tiva_clockconfig(uint32_t pllfreq0, uint32_t pllfreq1, uint32_t sysdiv)
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{
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#warning Missing logic
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}
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@ -172,8 +190,14 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
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void up_clockconfig(void)
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{
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uint32_t pllfreq0;
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uint32_t pllfreq1;
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/* Set the clocking to run with the default settings provided in the board.h
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* header file
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*/
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#warning Missing logic
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pllfreq0 = M2PLLFREQ0(BOARD_PLL_MINT, BOARD_PLL_MFRAC);
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pllfreq1 = QN2PLLFREQ1(BOARD_PLL_Q, BOARD_PLL_N);
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tiva_clockconfig(pllfreq0, pllfreq1, BOARD_PLL_SYSDIV);
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}
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@ -50,69 +50,52 @@
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/* Clocking *************************************************************************/
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/* RCC settings. Crystals on-board the TMC4C123G LaunchPad include:
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/* Crystals on-board the DK-TM4C129X include:
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*
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* 16MHz connected to OSC0/1 (pins 40/41)
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* 32.768kHz connected to XOSC0/1 (pins 34/36)
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* 1. 25.0MHz (Y2) is connected to OSC0/1 pins and is used as the run mode input to
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* the PLL.
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* 2. 32.768kHz (Y3) connected to XOSC0/1 and clocks the hibernation module.
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*/
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#define SYSCON_RCC_XTAL SYSCON_RCC_XTAL16000KHZ /* On-board crystal is 16 MHz */
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#define XTAL_FREQUENCY 16000000
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#define SYSCON_RCC_XTAL SYSCON_RCC_XTAL16000KHZ /* On-board crystal is 25 MHz */
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#define XTAL_FREQUENCY 25000000
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/* Oscillator source is the main oscillator */
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#define SYSCON_RCC_OSCSRC SYSCON_RCC_OSCSRC_MOSC
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#define SYSCON_RCC2_OSCSRC SYSCON_RCC2_OSCSRC2_MOSC
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#define OSCSRC_FREQUENCY XTAL_FREQUENCY
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/* Use system divider = 4; this corresponds to a system clock frequency
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* of (400 / 1) / 5 = 80MHz (Using RCC2 and DIV400).
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/* The PLL generates Fvco according to the following formulae. The input clock to
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* the PLL may be either the external crystal (Fxtal) or PIOSC (Fpiosc). This
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* logic supports only the external crystal as the PLL source clock.
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*
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* Fin = Fxtal / (Q + 1 )(N + 1) -OR- Fpiosc / (Q + 1)(N + 1)
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* Mdiv = Mint + (MFrac / 1024)
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* Fvco = Fin * Mdiv
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*
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* Where the register fields Q and N actually hold (Q-1) and (N-1). The following
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* setup then generates Fvco = 480MHz:
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*
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* Fin = 25 MHz / 1 / 5 = 5 MHz
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* Mdiv = 96
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* Fvco = 480
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*/
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#define TIVA_SYSDIV 5
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#define SYSCLK_FREQUENCY 80000000 /* 80MHz */
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#define BOARD_PLL_MINT 96 /* Integer part of PLL M value */
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#define BOARD_PLL_MFRAC 0 /* Fractional part of PLL M value */
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#define BOARD_PLL_N 5 /* PLL N value */
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#define BOARD_PLL_Q 1 /* PLL Q value */
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/* Other RCC settings:
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#define BOARD_FVCO_FREQUENCY 480000000 /* Resulting Fvco */
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/* When the PLL is active, the system clock frequency (SysClk) is calculated using
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* the following equation:
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*
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* - Main and internal oscillators enabled.
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* - PLL and sys dividers not bypassed
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* - PLL not powered down
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* - No auto-clock gating reset
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* SysClk = Fvco/ (sysdiv + 1)
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*
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* The following setup generates Sysclk = 120MHz:
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*/
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#define TIVA_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | \
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SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(TIVA_SYSDIV))
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/* RCC2 settings
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*
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* - PLL and sys dividers not bypassed.
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* - PLL not powered down
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* - Not using RCC2
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*
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* When SYSCON_RCC2_DIV400 is not selected, SYSDIV2 is the divisor-1.
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* When SYSCON_RCC2_DIV400 is selected, SYSDIV2 is the divisor-1)/2, plus
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* the LSB:
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*
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* SYSDIV2 SYSDIV2LSB DIVISOR
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* 0 N/A 2
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* 1 0 3
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* " 1 4
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* 2 0 5
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* " 1 6
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* etc.
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*/
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#if (TIVA_SYSDIV & 1) == 0
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# define TIVA_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV2LSB | \
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SYSCON_RCC2_SYSDIV_DIV400(TIVA_SYSDIV) | \
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SYSCON_RCC2_DIV400 | SYSCON_RCC2_USERCC2)
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#else
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# define TIVA_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV_DIV400(TIVA_SYSDIV) | \
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SYSCON_RCC2_DIV400 | SYSCON_RCC2_USERCC2)
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#endif
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#define BOARD_PLL_SYSDIV 4 /* Sysclk = Fvco / 4 = 120MHz */
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#define SYSCLK_FREQUENCY 120000000 /* Resulting SysClk frequency */
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/* LED definitions ******************************************************************/
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/* The TMC4C123G LaunchPad has a single RGB LED. There is only one visible LED which
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/* The DK-TM4C129X has a single RGB LED. There is only one visible LED which
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* will vary in color. But, from the standpoint of the firmware, this appears as
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* three LEDs:
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*
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