diff --git a/arch/arm/src/tiva/tiva_syscontrol.h b/arch/arm/src/tiva/tiva_syscontrol.h
index 99baf9cba6..b012a27463 100644
--- a/arch/arm/src/tiva/tiva_syscontrol.h
+++ b/arch/arm/src/tiva/tiva_syscontrol.h
@@ -46,6 +46,18 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
+#ifdef CONFIG_ARCH_CHIP_TM4C129
+/* Helpers for use with the TM4C129 version of tiva_clockconfig() */
+
+#  define M2PLLFREQ0(mint,mfrac) \
+     ((uint32_t)((mint) << SYSCON_PLLFREQ0_MINT_SHIFT) | \
+      (uint32_t)((mfrac) << SYSCON_PLLFREQ0_MFRAC_SHIFT))
+
+#  define QN2PLLFREQ1(q,n) \
+     ((uint32_t)(((n) - 1) << SYSCON_PLLFREQ1_N_SHIFT) | \
+      (uint32_t)(((q) - 1) << SYSCON_PLLFREQ1_Q_SHIFT))
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -69,6 +81,38 @@ extern "C"
  * Public Function Prototypes
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_CHIP_TM4C129
+/****************************************************************************
+ * Name: tiva_clockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on desired pllfreq0, pllfreq1, and
+ *   sysdiv settings.  This is use to set up the initial clocking but can be
+ *   used later to support slow clocked, low power consumption modes.
+ *
+ *   The pllfreq0 and pllfreq1 settings derive from the PLL M, N, and Q
+ *   values to generate Fvco like:
+ *
+ *     Fin  = Fxtal / (Q + 1 )(N + 1) -OR- Fpiosc / (Q + 1)(N + 1)
+ *     Mdiv = Mint + (MFrac / 1024)
+ *     Fvco = Fin * Mdiv
+ *
+ * When the PLL is active, the system clock frequency (SysClk) is calculated
+ * using the following equation:
+ *
+ *   SysClk = Fvco/ (sysdiv + 1)
+ *
+ * See the helper macros M2PLLFREQ0(mint,mfrac) and QN2PLLFREQ1(q,n).
+ *
+ * NOTE: The input clock to the PLL may be either the external crystal
+ * (Fxtal) or PIOSC (Fpiosc).  This logic supports only the external
+ * crystal as the PLL source clock.
+ *
+ ****************************************************************************/
+
+void tiva_clockconfig(uint32_t pllfreq0, uint32_t pllfreq1, uint32_t sysdiv);
+
+#else
 /****************************************************************************
  * Name: tiva_clockconfig
  *
@@ -80,6 +124,7 @@ extern "C"
  ****************************************************************************/
 
 void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2);
+#endif
 
 /****************************************************************************
  * Name: up_clockconfig
diff --git a/arch/arm/src/tiva/tm4c129_syscontrol.c b/arch/arm/src/tiva/tm4c129_syscontrol.c
index f7436ca98d..3be5b68cce 100644
--- a/arch/arm/src/tiva/tm4c129_syscontrol.c
+++ b/arch/arm/src/tiva/tm4c129_syscontrol.c
@@ -150,13 +150,31 @@ static inline void tiva_pll_lock(void)
  * Name: tiva_clockconfig
  *
  * Description:
- *   Called to change to new clock based on desired rcc and rcc2 settings.
- *   This is use to set up the initial clocking but can be used later to
- *   support slow clocked, low power consumption modes.
+ *   Called to change to new clock based on desired pllfreq0, pllfreq1, and
+ *   sysdiv settings.  This is use to set up the initial clocking but can be
+ *   used later to support slow clocked, low power consumption modes.
+ *
+ *   The pllfreq0 and pllfreq1 settings derive from the PLL M, N, and Q
+ *   values to generate Fvco like:
+ *
+ *     Fin  = Fxtal / (Q + 1 )(N + 1) -OR- Fpiosc / (Q + 1)(N + 1)
+ *     Mdiv = Mint + (MFrac / 1024)
+ *     Fvco = Fin * Mdiv
+ *
+ * When the PLL is active, the system clock frequency (SysClk) is calculated
+ * using the following equation:
+ *
+ *   SysClk = Fvco/ (sysdiv + 1)
+ *
+ * See the helper macros M2PLLFREQ0(mint,mfrac) and QN2PLLFREQ1(q,n).
+ *
+ * NOTE: The input clock to the PLL may be either the external crystal
+ * (Fxtal) or PIOSC (Fpiosc).  This logic supports only the external
+ * crystal as the PLL source clock.
  *
  ****************************************************************************/
 
-void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
+void tiva_clockconfig(uint32_t pllfreq0, uint32_t pllfreq1, uint32_t sysdiv)
 {
 #warning Missing logic
 }
@@ -172,8 +190,14 @@ void tiva_clockconfig(uint32_t newrcc, uint32_t newrcc2)
 
 void up_clockconfig(void)
 {
+  uint32_t pllfreq0;
+  uint32_t pllfreq1;
+
   /* Set the clocking to run with the default settings provided in the board.h
    * header file
    */
-#warning Missing logic
+
+  pllfreq0 = M2PLLFREQ0(BOARD_PLL_MINT, BOARD_PLL_MFRAC);
+  pllfreq1 = QN2PLLFREQ1(BOARD_PLL_Q, BOARD_PLL_N);
+  tiva_clockconfig(pllfreq0, pllfreq1, BOARD_PLL_SYSDIV);
 }
diff --git a/configs/dk-tm4c129x/include/board.h b/configs/dk-tm4c129x/include/board.h
index d474a1348b..e620d22f0e 100644
--- a/configs/dk-tm4c129x/include/board.h
+++ b/configs/dk-tm4c129x/include/board.h
@@ -50,69 +50,52 @@
 
 /* Clocking *************************************************************************/
 
-/* RCC settings.  Crystals on-board the TMC4C123G LaunchPad include:
+/* Crystals on-board the DK-TM4C129X include:
  *
- *   16MHz connected to OSC0/1 (pins 40/41)
- *   32.768kHz connected to XOSC0/1 (pins 34/36)
+ * 1. 25.0MHz (Y2) is connected to OSC0/1 pins and is used as the run mode input to
+ *    the PLL.
+ * 2. 32.768kHz (Y3) connected to XOSC0/1 and clocks the hibernation module.
  */
 
-#define SYSCON_RCC_XTAL      SYSCON_RCC_XTAL16000KHZ /* On-board crystal is 16 MHz */
-#define XTAL_FREQUENCY       16000000
+#define SYSCON_RCC_XTAL      SYSCON_RCC_XTAL16000KHZ /* On-board crystal is 25 MHz */
+#define XTAL_FREQUENCY       25000000
 
-/* Oscillator source is the main oscillator */
-
-#define SYSCON_RCC_OSCSRC    SYSCON_RCC_OSCSRC_MOSC
-#define SYSCON_RCC2_OSCSRC   SYSCON_RCC2_OSCSRC2_MOSC
-#define OSCSRC_FREQUENCY     XTAL_FREQUENCY
-
-/* Use system divider = 4; this corresponds to a system clock frequency
- * of (400 / 1) / 5 = 80MHz (Using RCC2 and DIV400).
+/* The PLL generates Fvco according to the following formulae.  The input clock to
+ * the PLL may be either the external crystal (Fxtal) or PIOSC (Fpiosc).  This
+ * logic supports only the external crystal as the PLL source clock.
+ *
+ *   Fin  = Fxtal / (Q + 1 )(N + 1) -OR- Fpiosc / (Q + 1)(N + 1)
+ *   Mdiv = Mint + (MFrac / 1024)
+ *   Fvco = Fin * Mdiv
+ *
+ * Where the register fields Q and N actually hold (Q-1) and (N-1).   The following
+ * setup then generates Fvco = 480MHz:
+ *
+ *   Fin  = 25 MHz / 1 / 5 = 5 MHz
+ *   Mdiv = 96
+ *   Fvco = 480
  */
 
-#define TIVA_SYSDIV          5
-#define SYSCLK_FREQUENCY     80000000  /* 80MHz */
+#define BOARD_PLL_MINT       96        /* Integer part of PLL M value */
+#define BOARD_PLL_MFRAC      0         /* Fractional part of PLL M value */
+#define BOARD_PLL_N          5         /* PLL N value */
+#define BOARD_PLL_Q          1         /* PLL Q value */
 
-/* Other RCC settings:
+#define BOARD_FVCO_FREQUENCY 480000000 /* Resulting Fvco */
+
+/* When the PLL is active, the system clock frequency (SysClk) is calculated using
+ * the following equation:
  *
- * - Main and internal oscillators enabled.
- * - PLL and sys dividers not bypassed
- * - PLL not powered down
- * - No auto-clock gating reset
+ *   SysClk = Fvco/ (sysdiv + 1)
+ *
+ * The following setup generates Sysclk = 120MHz:
  */
 
-#define TIVA_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | \
-                      SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(TIVA_SYSDIV))
-
-/* RCC2 settings
- *
- * - PLL and sys dividers not bypassed.
- * - PLL not powered down
- * - Not using RCC2
- *
- * When SYSCON_RCC2_DIV400 is not selected, SYSDIV2 is the divisor-1.
- * When SYSCON_RCC2_DIV400 is selected, SYSDIV2 is the divisor-1)/2, plus
- * the LSB:
- *
- * SYSDIV2 SYSDIV2LSB DIVISOR
- *   0       N/A         2
- *   1       0           3
- *   "       1           4
- *   2       0           5
- *   "       1           6
- *   etc.
- */
-
-#if (TIVA_SYSDIV & 1) == 0
-#  define TIVA_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV2LSB | \
-                           SYSCON_RCC2_SYSDIV_DIV400(TIVA_SYSDIV) | \
-                           SYSCON_RCC2_DIV400 | SYSCON_RCC2_USERCC2)
-#else
-#  define TIVA_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV_DIV400(TIVA_SYSDIV) | \
-                           SYSCON_RCC2_DIV400 | SYSCON_RCC2_USERCC2)
-#endif
+#define BOARD_PLL_SYSDIV     4         /* Sysclk = Fvco / 4 = 120MHz */
+#define SYSCLK_FREQUENCY     120000000 /* Resulting SysClk frequency */
 
 /* LED definitions ******************************************************************/
-/* The TMC4C123G LaunchPad has a single RGB LED.  There is only one visible LED which
+/* The DK-TM4C129X has a single RGB LED.  There is only one visible LED which
  * will vary in color.  But, from the standpoint of the firmware, this appears as
  * three LEDs:
  *