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Minor changes while pondering a camera interface

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This commit is contained in:
Gregory Nutt 2013-10-29 16:57:06 -06:00
parent 08b85d4465
commit dda3d9c47e
3 changed files with 25 additions and 4 deletions
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4
arch/Kconfig
View File

@ -296,5 +296,5 @@ config FLASH_SIZE
The size in bytes of the installed boot FLASH. "Boot" FLASH
refers to the FLASH that you link program code into.
endif
endmenu
endif # BOOT_RUNFROMFLASH && ARCH_HAVE_MMU
endmenu # Boot Memory Configuration

21
arch/arm/src/sama5/chip/sam_isi.h
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@ -325,4 +325,25 @@
# define ISI_WPSR_WPVSRC_R2Y_SET1 (8 << ISI_WPSR_WPVSRC_SHIFT) /* Write access in ISI_R2Y_SET1 */
# define ISI_WPSR_WPVSRC_R2Y_SET2 (9 << ISI_WPSR_WPVSRC_SHIFT) /* Write access in ISI_R2Y_SET2 */
/************************************************************************************
* Public Types
************************************************************************************/
/* "The destination frame buffers are defined by a series of Frame Buffer Descriptors
* (FBD). Each FBD controls the transfer of one entire frame and then optionally
* loads a further FBD to switch the DMA operation at another frame buffer address.
*
* "The FBD is defined by a series of three words. The first one defines the current
* frame buffer address (named DMA_X_ADDR register), the second defines control
* information (named DMA_X_CTRL register) and the third defines the next descriptor
* address (named DMA_X_DSCR). DMA transfer mode with linked list support is
* available for both codec and preview datapath."
*/
struct isi_dscr_s
{
uint32_t addr; /* Current framebuffer address */
uint32_t ctrl; /* Control information */
uint32_t dscr; /* Next descriptor address */
};
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ISI_H */

4
arch/arm/src/sama5/chip/sama5d3x_pinmap.h
View File

@ -190,8 +190,6 @@
#define PIO_ISI_D0 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN16) /* Type: GPIO */
#define PIO_ISI_D1 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN17) /* Type: GPIO */
#define PIO_ISI_D10 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN27) /* Type: GPIO */
#define PIO_ISI_D11 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN26) /* Type: GPIO */
#define PIO_ISI_D2 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN18) /* Type: GPIO */
#define PIO_ISI_D3 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN19) /* Type: GPIO */
#define PIO_ISI_D4 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN20) /* Type: GPIO */
@ -200,6 +198,8 @@
#define PIO_ISI_D7 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN23) /* Type: GPIO */
#define PIO_ISI_D8 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN29) /* Type: GPIO */
#define PIO_ISI_D9 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN28) /* Type: GPIO */
#define PIO_ISI_D10 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN27) /* Type: GPIO */
#define PIO_ISI_D11 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN26) /* Type: GPIO */
#define PIO_ISI_HSYNC (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN31) /* Type: GPIO */
#define PIO_ISI_PCK (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN30) /* Type: GPIO */
#define PIO_ISI_VSYNC (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOA | PIO_PIN30) /* Type: GPIO */