Misc fixes to get SDRAM support and RAM test to build for the Open1788 platform
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5793 42af7a65-404d-4744-a932-0658087f49c3
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@ -105,19 +105,9 @@ config ARCH_FAMILY_LPC176X
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config ARCH_FAMILY_LPC177X
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bool
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select ARCH_HAVE_EXTNAND
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select ARCH_HAVE_EXTSRAM0
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select ARCH_HAVE_EXTDRAM
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select ARCH_HAVE_EXTNOR
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select ARCH_HAVE_SDIO
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config ARCH_FAMILY_LPC178X
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bool
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select ARCH_HAVE_EXTNAND
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select ARCH_HAVE_EXTSRAM0
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select ARCH_HAVE_EXTDRAM
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select ARCH_HAVE_EXTNOR
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select ARCH_HAVE_SDIO
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config ARCH_HAVE_SPIFI
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bool
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@ -143,6 +133,10 @@ config LPC17_EMC
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bool "EMC"
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default y
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depends on ARCH_FAMILY_LPC178X
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select ARCH_HAVE_EXTNAND
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select ARCH_HAVE_EXTSRAM0
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select ARCH_HAVE_EXTDRAM
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select ARCH_HAVE_EXTNOR
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config LPC17_ETHERNET
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bool "Ethernet"
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@ -172,7 +166,8 @@ config LPC17_USBOTG
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config LPC17_SDCARD
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bool "SD Card Interface"
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depends on ARCH_HAVE_SDIO
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depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X
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select ARCH_HAVE_SDIO
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default n
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config LPC17_UART0
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@ -499,7 +499,7 @@
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#define GPIO_EMC_D9 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN9)
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#define GPIO_EMC_D10 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN10)
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#define GPIO_EMC_D11 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN11)
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#define GPIO_EMC_12 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN12)
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#define GPIO_EMC_D12 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN12)
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#define GPIO_EMC_D13 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN13)
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#define GPIO_EMC_D14 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN14)
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#define GPIO_EMC_D15 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN15)
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@ -277,7 +277,12 @@
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/* 0: EMC uses same clock as CPU */
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/* 1: EMC uses half the rate of CPU */
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/* Bits 1-31: Reserved */
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/* CPU Clock Selection register */
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/* EMC Clock Selection Register */
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#define SYSCON_EMCCLKSEL_CCLK_DIV2 (1 << 0) /* Bit 0: 1=EMC used CPU clock / 2 */
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#define SYSCON_EMCCLKSEL_CCLK_DIV1 (0) /* 0=EMC used CPU clock */
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/* CPU Clock Selection Register */
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#define SYSCON_CCLKSEL_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */
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#define SYSCON_CCLKSEL_CCLKDIV_MASK (0x1f << SYSCON_CCLKSEL_CCLKDIV_SHIFT)
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@ -42,7 +42,12 @@
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#include <arch/irq.h>
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#include "lpc17_syscon.h"
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "chip/lpc17_syscon.h"
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#include "lpc17_gpio.h"
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#include "lpc17_emc.h"
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/****************************************************************************
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@ -33,8 +33,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H
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#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H
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/****************************************************************************
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* Included Files
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@ -71,4 +71,4 @@
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void lpc17_emcinitialize(void);
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#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H */
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H */
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