Misc fixes to get SDRAM support and RAM test to build for the Open1788 platform

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5793 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-03-27 14:28:43 +00:00
parent 927d8f46e2
commit ddb8ec390c
5 changed files with 22 additions and 17 deletions

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@ -105,19 +105,9 @@ config ARCH_FAMILY_LPC176X
config ARCH_FAMILY_LPC177X
bool
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTDRAM
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_SDIO
config ARCH_FAMILY_LPC178X
bool
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTDRAM
select ARCH_HAVE_EXTNOR
select ARCH_HAVE_SDIO
config ARCH_HAVE_SPIFI
bool
@ -143,6 +133,10 @@ config LPC17_EMC
bool "EMC"
default y
depends on ARCH_FAMILY_LPC178X
select ARCH_HAVE_EXTNAND
select ARCH_HAVE_EXTSRAM0
select ARCH_HAVE_EXTDRAM
select ARCH_HAVE_EXTNOR
config LPC17_ETHERNET
bool "Ethernet"
@ -172,7 +166,8 @@ config LPC17_USBOTG
config LPC17_SDCARD
bool "SD Card Interface"
depends on ARCH_HAVE_SDIO
depends on ARCH_FAMILY_LPC177X || ARCH_FAMILY_LPC178X
select ARCH_HAVE_SDIO
default n
config LPC17_UART0

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@ -499,7 +499,7 @@
#define GPIO_EMC_D9 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN9)
#define GPIO_EMC_D10 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN10)
#define GPIO_EMC_D11 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN11)
#define GPIO_EMC_12 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN12)
#define GPIO_EMC_D12 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN12)
#define GPIO_EMC_D13 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN13)
#define GPIO_EMC_D14 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN14)
#define GPIO_EMC_D15 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT3 | GPIO_PIN15)

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@ -277,7 +277,12 @@
/* 0: EMC uses same clock as CPU */
/* 1: EMC uses half the rate of CPU */
/* Bits 1-31: Reserved */
/* CPU Clock Selection register */
/* EMC Clock Selection Register */
#define SYSCON_EMCCLKSEL_CCLK_DIV2 (1 << 0) /* Bit 0: 1=EMC used CPU clock / 2 */
#define SYSCON_EMCCLKSEL_CCLK_DIV1 (0) /* 0=EMC used CPU clock */
/* CPU Clock Selection Register */
#define SYSCON_CCLKSEL_CCLKDIV_SHIFT (0) /* 0-4: Divide value for CPU clock (CCLK) */
#define SYSCON_CCLKSEL_CCLKDIV_MASK (0x1f << SYSCON_CCLKSEL_CCLKDIV_SHIFT)

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@ -42,7 +42,12 @@
#include <arch/irq.h>
#include "lpc17_syscon.h"
#include <arch/board/board.h>
#include "up_arch.h"
#include "chip/lpc17_syscon.h"
#include "lpc17_gpio.h"
#include "lpc17_emc.h"
/****************************************************************************

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@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H
#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H
#define __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H
/****************************************************************************
* Included Files
@ -71,4 +71,4 @@
void lpc17_emcinitialize(void);
#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H */
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_EMC_H */