s32k3xx:EDMA Add Error handeling
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@ -749,6 +749,7 @@ static int s32k3xx_edma_interrupt(int irq, void *context, void *arg)
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struct s32k3xx_dmach_s *dmach;
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uint32_t regval32;
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uint32_t errval32;
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uint8_t chan;
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int result;
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@ -760,6 +761,29 @@ static int s32k3xx_edma_interrupt(int irq, void *context, void *arg)
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chan = dmach->chan;
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DEBUGASSERT(chan < S32K3XX_EDMA_NCHANNELS && dmach == &g_edma.dmach[chan]);
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/* Get the eDMA Error Status register value. */
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errval32 = getreg32(S32K3XX_EDMA_TCD[chan] +
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S32K3XX_EDMA_CH_ES_OFFSET);
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if (errval32 & EDMA_CH_ES_ERR)
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{
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DEBUGASSERT(dmach->state == S32K3XX_DMA_ACTIVE);
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/* Clear the error */
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putreg32(EDMA_CH_ES_ERR, S32K3XX_EDMA_TCD[chan] +
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S32K3XX_EDMA_CH_ES_OFFSET);
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/* Clear the pending eDMA channel interrupt */
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putreg32(EDMA_CH_INT, S32K3XX_EDMA_TCD[chan] +
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S32K3XX_EDMA_CH_INT_OFFSET);
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s32k3xx_dmaterminate(dmach, -EIO);
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return OK;
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}
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/* Check for an eDMA pending interrupt on this channel */
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regval32 = getreg32(S32K3XX_EDMA_INT);
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@ -1332,7 +1356,7 @@ int s32k3xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback,
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regval = getreg32(S32K3XX_EDMA_TCD[chan]
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+ S32K3XX_EDMA_CH_CSR_OFFSET);
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regval |= EDMA_CH_CSR_ERQ;
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regval |= EDMA_CH_CSR_ERQ | EDMA_CH_CSR_EEI;
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putreg32(regval, S32K3XX_EDMA_TCD[chan] + S32K3XX_EDMA_CH_CSR_OFFSET);
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}
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