diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index 27280620d3..ac604e4fd5 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/stm32l4_usbhost.h * * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. @@ -32,14 +32,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -58,9 +58,9 @@ # error "Unsupported STM32L4 chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifdef HAVE_USBHOST_TRACE enum usbhost_trace1codes_e @@ -85,7 +85,7 @@ enum usbhost_trace1codes_e OTGFS_VTRACE1_GINT_PTXFE, /* OTGFS Handle the periodic TxFIFO empty interrupt */ OTGFS_VTRACE1_GINT_HC, /* OTGFS Handle the host channels interrupt */ OTGFS_VTRACE1_GINT_HPRT, /* OTGFS Handle the host port interrupt */ - OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change*/ + OTGFS_VTRACE1_GINT_HPRT_POCCHNG, /* OTGFS HPRT: Port Over-Current Change */ OTGFS_VTRACE1_GINT_HPRT_PCDET, /* OTGFS HPRT: Port Connect Detect */ OTGFS_VTRACE1_GINT_HPRT_PENCHNG, /* OTGFS HPRT: Port Enable Changed */ OTGFS_VTRACE1_GINT_HPRT_LSDEV, /* OTGFS HPRT: Low Speed Device Connected */ @@ -139,11 +139,11 @@ enum usbhost_trace1codes_e #endif -/************************************************************************************ - * Public Functions - ************************************************************************************/ -/* - * STM32L4 USB OTG FS Host Driver Support +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* STM32L4 USB OTG FS Host Driver Support * * Pre-requisites * @@ -157,8 +157,8 @@ enum usbhost_trace1codes_e * Default 128 (512 bytes) * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit - * words. Default 96 (384 bytes) + * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * 32-bit words. Default 96 (384 bytes) * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * @@ -166,9 +166,9 @@ enum usbhost_trace1codes_e * debug. Depends on CONFIG_DEBUG. */ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -181,31 +181,34 @@ extern "C" #define EXTERN extern #endif -/*********************************************************************************** +/**************************************************************************** * Name: stm32l4_usbhost_vbusdrive * * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided be - * each platform that implements the STM32L4 OTG FS host interface + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32L4 OTG FS host + * interface * - * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump - * or, if 5 V are available on the application board, a basic power switch, must - * be added externally to drive the 5 V VBUS line. The external charge pump can - * be driven by any GPIO output. When the application decides to power on VBUS - * using the chosen GPIO, it must also set the port power bit in the host port - * control and status register (PPWR bit in OTG_FS_HPRT). + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge + * pump or, if 5 V are available on the application board, a basic power + * switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). * - * "The application uses this field to control power to this port, and the core - * clears this bit on an over current condition." + * "The application uses this field to control power to this port, and the + * core clears this bit on an over current condition." * * Input Parameters: - * iface - For future growth to handle multiple USB host interface. Should be zero. + * iface - For future growth to handle multiple USB host interface. + * Should be zero. * enable - true: enable VBUS power; false: disable VBUS power * * Returned Value: * None * - ***********************************************************************************/ + ****************************************************************************/ void stm32l4_usbhost_vbusdrive(int iface, bool enable); diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c index 6ede922c74..8ee37586ce 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c +++ b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c @@ -80,63 +80,108 @@ struct stm32l4_usbhost_trace_s static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = { - TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, "OTGFS ERROR: Host Port %d. Device disconnected\n"), - TRENTRY(OTGFS_TRACE1_IRQATTACH, TR_FMT1, "OTGFS ERROR: Failed to attach IRQ\n"), - TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, TR_FMT1, "OTGFS ERROR: Transfer Failed. ret=%d\n"), - TRENTRY(OTGFS_TRACE1_SENDSETUP, TR_FMT1, "OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"), - TRENTRY(OTGFS_TRACE1_SENDDATA, TR_FMT1, "OTGFS ERROR: ctrl_senddata() failed with: %d\n"), - TRENTRY(OTGFS_TRACE1_RECVDATA, TR_FMT1, "OTGFS ERROR: ctrl_recvdata() failed with: %d\n"), + TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, + "OTGFS ERROR: Host Port %d. Device disconnected\n"), + TRENTRY(OTGFS_TRACE1_IRQATTACH, TR_FMT1, + "OTGFS ERROR: Failed to attach IRQ\n"), + TRENTRY(OTGFS_TRACE1_TRNSFRFAILED, TR_FMT1, + "OTGFS ERROR: Transfer Failed. ret=%d\n"), + TRENTRY(OTGFS_TRACE1_SENDSETUP, TR_FMT1, + "OTGFS ERROR: ctrl_sendsetup() failed with: %d\n"), + TRENTRY(OTGFS_TRACE1_SENDDATA, TR_FMT1, + "OTGFS ERROR: ctrl_senddata() failed with: %d\n"), + TRENTRY(OTGFS_TRACE1_RECVDATA, TR_FMT1, + "OTGFS ERROR: ctrl_recvdata() failed with: %d\n"), #ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(OTGFS_VTRACE1_CONNECTED, TR_FMT1, "OTGFS Host Port %d connected.\n"), - TRENTRY(OTGFS_VTRACE1_DISCONNECTED, TR_FMT1, "OTGFS Host Port %d disconnected.\n"), - TRENTRY(OTGFS_VTRACE1_GINT, TR_FMT1, "OTGFS Handling Interrupt. Entry Point.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_SOF, TR_FMT1, "OTGFS Handle the start of frame interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, TR_FMT1, "OTGFS Handle the RxFIFO non-empty interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, TR_FMT1, "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, TR_FMT1, "OTGFS Handle the periodic TxFIFO empty interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HC, TR_FMT1, "OTGFS Handle the host channels interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT, TR_FMT1, "OTGFS Handle the host port interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1, "OTGFS HPRT: Port Over-Current Change.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1, "OTGFS HPRT: Port Connect Detect.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1, "OTGFS HPRT: Port Enable Changed.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1, "OTGFS HPRT: Low Speed Device Connected.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, TR_FMT1, "OTGFS HPRT: Full Speed Device Connected.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, TR_FMT1, "OTGFS HPRT: Host Switch: LS -> FS.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, TR_FMT1, "OTGFS HPRT: Host Switch: FS -> LS.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_DISC, TR_FMT1, "OTGFS Handle the disconnect detected interrupt.\n"), - TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, TR_FMT1, "OTGFS Handle the incomplete periodic transfer.\n"), + TRENTRY(OTGFS_VTRACE1_CONNECTED, TR_FMT1, + "OTGFS Host Port %d connected.\n"), + TRENTRY(OTGFS_VTRACE1_DISCONNECTED, TR_FMT1, + "OTGFS Host Port %d disconnected.\n"), + TRENTRY(OTGFS_VTRACE1_GINT, TR_FMT1, + "OTGFS Handling Interrupt. Entry Point.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_SOF, TR_FMT1, + "OTGFS Handle the start of frame interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_RXFLVL, TR_FMT1, + "OTGFS Handle the RxFIFO non-empty interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_NPTXFE, TR_FMT1, + "OTGFS Handle the non-periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_PTXFE, TR_FMT1, + "OTGFS Handle the periodic TxFIFO empty interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HC, TR_FMT1, + "OTGFS Handle the host channels interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT, TR_FMT1, + "OTGFS Handle the host port interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_POCCHNG, TR_FMT1, + "OTGFS HPRT: Port Over-Current Change.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PCDET, TR_FMT1, + "OTGFS HPRT: Port Connect Detect.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_PENCHNG, TR_FMT1, + "OTGFS HPRT: Port Enable Changed.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSDEV, TR_FMT1, + "OTGFS HPRT: Low Speed Device Connected.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSDEV, TR_FMT1, + "OTGFS HPRT: Full Speed Device Connected.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_LSFSSW, TR_FMT1, + "OTGFS HPRT: Host Switch: LS -> FS.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_HPRT_FSLSSW, TR_FMT1, + "OTGFS HPRT: Host Switch: FS -> LS.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_DISC, TR_FMT1, + "OTGFS Handle the disconnect detected interrupt.\n"), + TRENTRY(OTGFS_VTRACE1_GINT_IPXFR, TR_FMT1, + "OTGFS Handle the incomplete periodic transfer.\n"), #endif }; static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = { - TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, "OTGFS CLIP: chidx: %d buflen: %d\n"), + TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, + "OTGFS CLIP: chidx: %d buflen: %d\n"), #ifdef HAVE_USBHOST_TRACE_VERBOSE - TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, TR_FMT2, "OTGFS EP%d(IN) wake up with result: %d\n"), - TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2, "OTGFS EP%d(OUT) wake up with result: %d\n"), - TRENTRY(OTGFS_VTRACE2_CTRLIN, TR_FMT2, "OTGFS CTRL_IN type: %02x req: %02x\n"), - TRENTRY(OTGFS_VTRACE2_CTRLOUT, TR_FMT2, "OTGFS CTRL_OUT type: %02x req: %02x\n"), - TRENTRY(OTGFS_VTRACE2_INTRIN, TR_FMT2, "OTGFS INTR_IN chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_INTROUT, TR_FMT2, "OTGFS INTR_OUT chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_BULKIN, TR_FMT2, "OTGFS BULK_IN chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_BULKOUT, TR_FMT2, "OTGFS BULK_OUT chidx: %02x len: %02x\n"), - TRENTRY(OTGFS_VTRACE2_ISOCIN, TR_FMT2, "OTGFS ISOC_IN chidx: %02x len: %04d\n"), - TRENTRY(OTGFS_VTRACE2_ISOCOUT, TR_FMT2, "OTGFS ISOC_OUT chidx: %02x req: %02x\n"), - TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, TR_FMT2, "OTGFS Transfer chidx: %d buflen: %d\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), - TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2, "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), - TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2, "OTGFS Channel halted. chidx: %d, reason: %d\n"), + TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_IN, TR_FMT2, + "OTGFS EP%d(IN) wake up with result: %d\n"), + TRENTRY(OTGFS_VTRACE2_CHANWAKEUP_OUT, TR_FMT2, + "OTGFS EP%d(OUT) wake up with result: %d\n"), + TRENTRY(OTGFS_VTRACE2_CTRLIN, TR_FMT2, + "OTGFS CTRL_IN type: %02x req: %02x\n"), + TRENTRY(OTGFS_VTRACE2_CTRLOUT, TR_FMT2, + "OTGFS CTRL_OUT type: %02x req: %02x\n"), + TRENTRY(OTGFS_VTRACE2_INTRIN, TR_FMT2, + "OTGFS INTR_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_INTROUT, TR_FMT2, + "OTGFS INTR_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_BULKIN, TR_FMT2, + "OTGFS BULK_IN chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_BULKOUT, TR_FMT2, + "OTGFS BULK_OUT chidx: %02x len: %02x\n"), + TRENTRY(OTGFS_VTRACE2_ISOCIN, TR_FMT2, + "OTGFS ISOC_IN chidx: %02x len: %04d\n"), + TRENTRY(OTGFS_VTRACE2_ISOCOUT, TR_FMT2, + "OTGFS ISOC_OUT chidx: %02x req: %02x\n"), + TRENTRY(OTGFS_VTRACE2_STARTTRANSFER, TR_FMT2, + "OTGFS Transfer chidx: %d buflen: %d\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_IN, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,CTRL)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_CTRL_OUT, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,CTRL)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_IN, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,INTR)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_INTR_OUT, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,INTR)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_IN, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,BULK)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_BULK_OUT, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,BULK)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_IN, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,IN ,ISOC)\n"), + TRENTRY(OTGFS_VTRACE2_CHANCONF_ISOC_OUT, TR_FMT2, + "OTGFS Channel configured. chidx: %d: (EP%d,OUT,ISOC)\n"), + TRENTRY(OTGFS_VTRACE2_CHANHALT, TR_FMT2, + "OTGFS Channel halted. chidx: %d, reason: %d\n"), #endif }; diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.h b/arch/arm/src/stm32l4/stm32l4_userspace.h index 250c15b9ac..db190ed56e 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.h +++ b/arch/arm/src/stm32l4/stm32l4_userspace.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32l4/stm32l4_userspace.h * * Copyright (C) 2017 Gregory Nutt. All rights reserved. @@ -31,20 +31,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H #define __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Name: stm32l4_userspace diff --git a/arch/arm/src/stm32l4/stm32l4_waste.h b/arch/arm/src/stm32l4/stm32l4_waste.h index e14459c045..4b00bf08aa 100644 --- a/arch/arm/src/stm32l4/stm32l4_waste.h +++ b/arch/arm/src/stm32l4/stm32l4_waste.h @@ -54,7 +54,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /** Waste CPU Time diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h index c78f337b53..f20897eec2 100644 --- a/arch/arm/src/stm32l4/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/stm32l4_wdg.h @@ -63,7 +63,7 @@ extern "C" #endif /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** @@ -92,8 +92,8 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq); * Name: stm32l4_wwdginitialize * * Description: - * Initialize the WWDG watchdog time. The watchdog timer is initialized and - * registers as 'devpath. The initial state of the watchdog time is + * Initialize the WWDG watchdog time. The watchdog timer is initialized + * and registers as 'devpath. The initial state of the watchdog time is * disabled. * * Input Parameters: diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index d1127a39fe..479270f22c 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -206,7 +206,7 @@ static inline void rcc_enableahb2(void) #if STM32L4_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -/* These chips have no GPIOF, GPIOG or GPIOI */ + /* These chips have no GPIOF, GPIOG or GPIOI */ #if STM32L4_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif @@ -404,7 +404,7 @@ static inline void rcc_enableapb1(void) putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ - /* Second APB1 register */ + /* Second APB1 register */ regval = getreg32(STM32L4_RCC_APB1ENR2); @@ -454,8 +454,8 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32L4_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) - /* System configuration controller, comparators, and voltage reference buffer - * clock enable + /* System configuration controller, comparators, and voltage reference + * buffer clock enable */ regval |= RCC_APB2ENR_SYSCFGEN; @@ -647,7 +647,8 @@ static void stm32l4_stdclockconfig(void) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) + if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -764,8 +765,9 @@ static void stm32l4_stdclockconfig(void) /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | + STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | + STM32L4_PLLCFG_PLLR); #ifdef STM32L4_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; @@ -833,7 +835,7 @@ static void stm32l4_stdclockconfig(void) regval |= RCC_CR_PLLSAI1ON; putreg32(regval, STM32L4_RCC_CR); - /* Wait until the PLL is ready */ + /* Wait until the PLL is ready */ while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { @@ -875,7 +877,8 @@ static void stm32l4_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); + regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | + FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif @@ -890,7 +893,8 @@ static void stm32l4_stdclockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { } @@ -911,6 +915,7 @@ static void stm32l4_stdclockconfig(void) /* ensure Power control is enabled since it is indirectly required * to alter the LSE parameters. */ + stm32l4_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 5bbaf153a4..0353cc1f98 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -253,7 +253,6 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FSMCEN; #endif - #ifdef CONFIG_STM32L4_QSPI /* QuadSPI module clock enable */ @@ -403,7 +402,7 @@ static inline void rcc_enableapb1(void) putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ - /* Second APB1 register */ + /* Second APB1 register */ regval = getreg32(STM32L4_RCC_APB1ENR2); @@ -447,8 +446,8 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32L4_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) - /* System configuration controller, comparators, and voltage reference buffer - * clock enable + /* System configuration controller, comparators, and voltage reference + * buffer clock enable */ regval |= RCC_APB2ENR_SYSCFGEN; @@ -638,7 +637,8 @@ static void stm32l4_stdclockconfig(void) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) + if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -755,8 +755,9 @@ static void stm32l4_stdclockconfig(void) /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | + STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | + STM32L4_PLLCFG_PLLR); #ifdef STM32L4_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; @@ -824,7 +825,7 @@ static void stm32l4_stdclockconfig(void) regval |= RCC_CR_PLLSAI1ON; putreg32(regval, STM32L4_RCC_CR); - /* Wait until the PLL is ready */ + /* Wait until the PLL is ready */ while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { @@ -866,7 +867,8 @@ static void stm32l4_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); + regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | + FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif @@ -881,7 +883,8 @@ static void stm32l4_stdclockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { } @@ -902,6 +905,7 @@ static void stm32l4_stdclockconfig(void) /* ensure Power control is enabled since it is indirectly required * to alter the LSE parameters. */ + stm32l4_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 8b6823d9b5..db4b3c2c26 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -289,7 +289,6 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FSMCEN; #endif - #ifdef CONFIG_STM32L4_QSPI /* QuadSPI module clock enable */ @@ -460,7 +459,7 @@ static inline void rcc_enableapb1(void) putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ - /* Second APB1 register */ + /* Second APB1 register */ regval = getreg32(STM32L4_RCC_APB1ENR2); @@ -510,8 +509,8 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32L4_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) - /* System configuration controller, comparators, and voltage reference buffer - * clock enable + /* System configuration controller, comparators, and voltage reference + * buffer clock enable */ regval |= RCC_APB2ENR_SYSCFGEN; @@ -715,7 +714,8 @@ static void stm32l4_stdclockconfig(void) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) + if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -832,8 +832,9 @@ static void stm32l4_stdclockconfig(void) /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | + STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | + STM32L4_PLLCFG_PLLR); #ifdef STM32L4_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; @@ -901,7 +902,7 @@ static void stm32l4_stdclockconfig(void) regval |= RCC_CR_PLLSAI1ON; putreg32(regval, STM32L4_RCC_CR); - /* Wait until the PLL is ready */ + /* Wait until the PLL is ready */ while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { @@ -943,7 +944,8 @@ static void stm32l4_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache, data cache, and 4 wait states */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); + regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | + FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif @@ -958,7 +960,8 @@ static void stm32l4_stdclockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { } @@ -987,6 +990,7 @@ static void stm32l4_stdclockconfig(void) /* ensure Power control is enabled since it is indirectly required * to alter the LSE parameters. */ + stm32l4_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 5cd1daa867..c943ba12ce 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -178,7 +178,8 @@ struct stm32l4_dma_ops_s /* Dump the DMA registers */ CODE void (*dma_dump)(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, const char *msg); + const struct stm32l4_dmaregs_s *regs, + const char *msg); #endif }; @@ -219,7 +220,8 @@ static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, const struct stm32l4_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, uint8_t controller); +static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, + uint8_t controller); static void stm32l4_gdma_limits_get(uint8_t controller, FAR uint8_t *first, FAR uint8_t *last); @@ -234,37 +236,41 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = #ifdef CONFIG_STM32L4_DMA1 /* 0 - DMA1 */ - { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + { + .dma_disable = stm32l4_dma12_disable, + .dma_interrupt = stm32l4_dma12_interrupt, + .dma_setup = stm32l4_dma12_setup, + .dma_start = stm32l4_dma12_start, + .dma_residual = stm32l4_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32l4_dma12_sample, + .dma_dump = stm32l4_dma12_dump, #endif - }, + }, #else - { NULL }, + { + NULL + }, #endif #ifdef CONFIG_STM32L4_DMA2 /* 1 - DMA2 */ - { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + { + .dma_disable = stm32l4_dma12_disable, + .dma_interrupt = stm32l4_dma12_interrupt, + .dma_setup = stm32l4_dma12_setup, + .dma_start = stm32l4_dma12_start, + .dma_residual = stm32l4_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32l4_dma12_sample, + .dma_dump = stm32l4_dma12_dump, #endif - } + } #else - { NULL } + { + NULL + } #endif }; @@ -272,11 +278,11 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = { - { - .id = 1, - .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32L4_DMAMUX1_BASE - } + { + .id = 1, + .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ + .base = STM32L4_DMAMUX1_BASE + } }; /* This array describes the state of each controller */ @@ -285,23 +291,23 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ - { - .base = STM32L4_DMA1_BASE, - .first = DMA1_FIRST, - .nchan = DMA1_NCHAN, - .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ - .dmamux_offset = 0 - }, + { + .base = STM32L4_DMA1_BASE, + .first = DMA1_FIRST, + .nchan = DMA1_NCHAN, + .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ + .dmamux_offset = 0 + }, /* 1 - DMA2 */ - { - .base = STM32L4_DMA2_BASE, - .first = DMA2_FIRST, - .nchan = DMA2_NCHAN, - .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ - .dmamux_offset = 7 - } + { + .base = STM32L4_DMA2_BASE, + .first = DMA2_FIRST, + .nchan = DMA2_NCHAN, + .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ + .dmamux_offset = 7 + } }; /* This array describes the state of each DMA channel. */ @@ -311,110 +317,121 @@ static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = #ifdef CONFIG_STM32L4_DMA1 /* DMA1 */ - { - .ctrl = DMA1, - .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, - .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), - }, - { - .ctrl = DMA1, - .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, - .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), - }, - { - .ctrl = DMA1, - .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, - .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), - }, - { - .ctrl = DMA1, - .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, - .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), - }, - { - .ctrl = DMA1, - .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, - .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), - }, - { - .ctrl = DMA1, - .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, - .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), - }, - { - .ctrl = DMA1, - .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, - .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), - }, + { + .ctrl = DMA1, + .chan = 0, + .irq = STM32L4_IRQ_DMA1CH1, + .shift = DMA_CHAN_SHIFT(0), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + }, + + { + .ctrl = DMA1, + .chan = 1, + .irq = STM32L4_IRQ_DMA1CH2, + .shift = DMA_CHAN_SHIFT(1), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + }, + + { + .ctrl = DMA1, + .chan = 2, + .irq = STM32L4_IRQ_DMA1CH3, + .shift = DMA_CHAN_SHIFT(2), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + }, + + { + .ctrl = DMA1, + .chan = 3, + .irq = STM32L4_IRQ_DMA1CH4, + .shift = DMA_CHAN_SHIFT(3), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + }, + + { + .ctrl = DMA1, + .chan = 4, + .irq = STM32L4_IRQ_DMA1CH5, + .shift = DMA_CHAN_SHIFT(4), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + }, + + { + .ctrl = DMA1, + .chan = 5, + .irq = STM32L4_IRQ_DMA1CH6, + .shift = DMA_CHAN_SHIFT(5), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + }, + + { + .ctrl = DMA1, + .chan = 6, + .irq = STM32L4_IRQ_DMA1CH7, + .shift = DMA_CHAN_SHIFT(6), + .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + }, #endif #ifdef CONFIG_STM32L4_DMA2 /* DMA2 */ + { + .ctrl = DMA2, + .chan = 0, + .irq = STM32L4_IRQ_DMA2CH1, + .shift = DMA_CHAN_SHIFT(0), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + }, - { - .ctrl = DMA2, - .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, - .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), - }, - { - .ctrl = DMA2, - .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, - .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), - }, - { - .ctrl = DMA2, - .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, - .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), - }, - { - .ctrl = DMA2, - .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, - .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), - }, - { - .ctrl = DMA2, - .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, - .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), - }, - { - .ctrl = DMA2, - .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, - .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), - }, - { - .ctrl = DMA2, - .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, - .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), - }, + { + .ctrl = DMA2, + .chan = 1, + .irq = STM32L4_IRQ_DMA2CH2, + .shift = DMA_CHAN_SHIFT(1), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + }, + + { + .ctrl = DMA2, + .chan = 2, + .irq = STM32L4_IRQ_DMA2CH3, + .shift = DMA_CHAN_SHIFT(2), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + }, + + { + .ctrl = DMA2, + .chan = 3, + .irq = STM32L4_IRQ_DMA2CH4, + .shift = DMA_CHAN_SHIFT(3), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + }, + + { + .ctrl = DMA2, + .chan = 4, + .irq = STM32L4_IRQ_DMA2CH5, + .shift = DMA_CHAN_SHIFT(4), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + }, + + { + .ctrl = DMA2, + .chan = 5, + .irq = STM32L4_IRQ_DMA2CH6, + .shift = DMA_CHAN_SHIFT(5), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + }, + + { + .ctrl = DMA2, + .chan = 6, + .irq = STM32L4_IRQ_DMA2CH7, + .shift = DMA_CHAN_SHIFT(6), + .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + }, #endif }; @@ -441,7 +458,7 @@ static uint32_t dmachan_getbase(DMA_CHANNEL dmachan) return g_dma[controller].base; } -/********************************************************************** +/**************************************************************************** * Name: dmabase_getreg * * Description: @@ -464,7 +481,8 @@ static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset) * ****************************************************************************/ -static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, uint32_t value) +static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value) { uint32_t dmabase = dmachan_getbase(dmachan); @@ -492,7 +510,8 @@ static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset) * ****************************************************************************/ -static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, uint32_t value) +static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, + uint32_t value) { putreg32(value, dmachan->base + offset); } @@ -534,7 +553,8 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, uint8_t controller) +static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, + uint8_t controller) { uint8_t first = 0; uint8_t nchan = 0; @@ -621,7 +641,9 @@ static int stm32l4_dma12_interrupt(int irq, void *context, FAR void *arg) /* Get the channel and the controller that generated the interrupt */ - if (0) {} + if (0) + { + } #ifdef CONFIG_STM32L4_DMA1 else if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) { @@ -680,7 +702,8 @@ static int stm32l4_dma12_interrupt(int irq, void *context, FAR void *arg) ****************************************************************************/ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, - uint32_t maddr, size_t ntransfers, uint32_t ccr) + uint32_t maddr, size_t ntransfers, + uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint32_t regval; @@ -725,18 +748,18 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, dmachan_putreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx - * register. Configure data transfer direction, circular mode, peripheral & - * memory incremented mode, peripheral & memory data size, and interrupt + * register. Configure data transfer direction, circular mode, peripheral + * & memory incremented mode, peripheral & memory data size, and interrupt * after half and/or full transfer in the DMA_CCRx register. */ regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | - DMA_CCR_DIR); + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | - DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | - DMA_CCR_DIR); + DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | + DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); } @@ -776,11 +799,12 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, if ((ccr & DMA_CCR_CIRC) == 0) { - /* Once half of the bytes are transferred, the half-transfer flag (HTIF) - * is set and an interrupt is generated if the Half-Transfer Interrupt - * Enable bit (HTIE) is set. At the end of the transfer, the Transfer - * Complete Flag (TCIF) is set and an interrupt is generated if the - * Transfer Complete Interrupt Enable bit (TCIE) is set. + /* Once half of the bytes are transferred, the half-transfer flag + * (HTIF) is set and an interrupt is generated if the Half-Transfer + * Interrupt Enable bit (HTIE) is set. At the end of the transfer, + * the Transfer Complete Flag (TCIF) is set and an interrupt is + * generated if the Transfer Complete Interrupt Enable bit (TCIE) + * is set. */ ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : @@ -791,8 +815,9 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, /* In nonstop mode, when the transfer completes it immediately resets * and starts again. The transfer-complete interrupt is thus always * enabled, and the half-complete interrupt can be used in circular - * mode to determine when the buffer is half-full, or in double-buffered - * mode to determine when one of the two buffers is full. + * mode to determine when the buffer is half-full, or in + * double-buffered mode to determine when one of the two buffers + * is full. */ ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; @@ -855,16 +880,23 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, uint32_t dmabase = dmachan_getbase(dmachan); - dmainfo("DMA%d Registers: %s\n", dmachan->ctrl + 1, msg); - dmainfo(" ISR[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, + dmainfo("DMA%d Registers: %s\n", + dmachan->ctrl + 1, + msg); + dmainfo(" ISR[%08x]: %08x\n", + dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); - dmainfo(" CCR[%08x]: %08x\n", dmachan->base + STM32L4_DMACHAN_CCR_OFFSET, + dmainfo(" CCR[%08x]: %08x\n", + dmachan->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); - dmainfo(" CNDTR[%08x]: %08x\n", dmachan->base + STM32L4_DMACHAN_CNDTR_OFFSET, + dmainfo(" CNDTR[%08x]: %08x\n", + dmachan->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); - dmainfo(" CPAR[%08x]: %08x\n", dmachan->base + STM32L4_DMACHAN_CPAR_OFFSET, + dmainfo(" CPAR[%08x]: %08x\n", + dmachan->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); - dmainfo(" CMAR[%08x]: %08x\n", dmachan->base + STM32L4_DMACHAN_CMAR_OFFSET, + dmainfo(" CMAR[%08x]: %08x\n", + dmachan->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -903,7 +935,8 @@ static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", - dmamux->base + STM32L4_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); + dmamux->base + STM32L4_DMAMUX_CXCR_OFFSET(channel), + regs->dmamux.ccr); dmainfo(" CSR[%08x]: %08x\n", dmamux->base + STM32L4_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08x]: %08x\n", @@ -1035,6 +1068,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) break; } } + leave_critical_section(flags); dmainfo("ctrl=%d item=%d\n", controller, item); @@ -1184,8 +1218,8 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, * * Description: * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() can - * be called again + * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * can be called again * * Assumptions: * - DMA handle allocated by stm32l4_dmachannel() @@ -1325,11 +1359,13 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) case STM32L4_SRAM2_BASE: case STM32L4_SRAM3_BASE: case STM32L4_CODE_BASE: + /* All RAM and flash is supported */ return true; default: + /* Everything else is unsupported by DMA */ return false; diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 7d36d12f75..71caf84e47 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -453,7 +453,7 @@ static inline void rcc_enableapb1(void) putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ - /* Second APB1 register */ + /* Second APB1 register */ regval = getreg32(STM32L4_RCC_APB1ENR2); @@ -497,8 +497,8 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32L4_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) - /* System configuration controller, comparators, and voltage reference buffer - * clock enable + /* System configuration controller, comparators, and voltage reference + * buffer clock enable */ regval |= RCC_APB2ENR_SYSCFGEN; @@ -700,7 +700,9 @@ static void stm32l4_stdclockconfig(void) for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) + regval = getreg32(STM32L4_RCC_CR); + + if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -821,8 +823,9 @@ static void stm32l4_stdclockconfig(void) /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | + STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | + STM32L4_PLLCFG_PLLR); #ifdef STM32L4_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; @@ -890,7 +893,7 @@ static void stm32l4_stdclockconfig(void) regval |= RCC_CR_PLLSAI1ON; putreg32(regval, STM32L4_RCC_CR); - /* Wait until the PLL is ready */ + /* Wait until the PLL is ready */ while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { @@ -955,7 +958,8 @@ static void stm32l4_stdclockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { }