Finish TIM header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3042 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -109,60 +109,127 @@
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/* Register Bit-Field Definitions ***************************************************/
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/* Timer Input Capture/Output Compare Select */
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#define TIM_TIOS_
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/* Timer Compare Force Register */
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#define TIM_CFORC_
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/* Output Compare 7 Mask Register */
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#define TIM_OC7M_
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/* Output Compare 7 Data Register */
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#define TIM_OC7D_
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/* Timer Count Register */
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#define TIM_TCNTHI2_
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/* Timer Count Register */
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#define TIM_TCNTLO2_
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/* Timer System Control Register 1 */
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#define TIM_TSCR1_
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/* Timer Toggle Overflow Register */
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#define TIM_TTOV_
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/* Timer Control Register1 */
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#define TIM_TCTL1_
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/* Timer Control Register3 */
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#define TIM_TCTL3_
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/* Timer Interrupt Enable Register */
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#define TIM_TIE_
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/* Timer System Control Register 2 */
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#define TIM_TSCR2_
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/* Main Timer Interrupt Flag 1 */
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#define TIM_TFLG1_
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/* Main Timer Interrupt Flag 2 */
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#define TIM_TFLG2_
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/* Timer Input Capture/Output Compare Register 4 */
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#define TIM_TC4HI_
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/* Timer Input Capture/Output Compare Register 4 */
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#define TIM_TC4LO_
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/* Timer Input Capture/Output Compare Register 5 */
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#define TIM_TC5HI_
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/* Timer Input Capture/Output Compare Register 5 */
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#define TIM_TC5LO_
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/* Timer Input Capture/Output Compare Register 6 */
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#define TIM_TC6HI_
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/* Timer Input Capture/Output Compare Register 6 */
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#define TIM_TC6LO_
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/* Timer Input Capture/Output Compare Register 7 */
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#define TIM_TC7HI_
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/* Timer Input Capture/Output Compare Register 7 */
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#define TIM_TC7LO_
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/* 16-Bit Pulse Accumulator Control Register */
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#define TIM_PACTL_
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/* Pulse Accumulator Flag Register */
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#define TIM_PAFLG_
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/* Pulse Accumulator Count Register */
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#define TIM_PACNTHI_
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/* Pulse Accumulator Count Register */
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#define TIM_PACNTLO_
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/* Timer Test Register */
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#define TIM_TIMTST2_
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/* Timer Input Capture/Output Compare Select Bit-Field Definitions */
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#define TIM_TIOS(n) (1 << (n)) /* 0:Input capture, 1:Output compare */
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/* Timer Compare Force Register Bit-Field Definitions */
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#define TIM_CFORC(n) (1 << (n)) /* Force Output Compare Action */
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/* Output Compare 7 Mask Register Bit-Field Definitions */
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#define TIM_OC7M(n) (1 << (n)) /* Output Compare 7 Mask */
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/* Output Compare 7 Data Register Bit-Field Definitions */
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#define TIM_OC7D(n) (1 << (n)) /* Output Compare 7 Data */
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/* Timer Count HI/LO Register Bit-Field Definitions */
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/* These two registers form a 16-bit timer up counter and have no internal bit-fields */
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/* Timer System Control Register 1 Bit-Field Definitions */
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#define TIM_TSCR1_TFFCA (1 << 4) /* Timer Fast Flag Clear All */
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#define TIM_TSCR1_TSFRA (1 << 5) /* Timer Stops While in Freeze Mode */
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#define TIM_TSCR1_TSWAI (1 << 6) /* Timer Module Stops While in Wait */
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#define TIM_TSCR1_TEN (1 << 7) /* Timer Enable */
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/* Timer Toggle Overflow Register Bit-Field Definitions */
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#define TIM_TTOV(n) (1 << (n)) /* Toggle On Overflow Bits
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/* Timer Control Register1 Bit-Field Definitions */
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#define TIM_TCTL1_SHIFT(n) (((n)-4) << 1)
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#define TIM_TCTL1_MASK (n) (3 << TIM_TCTL1_SHIFT(n))
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# define TIM_TCTL1_OL(n) (1 << TIM_TCTL1_SHIFT(n)) /* Output Level */
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# define TIM_TCTL1_OM(n) (2 << TIM_TCTL1_SHIFT(n)) /* Output Mode */
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# define TIM_TCTL1_DISABLED(n) (0 << TIM_TCTL1_SHIFT(n)) /* Timer disconnected from output pin logic */
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# define TIM_TCTL1_TOGGLE(n) (1 << TIM_TCTL1_SHIFT(n)) /* Toggle OCx output line */
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# define TIM_TCTL1_CLEAR(n) (2 << TIM_TCTL1_SHIFT(n)) /* Clear OCx output line to zero */
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# define TIM_TCTL1_SET(n) (3 << TIM_TCTL1_SHIFT(n)) /* Set OCx output line to one */
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/* Timer Control Register3 Bit-Field Definitions */
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#define TIM_TCTL3_EDG_SHIFT(n) (((n)-4) << 1) /* Input Capture Edge Control */
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#define TIM_TCTL3_EDG_MASK (n) (3 << TIM_TCTL3_EDG_SHIFT(n))
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# define TIM_TCTL3_EDGA(n) (1 << TIM_TCTL3_EDG_SHIFT(n))
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# define TIM_TCTL3_EDGB(n) (2 << TIM_TCTL3_EDG_SHIFT(n))
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# define TIM_TCTL3_DISABLED(n) (0 << TIM_TCTL3_EDG_SHIFT(n)) /* Capture disabled */
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# define TIM_TCTL3_RISING(n) (1 << TIM_TCTL3_EDG_SHIFT(n)) /* Capture on rising edges only */
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# define TIM_TCTL3_FALLING(n) (2 << TIM_TCTL3_EDG_SHIFT(n)) /* Capture on falling edges only */
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# define TIM_TCTL3_BOTH(n) (3 << TIM_TCTL3_EDG_SHIFT(n)) /* Capture on any edge */
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/* Timer Interrupt Enable Register Bit-Field Definitions */
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#define TIM_TIE(n) (1 << (n)) /* Input Capture/Output Compare n Interrupt Enable */
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/* Timer System Control Register 2 Bit-Field Definitions */
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#define TIM_TSCR2_PR_SHIFT (0) /* Timer Prescaler Select */
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#define TIM_TSCR2_PR_MASK (7 << TIM_TSCR2_PR_SHIFT)
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# define TIM_TSCR2_PR0 (1 << TIM_TSCR2_PR_SHIFT)
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# define TIM_TSCR2_PR1 (2 << TIM_TSCR2_PR_SHIFT)
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# define TIM_TSCR2_PR2 (4 << TIM_TSCR2_PR_SHIFT)
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# define TIM_TSCR2_PR_DIV1 (0 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/1 */
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# define TIM_TSCR2_PR_DIV2 (1 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/2 */
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# define TIM_TSCR2_PR_DIV4 (2 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/4 */
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# define TIM_TSCR2_PR_DIV8 (3 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/8 */
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# define TIM_TSCR2_PR_DIV16 (4 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/16 */
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# define TIM_TSCR2_PR_DIV32 (5 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/32 */
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# define TIM_TSCR2_PR_DIV64 (6 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/64 */
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# define TIM_TSCR2_PR_DIV128 (7 << TIM_TSCR2_PR_SHIFT) /* Bus Clock/128 */
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#define TIM_TSCR2_TCRE (1 << 3) /* Timer Counter Reset Enable */
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#define TIM_TSCR2_TOI (1 << 7) /* Timer Overflow Interrupt Enable */
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/* Main Timer Interrupt Flag 1 Bit-Field Definitions */
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#define TIM_TFLG1(n) (1 << (n)) /* Input Capture/Output Compare Channel n Flag */
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/* Main Timer Interrupt Flag 2 Bit-Field Definitions */
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#define TIM_TFLG2_TOF (1 << 7) /* Timer Overflow Flag */
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/* Timer Input Capture/Output Compare HI/LO Register 4-7 Bit-Field Definitions */
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/* These register pairs form a 16-bit timer compare values and have no internal bit-fields */
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/* 16-Bit Pulse Accumulator Control Register Bit-Field Definitions */
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#define TIM_PACTL_PAI (1 << 0) /* Pulse Accumulator Input Interrupt Enable*/
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#define TIM_PACTL_PAOVI (1 << 1) /* Pulse Accumulator Overflow Interrupt Enable */
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#define TIM_PACTL_CLK_SHIFT (2) /* Clock Select Bits */
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#define TIM_PACTL_CLK_MASK (3 << TIM_PACTL_CLK_SHIFT)
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# define TIM_PACTL_CLK0 (1 << TIM_PACTL_CLK_SHIFT)
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# define TIM_PACTL_CLK1 (1 << TIM_PACTL_CLK_SHIFT)
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# define TIM_PACTL_PRESCAL (0 << TIM_PACTL_CLK_SHIFT) /* Use timer prescaler clock as timer counter clock */
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# define TIM_PACTL_PACLK (1 << TIM_PACTL_CLK_SHIFT) /* Use PACLK as input to timer counter clock */
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# define TIM_PACTL_DIV256 (2 << TIM_PACTL_CLK_SHIFT) /* Use PACLK/256 as timer counter clock frequency */
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# define TIM_PACTL_DIV64K (3 << TIM_PACTL_CLK_SHIFT) /* Use PACLK/65536 as timer counter clock frequency */
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#define TIM_PACTL_PIN_SHIFT (4) /* Pin action */
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#define TIM_PACTL_PIN_MASK (3 << TIM_PACTL_PIN_SHIFT)
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# define TIM_PACTL_PEDGE (1 << TIM_PACTL_PIN_SHIFT) /* Pulse Accumulator Edge Control */
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# define TIM_PACTL_PAMOD (2 << TIM_PACTL_PIN_SHIFT) /* Pulse Accumulator Mode */
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# define TIM_PACTL_FALLING (0 << TIM_PACTL_PIN_SHIFT) /* Falling edge */
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# define TIM_PACTL_RISING (1 << TIM_PACTL_PIN_SHIFT) /* Rising edge */
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# define TIM_PACTL_DIV64HI (2 << TIM_PACTL_PIN_SHIFT) /* Div. by 64 clock enabled with pin high level */
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# define TIM_PACTL_DIV64LO (3 << TIM_PACTL_PIN_SHIFT) /* Div. by 64 clock enabled with pin low level */
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#define TIM_PACTL_PAEN (1 << 6) /* Pulse Accumulator System Enable */
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/* Pulse Accumulator Flag Register Bit-Field Definitions */
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#define TIM_PAFLG_PAIF (1 << 0) /* Pulse Accumulator Input edge Flag */
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#define TIM_PAFLG_PAOVF (1 << 1) /* Pulse Accumulator Overflow Flag */
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/* Pulse Accumulator Count HI/LO Register Bit-Field Definitions */
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/* This register pair forms a 16-bit pulse accumulator value with no internal bit-fields */
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/* Timer Test Register Bit-Field Definitions */
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/* Not documented */
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/************************************************************************************
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* Public Types
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