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Add Ethernet pin/clock configuration logic

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4148 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-12-08 22:14:48 +00:00
parent d25ac40a99
commit de65832c7c
4 changed files with 70 additions and 3 deletions
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5
configs/stm3240g-eval/README.txt
View File

@ -374,6 +374,11 @@ STM3240G-EVAL-specific Configuration Options
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
4-bit transfer mode.
CONFIG_STM32_MII - Support Ethernet MII interface
CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
CONFIG_STM32_RMII - Support Ethernet RMII interface
STM3240G-EVAL LCD Hardware Configuration
Configurations

36
configs/stm3240g-eval/include/board.h
View File

@ -207,6 +207,42 @@
#define GPIO_USART3_RX GPIO_USART3_RX_2
#define GPIO_USART3_TX GPIO_USART3_TX_2
/* Ethernet:
*
* - PA2 is ETH_MDIO
* - PC1 is ETH_MDC
* - PB5 is ETH_PPS_OUT
* - PH2 is ETH_MII_CRS
* - PH3 is ETH_MII_COL
* - PI10 is ETH_MII_RX_ER
* - PH6 is ETH_MII_RXD2
* - PH7 is ETH_MII_RXD3
* - PC3 is ETH_MII_TX_CLK
* - PC2 is ETH_MII_TXD2
* - PB8 is ETH_MII_TXD3
* - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK
* - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV
* - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0
* - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1
* - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN
* - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0
* - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1
*/
#define GPIO_ETH_PPS_OUT GPIO_ETH_PPS_OUT_1
#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_2
#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_2
#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_2
#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_2
#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_2
#define GPIO_ETH_MII_TXD3 GPIO_ETH_MII_TXD3_1
#define GPIO_ETH_MII_TX_EN GPIO_ETH_MII_TX_EN_2
#define GPIO_ETH_MII_TXD0 GPIO_ETH_MII_TXD0_2
#define GPIO_ETH_MII_TXD1 GPIO_ETH_MII_TXD1_2
#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
/************************************************************************************
* Public Data
************************************************************************************/

17
configs/stm3240g-eval/nsh/defconfig
View File

@ -182,7 +182,7 @@ CONFIG_STM32_TIM11=n
#CONFIG_STM32_FORCEPOWER=y
#
# STM3240xxx specific serial device driver settings
# STM32F40xxx specific serial device driver settings
#
# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the
# console and ttys0 (default is the USART1).
@ -238,7 +238,7 @@ CONFIG_USART4_2STOP=0
CONFIG_USART5_2STOP=0
#
# STM32F103Z specific SSI device driver settings
# STM32F40xxx specific SSI device driver settings
#
# CONFIG_SSIn_DISABLE - select to disable all support for
# the SSI
@ -255,6 +255,19 @@ CONFIG_SSI1_DISABLE=y
CONFIG_SSI_POLLWAIT=y
#CONFIG_SSI_TXLIMIT=4
#
# STM32F40xxx Ethernet device driver settings
#
# CONFIG_STM32_MII - Support Ethernet MII interface
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
# CONFIG_STM32_RMII - Support Ethernet RMII interface
#
CONFIG_STM32_MII=y
CONFIG_STM32_MII_MCO1=y
CONFIG_STM32_MII_MCO2=n
CONFIG_STM32_RMII=n
#
# General build options
#

15
configs/stm3240g-eval/ostest/defconfig
View File

@ -238,7 +238,7 @@ CONFIG_USART4_2STOP=0
CONFIG_USART5_2STOP=0
#
# STM32F103Z specific SSI device driver settings
# STM32F40xxx specific SSI device driver settings
#
# CONFIG_SSIn_DISABLE - select to disable all support for
# the SSI
@ -255,6 +255,19 @@ CONFIG_SSI1_DISABLE=y
CONFIG_SSI_POLLWAIT=y
#CONFIG_SSI_TXLIMIT=4
#
# STM32F40xxx Ethernet device driver settings
#
# CONFIG_STM32_MII - Support Ethernet MII interface
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
# CONFIG_STM32_RMII - Support Ethernet RMII interface
#
CONFIG_STM32_MII=y
CONFIG_STM32_MII_MCO1=y
CONFIG_STM32_MII_MCO2=n
CONFIG_STM32_RMII=n
#
# General build options
#