Add more EMAC register definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1440 42af7a65-404d-4744-a932-0658087f49c3
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@ -62,65 +62,94 @@
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/* EMACC Registers *****************************************************************/
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#define EZ80_EMAC_TEST 0x20
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#define EZ80_EMAC_CFG1 0x21
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#define EZ80_EMAC_CFG2 0x22
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#define EZ80_EMAC_CFG3 0x23
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#define EZ80_EMAC_CFG4 0x24
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#define EZ80_EMAC_STAD_0 0x25
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#define EZ80_EMAC_STAD_1 0x26
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#define EZ80_EMAC_STAD_2 0x27
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#define EZ80_EMAC_STAD_3 0x28
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#define EZ80_EMAC_STAD_4 0x29
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#define EZ80_EMAC_STAD_5 0x2a
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#define EZ80_EMAC_TPTV_L 0x2b
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#define EZ80_EMAC_TPTV_H 0x2c
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#define EZ80_EMAC_IPGT 0x2d
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#define EZ80_EMAC_IPGR1 0x2e
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#define EZ80_EMAC_IPGR2 0x2f
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#define EZ80_EMAC_MAXF_L 0x30
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#define EZ80_EMAC_MAXF_H 0x31
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#define EZ80_EMAC_AFR 0x32
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#define EZ80_EMAC_HTBL_0 0x33
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#define EZ80_EMAC_HTBL_1 0x34
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#define EZ80_EMAC_HTBL_2 0x35
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#define EZ80_EMAC_HTBL_3 0x36
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#define EZ80_EMAC_HTBL_4 0x37
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#define EZ80_EMAC_HTBL_5 0x38
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#define EZ80_EMAC_HTBL_6 0x39
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#define EZ80_EMAC_HTBL_7 0x3a
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#define EZ80_EMAC_MIIMGT 0x3b
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#define EZ80_EMAC_CTLD_L 0x3c
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#define EZ80_EMAC_CTLD_H 0x3d
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#define EZ80_EMAC_RGAD 0x3e
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#define EZ80_EMAC_FIAD 0x3f
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#define EZ80_EMAC_PTMR 0x40
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#define EZ80_EMAC_RST 0x41
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#define EZ80_EMAC_TLBP_L 0x42
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#define EZ80_EMAC_TLBP_H 0x43
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#define EZ80_EMAC_BP_L 0x44
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#define EZ80_EMAC_BP_H 0x45
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#define EZ80_EMAC_BP_U 0x46
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#define EZ80_EMAC_RHBP_L 0x47
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#define EZ80_EMAC_RHBP_H 0x48
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#define EZ80_EMAC_RRP_L 0x49
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#define EZ80_EMAC_RRP_H 0x4a
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#define EZ80_EMAC_BUFSZ 0x4b
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#define EZ80_EMAC_IEN 0x4c
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#define EZ80_EMAC_ISTAT 0x4d
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#define EZ80_EMAC_PRSD_L 0x4e
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#define EZ80_EMAC_PRSD_H 0x4f
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#define EZ80_EMAC_MIISTAT 0x50
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#define EZ80_EMAC_RWP_L 0x51
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#define EZ80_EMAC_RWP_H 0x52
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#define EZ80_EMAC_TRP_L 0x53
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#define EZ80_EMAC_TRP_H 0x54
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#define EZ80_EMAC_BLKSLFT_L 0x55
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#define EZ80_EMAC_BLKSLFT_H 0x56
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#define EZ80_EMAC_FDATA_L 0x57
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#define EZ80_EMAC_FDATA_H 0x58
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#define EZ80_EMAC_FFLAGS 0x59
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#define EZ80_EMAC_FLAGS 0x59
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#define EZ80_EMAC_TEST 0x20 /* EMAC test register */
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#define EZ80_EMAC_CFG1 0x21 /* EMAC configuration 1 register */
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#define EZ80_EMAC_CFG2 0x22 /* EMAC configuration 2 register */
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#define EZ80_EMAC_CFG3 0x23 /* EMAC configuration 3 register */
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#define EZ80_EMAC_CFG4 0x24 /* EMAC configuration 4 register */
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#define EZ80_EMAC_STAD_0 0x25 /* EMAC station address register 0 */
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#define EZ80_EMAC_STAD_1 0x26 /* EMAC station address register 1 */
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#define EZ80_EMAC_STAD_2 0x27 /* EMAC station address register 2 */
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#define EZ80_EMAC_STAD_3 0x28 /* EMAC station address register 3 */
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#define EZ80_EMAC_STAD_4 0x29 /* EMAC station address register 4 */
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#define EZ80_EMAC_STAD_5 0x2a /* EMAC station address register 5 */
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#define EZ80_EMAC_TPTV_L 0x2b /* Transit pause timer value (low) */
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#define EZ80_EMAC_TPTV_H 0x2c /* Transit pause timer value (high) */
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#define EZ80_EMAC_IPGT 0x2d /* EMAC Interpacket gap register */
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#define EZ80_EMAC_IPGR1 0x2e /* Non-back-to-back IPG register 1 */
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#define EZ80_EMAC_IPGR2 0x2f /* Non-back-to-back IPG register 2 */
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#define EZ80_EMAC_MAXF_L 0x30 /* EMAC maximum frame length register (low) */
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#define EZ80_EMAC_MAXF_H 0x31 /* EMAC maximum frame length register (high) */
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#define EZ80_EMAC_AFR 0x32 /* EMAC address filter register */
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#define EZ80_EMAC_HTBL_0 0x33 /* EMAC hash table register 0 */
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#define EZ80_EMAC_HTBL_1 0x34 /* EMAC hash table register 1 */
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#define EZ80_EMAC_HTBL_2 0x35 /* EMAC hash table register 2 */
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#define EZ80_EMAC_HTBL_3 0x36 /* EMAC hash table register 3 */
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#define EZ80_EMAC_HTBL_4 0x37 /* EMAC hash table register 4 */
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#define EZ80_EMAC_HTBL_5 0x38 /* EMAC hash table register 5 */
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#define EZ80_EMAC_HTBL_6 0x39 /* EMAC hash table register 6 */
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#define EZ80_EMAC_HTBL_7 0x3a /* EMAC hash table register 7 */
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#define EZ80_EMAC_MIIMGT 0x3b /* EMACS MII management register */
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#define EZ80_EMAC_CTLD_L 0x3c /* PHY configuration data register (low) */
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#define EZ80_EMAC_CTLD_H 0x3d /* PHY configuration data register (high) */
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#define EZ80_EMAC_RGAD 0x3e /* PHY address register */
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#define EZ80_EMAC_FIAD 0x3f /* PHY unit select register */
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#define EZ80_EMAC_PTMR 0x40 /* EMAC transmit polling timer register */
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#define EZ80_EMAC_RST 0x41 /* EMAC reset control register */
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#define EZ80_EMAC_TLBP_L 0x42 /* EMAC tranmit lower boundary pointer (low) */
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#define EZ80_EMAC_TLBP_H 0x43 /* EMAC tranmit lower boundary pointer (high) */
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#define EZ80_EMAC_BP_L 0x44 /* EMAC boundary pointer register (low) */
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#define EZ80_EMAC_BP_H 0x45 /* EMAC boundary pointer register (high) */
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#define EZ80_EMAC_BP_U 0x46 /* EMAC boundary pointer register (upper byte) */
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#define EZ80_EMAC_RHBP_L 0x47 /* EMAC receive high boundary pointer register (low) */
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#define EZ80_EMAC_RHBP_H 0x48 /* EMAC receive high boundary pointer register (high) */
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#define EZ80_EMAC_RRP_L 0x49 /* EMAC receive read pointer (low) */
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#define EZ80_EMAC_RRP_H 0x4a /* EMAC receive read pointer (high) */
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#define EZ80_EMAC_BUFSZ 0x4b /* EMAC buffer size register */
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#define EZ80_EMAC_IEN 0x4c /* EMAC interrupt enable register */
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#define EZ80_EMAC_ISTAT 0x4d /* EMAC interrupt status register */
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#define EZ80_EMAC_PRSD_L 0x4e /* PHY read status data register (low) */
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#define EZ80_EMAC_PRSD_H 0x4f /* PHY read status data register (high) */
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#define EZ80_EMAC_MIISTAT 0x50 /* EMAC MII status register */
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#define EZ80_EMAC_RWP_L 0x51 /* EMAC receive write pointer (low) */
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#define EZ80_EMAC_RWP_H 0x52 /* EMAC receive write pointer (high) */
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#define EZ80_EMAC_TRP_L 0x53 /* EMAC transmit read pointer (low) */
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#define EZ80_EMAC_TRP_H 0x54 /* EMAC transmit read pointer (high) */
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#define EZ80_EMAC_BLKSLFT_L 0x55 /* EMAC receive blocks left register (low) */
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#define EZ80_EMAC_BLKSLFT_H 0x56 /* EMAC receive blocks left register (high) */
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#define EZ80_EMAC_FDATA_L 0x57 /* EMAC FIFO data register (low) */
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#define EZ80_EMAC_FDATA_H 0x58 /* EMAC FIFO data register (low) */
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#define EZ80_EMAC_FFLAGS 0x59 /* EMAC FIFO flags register */
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/* EMAC configuration 1/2/3 registers ***********************************************/
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#define EMAC_CFG1_DCRCC 0x01 /* Bit 0: 1=4 bytes of proprietary header */
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#define EMAC_CFG1_HUGEN 0x02 /* Bit 1: 1=Allow unlimited size frames to be recieved */
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#define EMAC_CFG1_FLCHK 0x04 /* Bit 2: 1=Frame lengths compared to length/type */
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#define EMAC_CFG1_FULLHD 0x08 /* Bit 3: 1=Enable full duplex mode */
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#define EMAC_CFG1_CRCEN 0x10 /* Bit 4: 1=Append CRC to every frame */
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#define EMAC_CFG1_VLPAD 0x20 /* Bit 5: 1=Pad all short frames to 64 bytes, append CRC */
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#define EMAC_CFG1_ADPADN 0x40 /* Bit 6: 1=Enable frame detection by check VALN protocol ID */
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#define EMAC_CFG1_PADEN 0x80 /* Bit 7: 1=Padd all short frames with zeros. */
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#define EMAC_CFG2_LCOLMASK 0x3f /* Bits 0-5: Number bytes after start frame for collision */
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#define EMAC_CFG2_NOBO 0x40 /* Bit 6: 1=immediate transmit after collision */
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#define EMAC_CFG2_BPNB 0x80 /* Bit 7: 1=after collision retransmit without back-off */
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#define EMAC_CFG3_RETRYMASK 0x0f /* Bits 0-3: Number retransmissions before abort */
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#define EMAC_CFG3_BITMD 0x10 /* Bit 4: 1=Enable 10Mbps ENDEC mode */
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#define EMAC_CFG3_XSDFR 0x20 /* Bit 5: 1=Defer to carrier indefinitely */
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#define EMAC_CFG3_PUREP 0x40 /* Bit 6: 1=Verify preamble */
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#define EMAC_CFG3_LONGP 0x80 /* Bit 7: 1=only allow preamble < 12 bytes */
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#define EMAC_CFG4_RXEN 0x01 /* Bit 0: 1=Receive frames */
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#define EMAC_CFG4_TPAUSE 0x02 /* Bit 1: 1=Force pause condition */
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#define EMAC_CFG4_TXFC 0x04 /* Bit 2: 1=Transmit pause control frames */
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#define EMAC_CFG4_RXFC 0x08 /* Bit 3: 1=Act on receive pause control frames */
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#define EMAC_CFG4_PARF 0x10 /* Bit 4: 1=Receive all frames */
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#define EMAC_CFG4_THDF 0x20 /* Bit 5: 1=Asser back-pressure */
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#define EMAC_CFG4_TPCF 0x40 /* Bit 6: 1=Transmit pause control frame. */
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/* Bit 7: reserved */
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/* PLL Registers *******************************************************************/
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