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arch/arm/src/s32k1xx/s32k1xx_clockconfig.c and related files: Fix confusion about who decrements the rster value. Some dividers may have a function range of 1..8 but the register value is 0..7. There were several places where values were getting decremented twice: Once by higher up logic and once by the register access logic. A such dividers were reviewed and, hopefully, all were fixed.

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This commit is contained in:
Gregory Nutt 2019-08-19 13:07:45 -06:00
parent 425a2d1b2c
commit df1294906d
5 changed files with 61 additions and 94 deletions
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2
arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h
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@ -112,7 +112,7 @@
# define SIM_CHIPCTL_CLKOUTSEL_QSPI_2xSFIF_CLK (15 << SIM_CHIPCTL_CLKOUTSEL_SHIFT) /* S32K148) */
#define SIM_CHIPCTL_CLKOUTDIV_SHIFT (8) /* Bits 8-10: CLKOUT Divide Ratio */
#define SIM_CHIPCTL_CLKOUTDIV_MASK (7 << SIM_CHIPCTL_CLKOUTDIV_SHIFT)
# define SIM_CHIPCTL_CLKOUTDIV(n) ((uint32_t)(n) << SIM_CHIPCTL_CLKOUTDIV_SHIFT) /* n=1..8 */
# define SIM_CHIPCTL_CLKOUTDIV(n) ((uint32_t)((n) - 1) << SIM_CHIPCTL_CLKOUTDIV_SHIFT) /* n=1..8 */
#define SIM_CHIPCTL_CLKOUTEN (1 << 11) /* Bit 11: CLKOUT enable */
#define SIM_CHIPCTL_TRACECLK_SEL (1 << 12) /* Bit 12: Debug trace clock select */
#define SIM_CHIPCTL_PDB_BB_SEL (1 << 13) /* Bit 13: PDB back-to-back select */

33
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
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@ -137,28 +137,27 @@ enum scg_system_clock_mode_e
* Private Data
****************************************************************************/
static const enum scg_system_clock_div_e
g_tmp_sysclk[TMP_SYS_CLK_NO][TMP_SYS_DIV_NO] =
static const uint8_t g_tmp_sysclk[TMP_SYS_CLK_NO][TMP_SYS_DIV_NO] =
{
{
SCG_SYSTEM_CLOCK_DIV_BY_1, /* SIRC SYS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_1, /* SIRC BUS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_2 /* SIRC SLOW_CLK divider */
1, /* SIRC SYS_CLK divider, range 1..16 */
1, /* SIRC BUS_CLK divider, range 1..16 */
2 /* SIRC SLOW_CLK divider, range 1..16 */
},
{
SCG_SYSTEM_CLOCK_DIV_BY_1, /* FIRC SYS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_2, /* FIRC BUS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_4 /* FIRC SLOW_CLK divider */
1, /* FIRC SYS_CLK divider, range 1..16 */
2, /* FIRC BUS_CLK divider, range 1..16 */
4 /* FIRC SLOW_CLK divider, range 1..16 */
},
{
SCG_SYSTEM_CLOCK_DIV_BY_1, /* SOSC SYS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_2, /* SOSC BUS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_2 /* SOSC SLOW_CLK divider */
1, /* SOSC SYS_CLK divider, range 1..16 */
2, /* SOSC BUS_CLK divider, range 1..16 */
2 /* SOSC SLOW_CLK divider, range 1..16 */
},
{
SCG_SYSTEM_CLOCK_DIV_BY_3, /* SPLL SYS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_2, /* SPLL BUS_CLK divider */
SCG_SYSTEM_CLOCK_DIV_BY_2 /* SPLL SLOW_CLK divider */
3, /* SPLL SYS_CLK divider, range 1..16 */
2, /* SPLL BUS_CLK divider, range 1..16 */
2 /* SPLL SLOW_CLK divider, range 1..16 */
}
};
@ -482,9 +481,9 @@ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src)
static int s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
const struct scg_system_clock_config_s *config)
{
uint32_t srcfreq = 0;
uint32_t sysfreq_mul = ((uint32_t)config->divcore) + 1;
uint32_t busfreq_mul = (((uint32_t)config->divcore) + 1) * (((uint32_t)config->divbus) + 1);
uint32_t srcfreq = 0;
uint32_t sysfreq_mul = ((uint32_t)config->divcore) + 1;
uint32_t busfreq_mul = (((uint32_t)config->divcore) + 1) * (((uint32_t)config->divbus) + 1);
uint32_t slowfreq_mul = (((uint32_t)config->divcore) + 1) * (((uint32_t)config->divslow) + 1);
uint32_t regval;
int ret = OK;

76
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
View File

@ -90,17 +90,17 @@
enum scg_system_clock_type_e
{
SCG_SYSTEM_CLOCK_CORE, /* Core clock */
SCG_SYSTEM_CLOCK_BUS, /* BUS clock */
SCG_SYSTEM_CLOCK_SLOW, /* System slow clock */
SCG_SYSTEM_CLOCK_MAX /* Max value */
SCG_SYSTEM_CLOCK_CORE, /* Core clock */
SCG_SYSTEM_CLOCK_BUS, /* BUS clock */
SCG_SYSTEM_CLOCK_SLOW, /* System slow clock */
SCG_SYSTEM_CLOCK_MAX /* Max value */
};
enum scg_async_clock_type_e
{
SCG_ASYNC_CLOCK_DIV1 = 0, /* Clock divider 1 */
SCG_ASYNC_CLOCK_DIV2 = 1, /* Clock divider 2 */
SCG_ASYNC_CLOCK_MAX = 2, /* Max value */
SCG_ASYNC_CLOCK_DIV1 = 0, /* Clock divider 1 */
SCG_ASYNC_CLOCK_DIV2 = 1, /* Clock divider 2 */
SCG_ASYNC_CLOCK_MAX = 2, /* Max value */
};
/* These structure are used to define the clock configuration. */
@ -109,19 +109,19 @@ enum scg_async_clock_type_e
enum scg_sirc_range_e
{
SCG_SIRC_RANGE_HIGH = 1, /* Slow IRC high range clock (8 MHz). */
SCG_SIRC_RANGE_HIGH = 1, /* Slow IRC high range clock (8 MHz). */
};
enum scg_async_clock_div_e
{
SCG_ASYNC_CLOCK_DISABLE = 0, /* Clock output is disabled */
SCG_ASYNC_CLOCK_DIV_BY_1 = 1, /* Divided by 1 */
SCG_ASYNC_CLOCK_DIV_BY_2 = 2, /* Divided by 2 */
SCG_ASYNC_CLOCK_DIV_BY_4 = 3, /* Divided by 4 */
SCG_ASYNC_CLOCK_DIV_BY_8 = 4, /* Divided by 8 */
SCG_ASYNC_CLOCK_DIV_BY_16 = 5, /* Divided by 16 */
SCG_ASYNC_CLOCK_DIV_BY_32 = 6, /* Divided by 32 */
SCG_ASYNC_CLOCK_DIV_BY_64 = 7 /* Divided by 64 */
SCG_ASYNC_CLOCK_DISABLE = 0, /* Clock output is disabled */
SCG_ASYNC_CLOCK_DIV_BY_1 = 1, /* Divided by 1 */
SCG_ASYNC_CLOCK_DIV_BY_2 = 2, /* Divided by 2 */
SCG_ASYNC_CLOCK_DIV_BY_4 = 3, /* Divided by 4 */
SCG_ASYNC_CLOCK_DIV_BY_8 = 4, /* Divided by 8 */
SCG_ASYNC_CLOCK_DIV_BY_16 = 5, /* Divided by 16 */
SCG_ASYNC_CLOCK_DIV_BY_32 = 6, /* Divided by 32 */
SCG_ASYNC_CLOCK_DIV_BY_64 = 7 /* Divided by 64 */
};
struct scg_sirc_config_s
@ -247,26 +247,6 @@ struct scg_clockout_config_s
/* SCG Clock Mode Configuration */
enum scg_system_clock_div_e
{
SCG_SYSTEM_CLOCK_DIV_BY_1 = 0, /* Divided by 1 */
SCG_SYSTEM_CLOCK_DIV_BY_2 = 1, /* Divided by 2 */
SCG_SYSTEM_CLOCK_DIV_BY_3 = 2, /* Divided by 3 */
SCG_SYSTEM_CLOCK_DIV_BY_4 = 3, /* Divided by 4 */
SCG_SYSTEM_CLOCK_DIV_BY_5 = 4, /* Divided by 5 */
SCG_SYSTEM_CLOCK_DIV_BY_6 = 5, /* Divided by 6 */
SCG_SYSTEM_CLOCK_DIV_BY_7 = 6, /* Divided by 7 */
SCG_SYSTEM_CLOCK_DIV_BY_8 = 7, /* Divided by 8 */
SCG_SYSTEM_CLOCK_DIV_BY_9 = 8, /* Divided by 9 */
SCG_SYSTEM_CLOCK_DIV_BY_10 = 9, /* Divided by 10 */
SCG_SYSTEM_CLOCK_DIV_BY_11 = 10, /* Divided by 11 */
SCG_SYSTEM_CLOCK_DIV_BY_12 = 11, /* Divided by 12 */
SCG_SYSTEM_CLOCK_DIV_BY_13 = 12, /* Divided by 13 */
SCG_SYSTEM_CLOCK_DIV_BY_14 = 13, /* Divided by 14 */
SCG_SYSTEM_CLOCK_DIV_BY_15 = 14, /* Divided by 15 */
SCG_SYSTEM_CLOCK_DIV_BY_16 = 15, /* Divided by 16 */
};
enum scg_system_clock_src_e
{
SCG_SYSTEM_CLOCK_SRC_SYS_OSC = 1, /* System OSC */
@ -280,10 +260,10 @@ enum scg_system_clock_src_e
struct scg_system_clock_config_s
{
enum scg_system_clock_div_e divslow; /* Slow clock divider */
enum scg_system_clock_div_e divbus; /* BUS clock divider */
enum scg_system_clock_div_e divcore; /* Core clock divider */
enum scg_system_clock_src_e src; /* System clock source */
uint8_t divslow; /* Slow clock divider, range=1..16 */
uint8_t divbus; /* BUS clock divider, range=1..16 */
uint8_t divcore; /* Core clock divider, range=1..16 */
};
struct scg_clock_mode_config_s
@ -334,22 +314,10 @@ enum sim_clkout_src_e
#endif
};
enum sim_clkout_div_e
{
SIM_CLKOUT_DIV_BY_1 = 0, /* Divided by 1 */
SIM_CLKOUT_DIV_BY_2 = 1, /* Divided by 2 */
SIM_CLKOUT_DIV_BY_3 = 2, /* Divided by 3 */
SIM_CLKOUT_DIV_BY_4 = 3, /* Divided by 4 */
SIM_CLKOUT_DIV_BY_5 = 4, /* Divided by 5 */
SIM_CLKOUT_DIV_BY_6 = 5, /* Divided by 6 */
SIM_CLKOUT_DIV_BY_7 = 6, /* Divided by 7 */
SIM_CLKOUT_DIV_BY_8 = 7, /* Divided by 8 */
};
struct sim_clock_out_config_e
struct sim_clock_out_config_s
{
enum sim_clkout_src_e source; /* SIM ClockOut source select */
enum sim_clkout_div_e divider; /* SIM ClockOut divide ratio */
uint8_t divider; /* SIM ClockOut divide ratio, range 1..8 */
bool initialize; /* true: Initialize the ClockOut clock */
bool enable; /* true: Enable the ClockOut clock */
};
@ -430,7 +398,7 @@ struct sim_qspi_ref_clk_gating_s
struct sim_clock_config_s
{
struct sim_clock_out_config_e clockout; /* Clock Out configuration */
struct sim_clock_out_config_s clockout; /* Clock Out configuration */
struct sim_lpo_clock_config_s lpoclk; /* Low Power Clock configuration */
struct sim_tclk_config_s tclk; /* Platform Gate Clock configuration */
struct sim_plat_gate_config_s platgate; /* Platform Gate Clock configuration */

18
boards/arm/s32k1xx/s32k118evb/src/s32k118_clockconfig.c
View File

@ -126,17 +126,17 @@ const struct clock_configuration_s g_initial_clkconfig =
{
.rccr = /* RCCR - Run Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
.divslow = 2, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
},
.vccr = /* VCCR - VLPR Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_4, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 1, /* DIVBUS, range 1..16 */
.divcore = 2 /* DIVCORE, range 1..16 */
},
/* .altclk */
.initialize = true, /* Initialize */
@ -147,7 +147,7 @@ const struct clock_configuration_s g_initial_clkconfig =
.clockout = /* Clock Out configuration. */
{
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
.divider = SIM_CLKOUT_DIV_BY_1, /* CLKOUTDIV */
.divider = 1, /* CLKOUTDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = false, /* CLKOUTEN */
},

26
boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c
View File

@ -138,24 +138,24 @@ const struct clock_configuration_s g_initial_clkconfig =
{
.rccr = /* RCCR - Run Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
.divslow = 2, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
},
.vccr = /* VCCR - VLPR Clock Control Register */
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_4, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 1, /* DIVBUS, range 1..16 */
.divcore = 2 /* DIVCORE, range 1..16 */
},
.hccr =
{
.divslow = SCG_SYSTEM_CLOCK_DIV_BY_4, /* DIVSLOW */
.divbus = SCG_SYSTEM_CLOCK_DIV_BY_2, /* DIVBUS */
.divcore = SCG_SYSTEM_CLOCK_DIV_BY_1, /* DIVCORE */
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL /* SCS */
.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
},
/* .altclk */
.initialize = true, /* Initialize */
@ -166,7 +166,7 @@ const struct clock_configuration_s g_initial_clkconfig =
.clockout = /* Clock Out configuration. */
{
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
.divider = SIM_CLKOUT_DIV_BY_1, /* CLKOUTDIV */
.divider = 1, /* CLKOUTDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = false, /* CLKOUTEN */
},