From df2241f816446ad27f003ecc156cef7a8488cbb0 Mon Sep 17 00:00:00 2001 From: Dave Marples Date: Thu, 6 Dec 2018 07:20:21 -0600 Subject: [PATCH] This commit changes the lazy and non-lazy exception handler to remove a couple of cpsid instructions from them on ARMv7-m. If my understanding is correct then these interrupt manipulations aren't doing anything anyway because prioritization stops secondary interrupts arriving and, even if they did work, they would have introduced race conditions for the period of time between the interrupt arriving and further interrupts being disabled. --- arch/arm/src/armv7-m/gnu/up_exception.S | 26 --------------------- arch/arm/src/armv7-m/gnu/up_lazyexception.S | 26 --------------------- 2 files changed, 52 deletions(-) diff --git a/arch/arm/src/armv7-m/gnu/up_exception.S b/arch/arm/src/armv7-m/gnu/up_exception.S index 0eddc05449..aeb8ac4cd6 100644 --- a/arch/arm/src/armv7-m/gnu/up_exception.S +++ b/arch/arm/src/armv7-m/gnu/up_exception.S @@ -179,28 +179,6 @@ exception_common: stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP/PRIMASK values */ -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT - /* Disable interrupts, select the stack to use for interrupt handling - * and call up_doirq to handle the interrupt - */ - - cpsid i /* Disable further interrupts */ - -#else - /* Set the BASEPRI register so that further normal interrupts will be - * masked. Nested, high priority may still occur, however. - * - * REVISIT: I think this is un-necessary: "When the processor is - * executing an exception handler, an exception can preempt the exception - * handler if its priority is higher than the priority of the exception - * being handled. See Interrupt priority grouping for more information - * about preemption by an interrupt." - */ - - mov r2, #NVIC_SYSH_DISABLE_PRIORITY - msr basepri, r2 /* Set the BASEPRI */ -#endif - /* There are two arguments to up_doirq: * * R0 = The IRQ number @@ -319,10 +297,6 @@ exception_common: #ifdef CONFIG_ARMV7M_USEBASEPRI msr basepri, r3 /* Restore interrupts priority masking */ -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT - cpsie i /* Re-enable interrupts */ -#endif - #else msr primask, r3 /* Restore interrupts */ #endif diff --git a/arch/arm/src/armv7-m/gnu/up_lazyexception.S b/arch/arm/src/armv7-m/gnu/up_lazyexception.S index a8334ab281..cf15e66a52 100644 --- a/arch/arm/src/armv7-m/gnu/up_lazyexception.S +++ b/arch/arm/src/armv7-m/gnu/up_lazyexception.S @@ -189,28 +189,6 @@ exception_common: stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */ #endif -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT - /* Disable interrupts, select the stack to use for interrupt handling - * and call up_doirq to handle the interrupt - */ - - cpsid i /* Disable further interrupts */ - -#else - /* Set the BASEPRI register so that further normal interrupts will be - * masked. Nested, high priority may still occur, however. - * - * REVISIT: I think this is un-necessary: "When the processor is - * executing an exception handler, an exception can preempt the exception - * handler if its priority is higher than the priority of the exception - * being handled. See Interrupt priority grouping for more information - * about preemption by an interrupt." - */ - - mov r2, #NVIC_SYSH_DISABLE_PRIORITY - msr basepri, r2 /* Set the BASEPRI */ -#endif - /* There are two arguments to up_doirq: * * R0 = The IRQ number @@ -354,10 +332,6 @@ exception_common: #ifdef CONFIG_ARMV7M_USEBASEPRI msr basepri, r3 /* Restore interrupts priority masking */ -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT - cpsie i /* Re-enable interrupts */ -#endif - #else msr primask, r3 /* Restore interrupts */ #endif