From df3404da093a09d1f1164c9727cacf27c285da1e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 10 Dec 2017 17:20:16 -0600 Subject: [PATCH] arch/arm/src/lpc54xx: Various fixes for initial build of SDRAM support. Still unverified (but at least appears to be nonfatal). --- arch/arm/src/lpc54xx/lpc54_emc.c | 6 +-- arch/arm/src/lpc54xx/lpc54_emc.h | 4 +- configs/lpcxpresso-lpc54628/README.txt | 9 ++-- configs/lpcxpresso-lpc54628/src/lpc54_sdram.c | 50 +++++++++---------- 4 files changed, 35 insertions(+), 34 deletions(-) diff --git a/arch/arm/src/lpc54xx/lpc54_emc.c b/arch/arm/src/lpc54xx/lpc54_emc.c index 2b85d19a0c..fdc81328cb 100644 --- a/arch/arm/src/lpc54xx/lpc54_emc.c +++ b/arch/arm/src/lpc54xx/lpc54_emc.c @@ -282,11 +282,11 @@ void lpc54_emc_initialize(FAR const struct emc_config_s *config) ****************************************************************************/ #ifdef CONFIG_LPC54_EMC_DYNAMIC -void lpc54_emc_sdram_initialize(FAR struct emc_dynamic_timing_config_s *timing, - FAR struct emc_dynamic_chip_config_s *chconfig, +void lpc54_emc_sdram_initialize(FAR const struct emc_dynamic_timing_config_s *timing, + FAR const struct emc_dynamic_chip_config_s *chconfig, unsigned int nchips) { - FAR struct emc_dynamic_chip_config_s *config; + FAR const struct emc_dynamic_chip_config_s *config; uintptr_t addr; uint32_t regval; uint32_t offset; diff --git a/arch/arm/src/lpc54xx/lpc54_emc.h b/arch/arm/src/lpc54xx/lpc54_emc.h index cd17ac0b61..54a26139df 100644 --- a/arch/arm/src/lpc54xx/lpc54_emc.h +++ b/arch/arm/src/lpc54xx/lpc54_emc.h @@ -221,8 +221,8 @@ void lpc54_emc_initialize(FAR const struct emc_config_s *config); ****************************************************************************/ #ifdef CONFIG_LPC54_EMC_DYNAMIC -void lpc54_emc_sdram_initialize(FAR struct emc_dynamic_timing_config_s *timing, - FAR struct emc_dynamic_chip_config_s *chconfig, +void lpc54_emc_sdram_initialize(FAR const struct emc_dynamic_timing_config_s *timing, + FAR const struct emc_dynamic_chip_config_s *chconfig, unsigned int nchips); #endif /* CONFIG_LPC54_EMC_DYNAMIC */ diff --git a/configs/lpcxpresso-lpc54628/README.txt b/configs/lpcxpresso-lpc54628/README.txt index 6caaabc673..dbcd51f0a8 100644 --- a/configs/lpcxpresso-lpc54628/README.txt +++ b/configs/lpcxpresso-lpc54628/README.txt @@ -29,7 +29,7 @@ STATUS 2017-12-10: The basic NSH configuration is functional at 220MHz with a Serial console, timer and LED support. Added support for the external - SDRAM and for the RAM test utility. + SDRAM and for the RAM test utility -- UNTESTED! Configurations ============== @@ -92,9 +92,10 @@ Configurations nsh: - Configures the NuttShell (nsh) located at examples/nsh. This - configuration is focused on low level, command-line driver testing. It - has no network. + Configures the NuttShell (nsh) application located at examples/nsh. + This configuration was used to bring up the board support and, hence, + is focused on low level, command-line driver testing. It has no + network. NOTES: diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c b/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c index c00c144dc1..c2eac60800 100644 --- a/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c +++ b/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c @@ -39,7 +39,7 @@ #include -#include "lpc54_emc.h.h" +#include "lpc54_emc.h" #include "lpcxpresso-lpc54628.h" #include @@ -61,11 +61,11 @@ static const struct emc_config_s g_emc_config = { .bigendian = false, /* Little endian */ - .clksrc = EMC_INTLOOPBACK; /* Internal loop back from EMC_CLK output */ + .clksrc = EMC_INTLOOPBACK, /* Internal loop back from EMC_CLK output */ #ifdef BOARD_220MHz - .clkdiv = 3; /* EMC Clock = CPU FREQ/3 */ + .clkdiv = 3, /* EMC Clock = CPU FREQ/3 */ #else /* if BOARD_180MHz */ - .clkdiv = 2; /* EMC Clock = CPU FREQ/2 */ + .clkdiv = 2, /* EMC Clock = CPU FREQ/2 */ #endif }; @@ -73,31 +73,31 @@ static const struct emc_config_s g_emc_config = static const struct emc_dynamic_timing_config_s g_emc_dynconfig = { - .rdconfig = EMC_CMDDELAY; - .refresh = (64 * 1000000 / 4096) /* 4096 rows/ 64ms */; - .rp = 18; - .ras = 42; - .srex = 67; - .apr = 18; - .wr = EMC_CLOCK_PERIOD_NS + 6; /* one clk + 6ns */ - .dal = EMC_CLOCK_PERIOD_NS + 24; - .rc = 60; - .rfc = 60; - .xsr = 67; - .rrd = 23; - .mrd = 2; + .rdconfig = EMC_CMDDELAY, + .refresh = (64 * 1000000 / 4096), /* 4096 rows/ 64ms */ + .rp = 18, + .ras = 42, + .srex = 67, + .apr = 18, + .wr = EMC_CLOCK_PERIOD_NS + 6, /* one clk + 6ns */ + .dal = EMC_CLOCK_PERIOD_NS + 24, + .rc = 60, + .rfc = 60, + .xsr = 67, + .rrd = 23, + .mrd = 2, }; /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ -static onst struct emc_dynamic_chip_config_s g_emc_dynchipconfig; +static const struct emc_dynamic_chip_config_s g_emc_dynchipconfig = { - .chndx = 0; - .dyndev = EMC_SDRAM; - .rasnclk = 2; - .mode = 0x23; - .extmode = 0; /* LPSDRAM only */ - .addrmap = 0x09; /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ + .chndx = 0, + .dyndev = EMC_SDRAM, + .rasnclk = 2, + .mode = 0x23, + .extmode = 0, /* SDRAM only */ + .addrmap = 0x09, /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ }; /**************************************************************************** @@ -120,7 +120,7 @@ void lpc54_sdram_initialize(void) /* EMC Dynamc memory configuration. */ - lpc54_emc_dram_initialize(&g_emc_dynconfig, &g_emc_dynchipconfig, 1); + lpc54_emc_sdram_initialize(&g_emc_dynconfig, &g_emc_dynchipconfig, 1); } #endif /* CONFIG_LPC54_EMC && CONFIG_LPC54_EMC_DYNAMIC */