diff --git a/arch/arm/src/armv8-m/arm_secure_irq.c b/arch/arm/src/armv8-m/arm_secure_irq.c
index 59913fefd0..dc52a5454c 100644
--- a/arch/arm/src/armv8-m/arm_secure_irq.c
+++ b/arch/arm/src/armv8-m/arm_secure_irq.c
@@ -63,9 +63,8 @@ void up_secure_irq(int irq, bool secure)
         break;
 
       case NVIC_IRQ_DBGMONITOR:
-        regaddr = NVIC_DEMCR;
-        regbit  = NVIC_DEMCR_SDME;
-        secure  = !secure;
+        regaddr = NVIC_DAUTHCTRL;
+        regbit  = NVIC_DAUTHCTRL_SPIDENSEL;
         break;
 
       default:
diff --git a/arch/arm/src/armv8-m/nvic.h b/arch/arm/src/armv8-m/nvic.h
index d6b080946e..f10362e03d 100644
--- a/arch/arm/src/armv8-m/nvic.h
+++ b/arch/arm/src/armv8-m/nvic.h
@@ -823,6 +823,11 @@
 #define NVIC_DSCEMCR_CLR_MON_PEND       (1 << 17) /* Bit 17: Clear monitor pend */
 #define NVIC_DSCEMCR_CLR_MON_REQ        (1 << 19) /* Bit 19: Clear monitor request */
 
+/* Debug Authentication Control Register (DAUTHCTRL) */
+
+#define NVIC_DAUTHCTRL_SPIDENSEL        (1 << 0)  /* Bit 0:  Secure invasive debug enable select */
+#define NVIC_DAUTHCTRL_INTSPIDEN        (1 << 1)  /* Bit 1:  Internal Secure invasive debug enable */
+
 /*  Floating-Point Context Control Register (FPCCR) */
 
 #define NVIC_FPCCR_LSPACT               (1 << 0)  /* Bit 0:  Lazy state preservation active */