arch: risc-v: Introduce RISCV_IPI macro for SMP

Summary:
- This commit introduces RISCV_IPI macro for SMP
- Also, replace RISCV_IRQ_MSOFT with RISCV_IRQ_SOFT
- Remove duplicate irq_attach() from qemu_rv_irq.c

Impact:
- None

Testing:
- Tested with rv-virt:smp64 and maix-bit:smp on QEMU

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>

arch/risc-v/src/common/riscv_cpupause.c

@@ -180,9 +180,9 @@ int riscv_pause_handler(int irq, void *c, void *arg)
 {
   int cpu = up_cpu_index();
 
-  /* Clear machine software interrupt */
+  /* Clear IPI (Inter-Processor-Interrupt) */
 
-  putreg32(0, (uintptr_t)RISCV_CLINT_MSIP + (4 * cpu));
+  putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
 
   /* Check for false alarms.  Such false could occur as a consequence of
    * some deadlock breaking logic that might have already serviced the SG2
@@ -258,7 +258,7 @@ int up_cpu_pause(int cpu)
 
   /* Execute Pause IRQ to CPU(cpu) */
 
-  putreg32(1, (uintptr_t)RISCV_CLINT_MSIP + (4 * cpu));
+  putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu));
 
   /* Wait for the other CPU to unlock g_cpu_paused meaning that
    * it is fully paused and ready for up_cpu_resume();

arch/risc-v/src/common/riscv_cpustart.c

@@ -60,13 +60,13 @@
 
 void riscv_cpu_boot(int cpu)
 {
-  /* Clear machine software interrupt for CPU(cpu) */
+  /* Clear IPI for CPU(cpu) */
 
-  putreg32(0, (uintptr_t)RISCV_CLINT_MSIP + (4 * cpu));
+  putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
 
   /* Enable machine software interrupt for IPI to boot */
 
-  up_enable_irq(RISCV_IRQ_MSOFT);
+  up_enable_irq(RISCV_IRQ_SOFT);
 
   /* Wait interrupt */
 
@@ -89,7 +89,7 @@ void riscv_cpu_boot(int cpu)
 
   /* Clear machine software interrupt for CPU(cpu) */
 
-  putreg32(0, (uintptr_t)RISCV_CLINT_MSIP + (4 * cpu));
+  putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
 
 #ifdef CONFIG_SCHED_INSTRUMENTATION
   /* Notify that this CPU has started */
@@ -143,7 +143,7 @@ int up_cpu_start(int cpu)
 
   /* Send IPI to CPU(cpu) */
 
-  putreg32(1, (uintptr_t)RISCV_CLINT_MSIP + (cpu * 4));
+  putreg32(1, (uintptr_t)RISCV_IPI + (cpu * 4));
 
   return 0;
 }

arch/risc-v/src/common/riscv_exception.c

@@ -32,6 +32,7 @@
 #include <nuttx/arch.h>
 
 #include "riscv_internal.h"
+#include "chip.h"
 
 /****************************************************************************
  * Private Data
@@ -133,7 +134,7 @@ void riscv_exception_attach(void)
   irq_attach(RISCV_IRQ_STOREPF, riscv_exception, NULL);
 
 #ifdef CONFIG_SMP
-  irq_attach(RISCV_IRQ_MSOFT, riscv_pause_handler, NULL);
+  irq_attach(RISCV_IRQ_SOFT, riscv_pause_handler, NULL);
 #else
   irq_attach(RISCV_IRQ_MSOFT, riscv_exception, NULL);
 #endif

arch/risc-v/src/k210/hardware/k210_clint.h

@@ -31,4 +31,6 @@
 
 #define RISCV_CLINT_MSIP     K210_CLINT_MSIP
 
+#define RISCV_IPI            RISCV_CLINT_MSIP
+
 #endif /* __ARCH_RISCV_SRC_K210_HARDWARE_K210_CLINT_H */

arch/risc-v/src/k210/k210_irq.c

@@ -85,11 +85,11 @@ void up_irqinitialize(void)
   riscv_exception_attach();
 
 #ifdef CONFIG_SMP
-  /* Clear MSOFT for CPU0 */
+  /* Clear RISCV_IPI for CPU0 */
 
-  putreg32(0, K210_CLINT_MSIP);
+  putreg32(0, RISCV_IPI);
 
-  up_enable_irq(RISCV_IRQ_MSOFT);
+  up_enable_irq(RISCV_IRQ_SOFT);
 #endif
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS

arch/risc-v/src/qemu-rv/hardware/qemu_rv_clint.h

@@ -31,4 +31,6 @@
 
 #define RISCV_CLINT_MSIP        QEMU_RV_CLINT_MSIP
 
+#define RISCV_IPI               RISCV_CLINT_MSIP
+
 #endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_CLINT_H */

arch/risc-v/src/qemu-rv/qemu_rv_irq.c

@@ -79,14 +79,11 @@ void up_irqinitialize(void)
   riscv_exception_attach();
 
 #ifdef CONFIG_SMP
-  /* Clear MSOFT for CPU0 */
+  /* Clear RISCV_IPI for CPU0 */
 
-  putreg32(0, RISCV_CLINT_MSIP);
+  putreg32(0, RISCV_IPI);
 
-  /* Setup MSOFT for CPU0 with pause handler */
+  up_enable_irq(RISCV_IRQ_SOFT);
-
-  irq_attach(RISCV_IRQ_MSOFT, riscv_pause_handler, NULL);
-  up_enable_irq(RISCV_IRQ_MSOFT);
 #endif
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS