arch/arm/src/stm32f7/stm32_serial.c: Previous logic would invalidate the data cache as each byte was read from the DMA buffer. This change adds logic to invalidate the data cache less frequently by monitoring the state of the Rx DMA buffer cache coherency and invalidating only regions as necessary. This commit also reverts commit e17d8c719e which has a logic error in cases where data is removed from the Rx DMA buffer at a rate higher than it is added to the Rx DMA buffer.
This commit is contained in:
Evgeniy Bobkov
Gregory Nutt
parent
0e7fa2c9b0
commit
df7565e557
@ -294,9 +294,9 @@
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struct up_dev_s
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{
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struct uart_dev_s dev; /* Generic UART device */
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uint16_t ie; /* Saved interrupt mask bits value */
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uint16_t sr; /* Saved status bits */
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struct uart_dev_s dev; /* Generic UART device */
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uint16_t ie; /* Saved interrupt mask bits value */
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uint16_t sr; /* Saved status bits */
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/* Has been initialized and HW is setup. */
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@ -307,39 +307,39 @@ struct up_dev_s
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*/
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#ifdef CONFIG_SERIAL_TERMIOS
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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bool iflow; /* input flow control (RTS) enabled */
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bool iflow; /* input flow control (RTS) enabled */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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bool oflow; /* output flow control (CTS) enabled */
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bool oflow; /* output flow control (CTS) enabled */
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#endif
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uint32_t baud; /* Configured baud */
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uint32_t baud; /* Configured baud */
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#else
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const uint8_t parity; /* 0=none, 1=odd, 2=even */
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const uint8_t bits; /* Number of bits (7 or 8) */
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const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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const uint8_t parity; /* 0=none, 1=odd, 2=even */
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const uint8_t bits; /* Number of bits (7 or 8) */
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const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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const bool iflow; /* input flow control (RTS) enabled */
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const bool iflow; /* input flow control (RTS) enabled */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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const bool oflow; /* output flow control (CTS) enabled */
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const bool oflow; /* output flow control (CTS) enabled */
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#endif
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const uint32_t baud; /* Configured baud */
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const uint32_t baud; /* Configured baud */
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#endif
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const uint8_t irq; /* IRQ associated with this USART */
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const uint32_t apbclock; /* PCLK 1 or 2 frequency */
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const uint32_t usartbase; /* Base address of USART registers */
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const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */
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const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */
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const uint8_t irq; /* IRQ associated with this USART */
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const uint32_t apbclock; /* PCLK 1 or 2 frequency */
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const uint32_t usartbase; /* Base address of USART registers */
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const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */
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const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
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const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
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#endif
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#ifdef CONFIG_SERIAL_OFLOWCONTROL
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const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
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const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
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#endif
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#ifdef SERIAL_HAVE_DMA
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@ -349,15 +349,21 @@ struct up_dev_s
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/* RX DMA state */
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#ifdef SERIAL_HAVE_DMA
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DMA_HANDLE rxdma; /* currently-open receive DMA stream */
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bool rxenable; /* DMA-based reception en/disable */
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uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */
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char *const rxfifo; /* Receive DMA buffer */
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DMA_HANDLE rxdma; /* currently-open receive DMA stream */
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bool rxenable; /* DMA-based reception en/disable */
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uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */
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#ifdef CONFIG_ARMV7M_DCACHE
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uint32_t rxdmaavail; /* Number of bytes available without need to
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* to invalidate the data cache */
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#endif
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char *const rxfifo; /* Receive DMA buffer */
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#endif
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#ifdef HAVE_RS485
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const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
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const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
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const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin
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* configuration */
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const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for
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* TX enabled */
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#endif
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};
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@ -1601,11 +1607,14 @@ static int up_dma_setup(struct uart_dev_s *dev)
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RXDMA_BUFFER_SIZE,
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SERIAL_DMA_CONTROL_WORD);
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/* Reset our DMA shadow pointer to match the address just
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* programmed above.
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/* Reset our DMA shadow pointer and Rx data availability count to match
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* the address just programmed above.
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*/
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priv->rxdmanext = 0;
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#ifdef CONFIG_ARMV7M_DCACHE
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priv->rxdmaavail = 0;
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#endif
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/* Enable receive DMA for the UART */
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@ -2357,13 +2366,57 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
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static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
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{
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struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
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uint32_t nextrx = up_dma_nextrx(priv);
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int c = 0;
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/* Check if additional bytes have been added to the DMA buffer. */
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/* Check if more data is available */
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if (up_dma_nextrx(priv) != priv->rxdmanext)
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if (nextrx != priv->rxdmanext)
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{
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/* Read one byte from the Rx DMA buffer */
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#ifdef CONFIG_ARMV7M_DCACHE
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/* If the data cache is enabled, then we will also need to manage
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* cache coherency. Are any bytes available in the currently coherent
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* region of the data cache?
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*/
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if (priv->rxdmaavail == 0)
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{
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uint32_t rxdmaavail;
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uintptr_t addr;
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/* No.. then we will have to invalidate additional space in the Rx
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* DMA buffer.
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*/
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if (nextrx > priv->rxdmanext)
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{
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/* Number of available bytes */
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rxdmaavail = nextrx - priv->rxdmanext;
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}
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else
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{
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/* Number of available bytes up to the end of RXDMA buffer */
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rxdmaavail = RXDMA_BUFFER_SIZE - priv->rxdmanext;
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}
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/* Invalidate the DMA buffer range */
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addr = (uintptr_t)&priv->rxfifo[priv->rxdmanext];
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arch_invalidate_dcache(addr, addr + rxdmaavail);
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/* We don't need to invalidate the data cache for the next
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* rxdmaavail number of next bytes.
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*/
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priv->rxdmaavail = rxdmaavail;
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}
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priv->rxdmaavail--;
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#endif
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/* Now read from the DMA buffer */
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c = priv->rxfifo[priv->rxdmanext];
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@ -2374,6 +2427,12 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
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}
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}
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/* NOTE: If no data is available, then we would return NULL which is,
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* of course, valid binary data. The protocol is that the upper half
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* driver must call up_dma_rxavailable prior to calling this function to
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* assure that this never happens.
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*/
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return c;
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}
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#endif
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@ -2543,19 +2602,6 @@ static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
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if (priv->rxenable && up_dma_rxavailable(&priv->dev))
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{
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/* Invalidate the entire DMA buffer. It would be tempting to
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* invalidate only half of the DMA buffer, since the DMA completion
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* event means that only half of the DMA buffer has been filled.
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* However, we need to account for the behavior of up_dma_rxavailable()
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* which may encroach into the next half of the DMA buffer while DMA
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* is still in progress in that half.
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*/
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arch_invalidate_dcache((uintptr_t)priv->rxfifo,
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(uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE - 1);
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/* Receive the newly DMA'ed characters */
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uart_recvchars(&priv->dev);
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}
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}
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