From df7bffe8fdc907b427b41c37c62f11382b0bd1f8 Mon Sep 17 00:00:00 2001 From: Alin Jerpelea Date: Wed, 24 Mar 2021 09:14:10 +0100 Subject: [PATCH] arch: arm: armv7-r: fix nxstyle errors Fix nxstyle errors to pass CI Signed-off-by: Alin Jerpelea --- arch/arm/src/armv7-r/arm.h | 8 +- arch/arm/src/armv7-r/arm_dataabort.c | 4 +- arch/arm/src/armv7-r/arm_gicv2.c | 21 +- arch/arm/src/armv7-r/arm_head.S | 4 +- arch/arm/src/armv7-r/arm_l2cc_pl310.c | 35 +-- arch/arm/src/armv7-r/arm_mpu.c | 7 +- arch/arm/src/armv7-r/arm_prefetchabort.c | 4 +- arch/arm/src/armv7-r/arm_restorefpu.S | 20 +- arch/arm/src/armv7-r/arm_savefpu.S | 24 +- arch/arm/src/armv7-r/arm_vectors.S | 56 ++--- arch/arm/src/armv7-r/barriers.h | 12 +- arch/arm/src/armv7-r/cp15.h | 56 ++--- arch/arm/src/armv7-r/cp15_cacheops.h | 201 +++++++++-------- arch/arm/src/armv7-r/gic.h | 269 ++++++++++++----------- arch/arm/src/armv7-r/l2cc_pl310.h | 38 ++-- arch/arm/src/armv7-r/mpcore.h | 16 +- arch/arm/src/armv7-r/mpu.h | 9 +- arch/arm/src/armv7-r/sctlr.h | 179 +++++++++------ arch/arm/src/armv7-r/svcall.h | 28 +-- 19 files changed, 540 insertions(+), 451 deletions(-) diff --git a/arch/arm/src/armv7-r/arm.h b/arch/arm/src/armv7-r/arm.h index f609506305..530dba460c 100644 --- a/arch/arm/src/armv7-r/arm.h +++ b/arch/arm/src/armv7-r/arm.h @@ -20,8 +20,9 @@ /* References: * - * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright - * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414) + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. + * All rights reserved. ARM DDI 0406C.c (ID051414) */ #ifndef __ARCH_ARM_SRC_ARMV7_R_CPSR_H @@ -52,6 +53,7 @@ # define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ # define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ # define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ + #define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ #define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ #define PSR_MASK_MASK (7 << PSR_GE_SHIFT) @@ -116,7 +118,7 @@ extern "C" * memory resources! We need to be very careful in this case. This * function will perform MCU- and board-specific initialization which, * among other things, must initialize memories. After initializatino - ( of the memories, this function will call arm_data_initialize() to + * of the memories, this function will call arm_data_initialize() to * initialize the memory resources * 4. This function will then branch to nx_start() to start the operating * system. diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c index cb9a801274..51e6cbfba0 100644 --- a/arch/arm/src/armv7-r/arm_dataabort.c +++ b/arch/arm/src/armv7-r/arm_dataabort.c @@ -52,8 +52,8 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) { - /* Save the saved processor context in CURRENT_REGS where it can be accessed - * for register dumps and possibly context switching. + /* Save the saved processor context in CURRENT_REGS where it can be + * accessed for register dumps and possibly context switching. */ CURRENT_REGS = regs; diff --git a/arch/arm/src/armv7-r/arm_gicv2.c b/arch/arm/src/armv7-r/arm_gicv2.c index a2ff4d9a66..f12507888a 100644 --- a/arch/arm/src/armv7-r/arm_gicv2.c +++ b/arch/arm/src/armv7-r/arm_gicv2.c @@ -175,11 +175,11 @@ void arm_gic_initialize(void) /* Registers with 8-bits per interrupt */ putreg32(0x80808080, GIC_ICDIPR(0)); /* SGI[3:0] priority */ - putreg32(0x80808080, GIC_ICDIPR(4)); /* SGI[4:7] priority */ - putreg32(0x80808080, GIC_ICDIPR(8)); /* SGI[8:11] priority */ - putreg32(0x80808080, GIC_ICDIPR(12)); /* SGI[12:15] priority */ - putreg32(0x80000000, GIC_ICDIPR(24)); /* PPI[0] priority */ - putreg32(0x80808080, GIC_ICDIPR(28)); /* PPI[1:4] priority */ + putreg32(0x80808080, GIC_ICDIPR(4)); /* SGI[4:7] priority */ + putreg32(0x80808080, GIC_ICDIPR(8)); /* SGI[8:11] priority */ + putreg32(0x80808080, GIC_ICDIPR(12)); /* SGI[12:15] priority */ + putreg32(0x80000000, GIC_ICDIPR(24)); /* PPI[0] priority */ + putreg32(0x80808080, GIC_ICDIPR(28)); /* PPI[1:4] priority */ /* Set the binary point register. * @@ -187,9 +187,10 @@ void arm_gic_initialize(void) * field; the value n (n=0-6) specifies that bits (n+1) through bit 7 are * used in the comparison for interrupt pre-emption. A GIC supports a * minimum of 16 and a maximum of 256 priority levels so not all binary - * point settings may be meaningul. The special value n=7 (GIC_ICCBPR_NOPREMPT) - * disables pre-emption. We disable all pre-emption here to prevent nesting - * of interrupt handling. + * point settings may be meaningul. + * The special value n=7 (GIC_ICCBPR_NOPREMPT) disables pre-emption. + * We disable all pre-emption here to prevent nesting of interrupt + * handling. */ putreg32(GIC_ICCBPR_NOPREMPT, GIC_ICCBPR); @@ -403,8 +404,8 @@ uint32_t *arm_decodeirq(uint32_t *regs) * * This function implements enabling of the device specified by 'irq' * at the interrupt controller level if supported by the architecture - * (up_irq_restore() supports the global level, the device level is hardware - * specific). + * (up_irq_restore() supports the global level, the device level is + * hardware specific). * * Since this API is not supported on all architectures, it should be * avoided in common implementations where possible. diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index f42c77dfe2..a1deebc820 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -33,9 +33,9 @@ #include -/********************************************************************************** +/**************************************************************************** * Configuration - **********************************************************************************/ + ****************************************************************************/ /* Hard-coded options */ diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c index 358a70ddd1..de3bfa8cc0 100644 --- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/arm_l2cc_pl310.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2, * Technical Reference Manual, ARM DDI 0246F (ID011711), ARM @@ -45,7 +45,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ***********************************************************/ + +/* Configuration ************************************************************/ + /* Number of ways depends on ARM configuration */ #if defined(CONFIG_ARMV7R_ASSOCIATIVITY_8WAY) @@ -302,17 +304,18 @@ void arm_l2ccinitialize(void) /* Make sure that this is a PL310 cache, version r3p2. * * REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is - * r3p2, but the chip that I have actually* reports 0x410000C9 which is some - * later revision. + * r3p2, but the chip that I have actually* reports 0x410000C9 which is + * some later revision. */ - //DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2); + /* DEBUGASSERT((getreg32(L2CC_IDR) & + * L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2); + */ /* Make sure that actual cache configuration agrees with the configured * cache configuration. */ - #if defined(CONFIG_ARMV7R_ASSOCIATIVITY_8WAY) DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0); #elif defined(CONFIG_ARMV7R_ASSOCIATIVITY_16WAY) @@ -322,17 +325,23 @@ void arm_l2ccinitialize(void) #endif #if defined(CONFIG_ARMV7R_WAYSIZE_16KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB); + DEBUGASSERT((getreg32(L2CC_ACR) & + L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB); #elif defined(CONFIG_ARMV7R_WAYSIZE_32KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB); + DEBUGASSERT((getreg32(L2CC_ACR) & + L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB); #elif defined(CONFIG_ARMV7R_WAYSIZE_64KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB); + DEBUGASSERT((getreg32(L2CC_ACR) & + L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB); #elif defined(CONFIG_ARMV7R_WAYSIZE_128KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB); + DEBUGASSERT((getreg32(L2CC_ACR) & + L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB); #elif defined(CONFIG_ARMV7R_WAYSIZE_256KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB); + DEBUGASSERT((getreg32(L2CC_ACR) & + L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB); #elif defined(CONFIG_ARMV7R_WAYSIZE_512KB) - DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB); + DEBUGASSERT((getreg32(L2CC_ACR) & + L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB); #else # error No way size selected #endif diff --git a/arch/arm/src/armv7-r/arm_mpu.c b/arch/arm/src/armv7-r/arm_mpu.c index d17bede4b6..5fd372339b 100644 --- a/arch/arm/src/armv7-r/arm_mpu.c +++ b/arch/arm/src/armv7-r/arm_mpu.c @@ -33,6 +33,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_ARM_MPU_NREGIONS @@ -121,7 +122,7 @@ static inline uint32_t mpu_subregion_ms(size_t size, uint8_t l2size) } asize = (size + mask) & ~mask; /* Adjusted size */ - nsrs = asize >> (l2size-3); /* Number of subregions */ + nsrs = asize >> (l2size - 3); /* Number of subregions */ return g_ms_regionmask[nsrs]; } @@ -171,8 +172,8 @@ static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size) mask = 0x1fffffff; /* Shifted mask */ } - aoffset = offset & ~mask; /* Adjusted offset */ - nsrs = aoffset >> (l2size-3); /* Number of subregions */ + aoffset = offset & ~mask; /* Adjusted offset */ + nsrs = aoffset >> (l2size - 3); /* Number of subregions */ return g_ls_regionmask[nsrs]; } diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c index 05b263a950..4ae10c6520 100644 --- a/arch/arm/src/armv7-r/arm_prefetchabort.c +++ b/arch/arm/src/armv7-r/arm_prefetchabort.c @@ -48,8 +48,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) { - /* Save the saved processor context in CURRENT_REGS where it can be accessed - * for register dumps and possibly context switching. + /* Save the saved processor context in CURRENT_REGS where it can be + * accessed for register dumps and possibly context switching. */ CURRENT_REGS = regs; diff --git a/arch/arm/src/armv7-r/arm_restorefpu.S b/arch/arm/src/armv7-r/arm_restorefpu.S index a4a0ef2c9a..4ffd987b5f 100644 --- a/arch/arm/src/armv7-r/arm_restorefpu.S +++ b/arch/arm/src/armv7-r/arm_restorefpu.S @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/arm_restorefpu.S * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -28,9 +28,9 @@ #ifdef CONFIG_ARCH_FPU -/************************************************************************************ +/**************************************************************************** * Public Symbols - ************************************************************************************/ + ****************************************************************************/ .globl arm_restorefpu @@ -42,13 +42,13 @@ .syntax unified .file "arm_restorefpu.S" -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ .text -/************************************************************************************ +/**************************************************************************** * Name: arm_restorefpu * * Description: @@ -66,7 +66,7 @@ * This function does not return anything explicitly. However, it is called from * interrupt level assembly logic that assumes that r0 is preserved. * - ************************************************************************************/ + ****************************************************************************/ .globl arm_restorefpu .type arm_restorefpu, function diff --git a/arch/arm/src/armv7-r/arm_savefpu.S b/arch/arm/src/armv7-r/arm_savefpu.S index dc3b102779..93bc44084b 100644 --- a/arch/arm/src/armv7-r/arm_savefpu.S +++ b/arch/arm/src/armv7-r/arm_savefpu.S @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/arm_savefpu.S * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -30,23 +30,23 @@ .file "arm_savefpu.S" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Symbols - ************************************************************************************/ + ****************************************************************************/ .globl arm_savefpu -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ .text -/************************************************************************************ +/**************************************************************************** * Name: arm_savefpu * * Description: @@ -63,7 +63,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .globl arm_savefpu .type arm_savefpu, function diff --git a/arch/arm/src/armv7-r/arm_vectors.S b/arch/arm/src/armv7-r/arm_vectors.S index fbc78913c8..a343bedfef 100644 --- a/arch/arm/src/armv7-r/arm_vectors.S +++ b/arch/arm/src/armv7-r/arm_vectors.S @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/arm_vectors.S * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -30,13 +30,13 @@ .file "arm_vectors.S" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ .data g_irqtmp: @@ -54,27 +54,27 @@ g_fiqtmp: .word 0 /* Saved spsr */ #endif -/************************************************************************************ +/**************************************************************************** * Assembly Macros - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ .text -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorirq * * Description: * Interrupt exception. Entered in IRQ mode with spsr = SVC CPSR, lr = SVC PC * - ************************************************************************************/ + ****************************************************************************/ .globl arm_decodeirq .globl arm_vectorirq @@ -224,13 +224,13 @@ arm_vectorirq: .size arm_vectorirq, . - arm_vectorirq .align 5 -/************************************************************************************ +/**************************************************************************** * Function: arm_vectorsvc * * Description: * SVC interrupt. We enter the SVC in SVC mode. * - ************************************************************************************/ + ****************************************************************************/ .globl arm_syscall .globl arm_vectorsvc @@ -348,7 +348,7 @@ arm_vectorsvc: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectordata * * Description: @@ -357,7 +357,7 @@ arm_vectorsvc: * current processor state and gives control to data abort handler. This function * is entered in ABORT mode with spsr = SVC CPSR, lr = SVC PC * - ************************************************************************************/ + ****************************************************************************/ .globl arm_dataabort .globl arm_vectordata @@ -494,7 +494,7 @@ arm_vectordata: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorprefetch * * Description: @@ -503,7 +503,7 @@ arm_vectordata: * handler saves the current processor state and gives control to prefetch abort * handler. This function is entered in ABT mode with spsr = SVC CPSR, lr = SVC PC. * - ************************************************************************************/ + ****************************************************************************/ .globl arm_prefetchabort .globl arm_vectorprefetch @@ -640,14 +640,14 @@ arm_vectorprefetch: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorundefinsn * * Description: * Undefined instruction entry exception. Entered in UND mode, spsr = SVC CPSR, * lr = SVC PC * - ************************************************************************************/ + ****************************************************************************/ .globl arm_undefinedinsn .globl arm_vectorundefinsn @@ -781,14 +781,14 @@ arm_vectorundefinsn: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorfiq * * Description: * Shouldn't happen unless a arm_decodefiq() is provided. FIQ is primarily used * with the TrustZone feature in order to handle secure interrupts. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_ARMV7R_DECODEFIQ .globl arm_decodefiq @@ -938,9 +938,9 @@ arm_vectorfiq: #endif .size arm_vectorfiq, . - arm_vectorfiq -/************************************************************************************ +/**************************************************************************** * Name: g_intstackalloc/g_intstackbase - ************************************************************************************/ + ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 7 .bss diff --git a/arch/arm/src/armv7-r/barriers.h b/arch/arm/src/armv7-r/barriers.h index d1ff2040b2..7e32a76af6 100644 --- a/arch/arm/src/armv7-r/barriers.h +++ b/arch/arm/src/armv7-r/barriers.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/barriers.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,18 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_COMMON_ARMV7_R_BARRIERS_H #define __ARCH_ARM_SRC_COMMON_ARMV7_R_BARRIERS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* ARMv7-R memory barriers */ diff --git a/arch/arm/src/armv7-r/cp15.h b/arch/arm/src/armv7-r/cp15.h index 883ac099ad..8f2d2bd8ee 100644 --- a/arch/arm/src/armv7-r/cp15.h +++ b/arch/arm/src/armv7-r/cp15.h @@ -1,15 +1,10 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/cp15.h * CP15 register access * * Copyright (C) 2015 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * References: - * - * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright - * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414) - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -37,20 +32,27 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ + +/* References: + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. + * All rights reserved. ARM DDI 0406C.c (ID051414) + */ #ifndef __ARCH_ARM_SRC_ARMV7_R_CP15_H #define __ARCH_ARM_SRC_ARMV7_R_CP15_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* System control register descriptions. * * CP15 registers are accessed with MRC and MCR instructions as follows: @@ -107,15 +109,15 @@ #define CP15_DFAR(r) _CP15(0, r, c6, c0, 0) /* Data Fault Address Register */ #define CP15_IFAR(r) _CP15(0, r, c6, c0, 2) /* Instruction Fault Address Register */ -#define CP15_DRBAR(r) _CP15(0, r, c6, c1, 0) /* Data Region Base Address Register */ -#define CP15_DRSR(r) _CP15(0, r, c6, c1, 2) /* Data Region Size and Enable Register */ -#define CP15_DRACR(r) _CP15(0, r, c6, c1, 4) /* Data Region Access Control Register */ +#define CP15_DRBAR(r) _CP15(0, r, c6, c1, 0) /* Data Region Base Address Register */ +#define CP15_DRSR(r) _CP15(0, r, c6, c1, 2) /* Data Region Size and Enable Register */ +#define CP15_DRACR(r) _CP15(0, r, c6, c1, 4) /* Data Region Access Control Register */ #ifndef CONFIG_ARM_HAVE_MPU_UNIFIED -# define CP15_IRBAR(r) _CP15(0, r, c6, c1, 1) /* Instruction Region Base Address Register */ -# define CP15_IRSR(r) _CP15(0, r, c6, c1, 3) /* Instruction Region Size and Enable Register */ -# define CP15_IRACR(r) _CP15(0, r, c6, c1, 5) /* Instruction Region Access Control Register */ +# define CP15_IRBAR(r) _CP15(0, r, c6, c1, 1) /* Instruction Region Base Address Register */ +# define CP15_IRSR(r) _CP15(0, r, c6, c1, 3) /* Instruction Region Size and Enable Register */ +# define CP15_IRACR(r) _CP15(0, r, c6, c1, 5) /* Instruction Region Access Control Register */ #endif -#define CP15_RGNR(r) _CP15(0, r, c6, c2, 0) /* MPU Region Number Register */ +#define CP15_RGNR(r) _CP15(0, r, c6, c2, 0) /* MPU Region Number Register */ #define CP15_ICIALLUIS(r) _CP15(0, r, c7, c1, 0) /* Cache Operations Registers */ #define CP15_BPIALLIS(r) _CP15(0, r, c7, c1, 6) @@ -155,16 +157,16 @@ #define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3) #define CP15_TPIDRPRW(r) _CP15(0, r, c13, c0, 4) -#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */ -#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */ -#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */ -#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical Timer Control register */ -#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */ -#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */ -#define CP15_CNTPCT(r,n) _CP15(0, r, c14, c14, n) /* 64-bit Physical Count register */ -#define CP15_CNTVCT(r,n) _CP15(1, r, c14, c14, n) /* Virtual Count register */ +#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */ +#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */ +#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */ +#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical Timer Control register */ +#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */ +#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */ +#define CP15_CNTPCT(r,n) _CP15(0, r, c14, c14, n) /* 64-bit Physical Count register */ +#define CP15_CNTVCT(r,n) _CP15(1, r, c14, c14, n) /* Virtual Count register */ #define CP15_CNTP_CVAL(r,n) _CP15(2, r, c14, c14, n) /* PL1 Physical Timer CompareValue register */ #define CP15_CNTV_CVAL(r,n) _CP15(3, r, c14, c14, n) /* Virtual Timer CompareValue register */ -#define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */ +#define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */ #endif /* __ARCH_ARM_SRC_ARMV7_R_CP15_H */ diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h index 1713e2e38f..5b439cf049 100644 --- a/arch/arm/src/armv7-r/cp15_cacheops.h +++ b/arch/arm/src/armv7-r/cp15_cacheops.h @@ -1,16 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/cp15_cacheops.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * References: - * - * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright © - * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414) - * - * Portions of this file derive from Atmel sample code for the SAMA5D3 Cortex-A5 - * which also has a modified BSD-style license: + * Portions of this file derive from Atmel sample code for the SAMA5D3 + * Cortex-A5 which also has a modified BSD-style license: * * Copyright (c) 2012, Atmel Corporation * All rights reserved. @@ -42,32 +37,42 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ + +/* References: + * + * "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved. + * ARM DDI 0406C.c (ID051414) + */ #ifndef __ARCH_ARM_SRC_ARMV7_R_CP15_CACHEOPS_H #define __ARCH_ARM_SRC_ARMV7_R_CP15_CACHEOPS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Cache definitions ****************************************************************/ + ****************************************************************************/ + +/* Cache definitions ********************************************************/ + /* L1 Memory */ #define CP15_L1_LINESIZE 32 -/* CP15 Registers *******************************************************************/ +/* CP15 Registers ***********************************************************/ + /* Terms: * 1) Point of coherency (PoC) - * The PoC is the point at which all agents that can access memory are guaranteed - * to see the same copy of a memory location + * The PoC is the point at which all agents that can access memory are + * guaranteed to see the same copy of a memory location * 2) Point of unification (PoU) * The PoU is the point by which the instruction and data caches and the - * translation table walks of the processor are guaranteed to see the same copy - * of a memory location. + * translation table walks of the processor are guaranteed to see the same + * copy of a memory location. * * Cache Operations: * @@ -76,12 +81,13 @@ * Register Format: Should be zero (SBZ) * Instruction: MCR p15, 0, , c7, c1, 0 * CP15 Register: BPIALLIS - * Description: Invalidate entire branch predictor array Inner Shareable. + * Description: Invalidate entire branch predictor array Inner + * Shareable. * Register Format: Should be zero (SBZ) * Instruction: MCR p15, 0, , c7, c1, 6 * CP15 Register: ICIALLU - * Description: Invalidate all instruction caches to PoU. Also flushes branch - * target cache. + * Description: Invalidate all instruction caches to PoU. Also flushes + * branch target cache. * Register Format: Should be zero (SBZ) * Instruction: MCR p15, 0, , c7, c5, 0 * CP15 Register: ICIMVAU @@ -165,9 +171,10 @@ #define CACHE_SBZ_MASK (31 << TLB_SBZ_SHIFT) #define CACHE_VA_MASK (0xfffffffe0) /* Bits 5-31: Virtual address */ -/************************************************************************************ +/**************************************************************************** * Assembly Macros - ************************************************************************************/ + ****************************************************************************/ + /* cp15_cache Cache Operations * * Usage @@ -201,7 +208,7 @@ #ifdef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Name: cp15_enable_dcache * * Description: @@ -213,7 +220,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_enable_dcache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ @@ -221,7 +228,7 @@ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_disable_dcache * * Description: @@ -233,7 +240,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_disable_dcache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ @@ -241,7 +248,7 @@ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_enable_icache * * Description: @@ -253,7 +260,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_enable_icache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ @@ -261,7 +268,7 @@ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_disable_icache * * Description: @@ -273,7 +280,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_disable_icache, tmp mrc p15, 0, \tmp, c1, c0, 0 /* Read SCTLR */ @@ -281,7 +288,7 @@ mcr p15, 0, \tmp, c1, c0, 0 /* Update the SCTLR */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_icache_inner_sharable * * Description: @@ -293,14 +300,14 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_invalidate_icache_inner_sharable, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_btb_inner_sharable * * Description: @@ -312,18 +319,19 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_invalidate_btb_inner_sharable, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_icache * * Description: - * Invalidate all instruction caches to PoU, also flushes branch target cache + * Invalidate all instruction caches to PoU, also flushes branch target + * cache * * Input Parameters: * None @@ -331,14 +339,14 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_invalidate_icache, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_icache_bymva * * Description: @@ -350,13 +358,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_invalidate_icache_bymva, va mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_flush_btb * * Description: @@ -368,14 +376,14 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_flush_btb, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_flush_btb_bymva * * Description: @@ -387,14 +395,14 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_flush_btb_bymva, tmp mov \tmp, #0 mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_dcacheline_bymva * * Description: @@ -406,13 +414,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_invalidate_dcacheline_bymva, va mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_dcacheline_bysetway * * Description: @@ -424,13 +432,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_invalidate_dcacheline_bysetway, setway mrc p15, 0, \setway, c7, c6, 2 /* DCISW */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_clean_dcache_bymva * * Description: @@ -442,13 +450,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_clean_dcache_bymva, va mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_clean_dcache_bysetway * * Description: @@ -460,13 +468,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_clean_dcache_bysetway, setway mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_clean_ucache_bymva * * Description: @@ -478,13 +486,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_clean_ucache_bymva, setway mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline_bymva * * Description: @@ -496,13 +504,13 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_cleaninvalidate_dcacheline_bymva, va mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */ .endm -/************************************************************************************ +/**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline * * Description: @@ -514,7 +522,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ .macro cp15_cleaninvalidate_dcacheline, setway mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */ @@ -522,13 +530,13 @@ #endif /* __ASSEMBLY__ */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Name: cp15_enable_dcache * * Description: @@ -540,7 +548,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_enable_dcache(void) { @@ -555,7 +563,7 @@ static inline void cp15_enable_dcache(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_disable_dcache * * Description: @@ -567,7 +575,7 @@ static inline void cp15_enable_dcache(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_disable_dcache(void) { @@ -582,7 +590,7 @@ static inline void cp15_disable_dcache(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_enable_icache * * Description: @@ -594,7 +602,7 @@ static inline void cp15_disable_dcache(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_enable_icache(void) { @@ -609,7 +617,7 @@ static inline void cp15_enable_icache(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_disable_icache * * Description: @@ -621,7 +629,7 @@ static inline void cp15_enable_icache(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_disable_icache(void) { @@ -636,7 +644,7 @@ static inline void cp15_disable_icache(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_icache_inner_sharable * * Description: @@ -648,7 +656,7 @@ static inline void cp15_disable_icache(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_invalidate_icache_inner_sharable(void) { @@ -662,7 +670,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_btb_inner_sharable * * Description: @@ -674,7 +682,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_invalidate_btb_inner_sharable(void) { @@ -688,11 +696,12 @@ static inline void cp15_invalidate_btb_inner_sharable(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_icache * * Description: - * Invalidate all instruction caches to PoU, also flushes branch target cache + * Invalidate all instruction caches to PoU, also flushes branch target + * cache * * Input Parameters: * None @@ -700,7 +709,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_invalidate_icache(void) { @@ -714,7 +723,7 @@ static inline void cp15_invalidate_icache(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_icache_bymva * * Description: @@ -726,7 +735,7 @@ static inline void cp15_invalidate_icache(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_invalidate_icache_bymva(unsigned int va) { @@ -739,7 +748,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_flush_btb * * Description: @@ -751,7 +760,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_flush_btb(void) { @@ -765,7 +774,7 @@ static inline void cp15_flush_btb(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_flush_btb_bymva * * Description: @@ -777,7 +786,7 @@ static inline void cp15_flush_btb(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_flush_btb_bymva(void) { @@ -791,7 +800,7 @@ static inline void cp15_flush_btb_bymva(void) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_dcacheline_bymva * * Description: @@ -803,7 +812,7 @@ static inline void cp15_flush_btb_bymva(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ /* Invalidate data cache line by VA to PoC */ @@ -818,7 +827,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_invalidate_dcacheline_bysetway * * Description: @@ -830,7 +839,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ /* Invalidate data cache line by set/way */ @@ -845,7 +854,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_clean_dcache_bymva * * Description: @@ -857,7 +866,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ /* Clean data cache line by MVA */ @@ -872,7 +881,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_clean_dcache_bysetway * * Description: @@ -884,7 +893,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_clean_dcache_bysetway(unsigned int setway) { @@ -897,7 +906,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_clean_ucache_bymva * * Description: @@ -909,7 +918,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_clean_ucache_bymva(unsigned int setway) { @@ -922,7 +931,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline_bymva * * Description: @@ -934,7 +943,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) { @@ -947,7 +956,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) ); } -/************************************************************************************ +/**************************************************************************** * Name: cp15_cleaninvalidate_dcacheline * * Description: @@ -959,7 +968,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway) { diff --git a/arch/arm/src/armv7-r/gic.h b/arch/arm/src/armv7-r/gic.h index 6b9ddef735..17c0fd0cd4 100644 --- a/arch/arm/src/armv7-r/gic.h +++ b/arch/arm/src/armv7-r/gic.h @@ -47,65 +47,65 @@ /* 1x32 bit field per register */ -#define GIC_INDEX1(n) (n) /* 1 field per word */ -#define GIC_OFFSET1(n) (GIC_INDEX1(n) << 2) /* 32-bit word offset */ -#define GIC_SHIFT1(n) (0) /* No shift */ -#define GIC_MASK1(n) (0xffffffff) /* Whole word */ +#define GIC_INDEX1(n) (n) /* 1 field per word */ +#define GIC_OFFSET1(n) (GIC_INDEX1(n) << 2) /* 32-bit word offset */ +#define GIC_SHIFT1(n) (0) /* No shift */ +#define GIC_MASK1(n) (0xffffffff) /* Whole word */ /* 2x16 bit field per register */ -#define GIC_INDEX2(n) (n >> 1) /* 2 fields per word */ -#define GIC_OFFSET2(n) (GIC_INDEX2(n) << 2) /* 32-bit word offset */ -#define GIC_SHIFT2(n) (((n) & 1) << 4) /* Shift 16-bits per field */ -#define GIC_MASK2(n) (0xffff << GIC_SHIFT2(n)) /* 16-bit mask */ +#define GIC_INDEX2(n) (n >> 1) /* 2 fields per word */ +#define GIC_OFFSET2(n) (GIC_INDEX2(n) << 2) /* 32-bit word offset */ +#define GIC_SHIFT2(n) (((n) & 1) << 4) /* Shift 16-bits per field */ +#define GIC_MASK2(n) (0xffff << GIC_SHIFT2(n)) /* 16-bit mask */ /* 4x8 bit field per register */ -#define GIC_INDEX4(n) (n >> 2) /* 4 fields per word */ -#define GIC_OFFSET4(n) (GIC_INDEX4(n) << 2) /* 32-bit word offset */ -#define GIC_SHIFT4(n) (((n) & 3) << 3) /* Shift 8-bits per field */ -#define GIC_MASK4(n) (0xff << GIC_SHIFT4(n)) /* 8-bit mask */ +#define GIC_INDEX4(n) (n >> 2) /* 4 fields per word */ +#define GIC_OFFSET4(n) (GIC_INDEX4(n) << 2) /* 32-bit word offset */ +#define GIC_SHIFT4(n) (((n) & 3) << 3) /* Shift 8-bits per field */ +#define GIC_MASK4(n) (0xff << GIC_SHIFT4(n)) /* 8-bit mask */ /* 8x4 bit field per register */ -#define GIC_INDEX8(n) (n >> 3) /* 8 fields per word */ -#define GIC_OFFSET8(n) (GIC_INDEX8(n) << 2) /* 32-bit word offset */ -#define GIC_SHIFT8(n) (((n) & 7) << 2) /* Shift 4-bits per field */ -#define GIC_MASK8(n) (15 << GIC_SHIFT8(n)) /* 4-bit mask */ +#define GIC_INDEX8(n) (n >> 3) /* 8 fields per word */ +#define GIC_OFFSET8(n) (GIC_INDEX8(n) << 2) /* 32-bit word offset */ +#define GIC_SHIFT8(n) (((n) & 7) << 2) /* Shift 4-bits per field */ +#define GIC_MASK8(n) (15 << GIC_SHIFT8(n)) /* 4-bit mask */ /* 16x2 bit field per register */ -#define GIC_INDEX16(n) (n >> 4) /* 16 fields per word */ -#define GIC_OFFSET16(n) (GIC_INDEX16(n) << 2) /* 32-bit word offset */ -#define GIC_SHIFT16(n) (((n) & 15) << 1) /* Shift 2-bits per field */ -#define GIC_MASK16(n) (3 << GIC_SHIFT16(n)) /* 2-bit mask */ +#define GIC_INDEX16(n) (n >> 4) /* 16 fields per word */ +#define GIC_OFFSET16(n) (GIC_INDEX16(n) << 2) /* 32-bit word offset */ +#define GIC_SHIFT16(n) (((n) & 15) << 1) /* Shift 2-bits per field */ +#define GIC_MASK16(n) (3 << GIC_SHIFT16(n)) /* 2-bit mask */ /* 32x1 bit field per register */ -#define GIC_INDEX32(n) (n >> 5) /* 32 fields per word */ -#define GIC_OFFSET32(n) (GIC_INDEX32(n) << 2) /* 32-bit word offset */ -#define GIC_SHIFT32(n) ((n) & 31) /* Shift 1-bit per field */ -#define GIC_MASK32(n) (1U << GIC_SHIFT32(n)) /* 1-bit mask */ +#define GIC_INDEX32(n) (n >> 5) /* 32 fields per word */ +#define GIC_OFFSET32(n) (GIC_INDEX32(n) << 2) /* 32-bit word offset */ +#define GIC_SHIFT32(n) ((n) & 31) /* Shift 1-bit per field */ +#define GIC_MASK32(n) (1U << GIC_SHIFT32(n)) /* 1-bit mask */ /* GIC Register Offsets *****************************************************/ /* Interrupt Interface registers */ -#define GIC_ICCICR_OFFSET 0x0000 /* CPU Interface Control Register */ -#define GIC_ICCPMR_OFFSET 0x0004 /* Interrupt Priority Mask Register */ -#define GIC_ICCBPR_OFFSET 0x0008 /* Binary point Register */ -#define GIC_ICCIAR_OFFSET 0x000c /* Interrupt Acknowledge */ -#define GIC_ICCEOIR_OFFSET 0x0010 /* End of interrupt */ -#define GIC_ICCRPR_OFFSET 0x0014 /* Running interrupt */ -#define GIC_ICCHPIR_OFFSET 0x0018 /* Highest pending interrupt */ -#define GIC_ICCABPR_OFFSET 0x001c /* Aliased Non-secure Binary Point Register */ -#define GIC_ICCIDR_OFFSET 0x00fc /* CPU Interface Implementer ID Register */ +#define GIC_ICCICR_OFFSET 0x0000 /* CPU Interface Control Register */ +#define GIC_ICCPMR_OFFSET 0x0004 /* Interrupt Priority Mask Register */ +#define GIC_ICCBPR_OFFSET 0x0008 /* Binary point Register */ +#define GIC_ICCIAR_OFFSET 0x000c /* Interrupt Acknowledge */ +#define GIC_ICCEOIR_OFFSET 0x0010 /* End of interrupt */ +#define GIC_ICCRPR_OFFSET 0x0014 /* Running interrupt */ +#define GIC_ICCHPIR_OFFSET 0x0018 /* Highest pending interrupt */ +#define GIC_ICCABPR_OFFSET 0x001c /* Aliased Non-secure Binary Point Register */ +#define GIC_ICCIDR_OFFSET 0x00fc /* CPU Interface Implementer ID Register */ /* Distributor Registers */ -#define GIC_ICDDCR_OFFSET 0x0000 /* Distributor Control Register */ -#define GIC_ICDICTR_OFFSET 0x0004 /* Interrupt Controller Type Register */ -#define GIC_ICDIIDR_OFFSET 0x0008 /* Distributor Implementer ID Register */ +#define GIC_ICDDCR_OFFSET 0x0000 /* Distributor Control Register */ +#define GIC_ICDICTR_OFFSET 0x0004 /* Interrupt Controller Type Register */ +#define GIC_ICDIIDR_OFFSET 0x0008 /* Distributor Implementer ID Register */ /* 0x000c-0x007c: Reserved */ @@ -153,7 +153,7 @@ /* PPI Status Register: 0x0d00 */ -#define GIC_ICDPPISR_OFFSET 0x0d00 /* PPI Status Register */ +#define GIC_ICDPPISR_OFFSET 0x0d00 /* PPI Status Register */ /* SPI Status Registers: 0x0d04-0x0d1c */ @@ -163,7 +163,7 @@ /* Software Generated Interrupt Register: 0x0f00 */ -#define GIC_ICDSGIR_OFFSET 0x0f00 /* Software Generated Interrupt Register */ +#define GIC_ICDSGIR_OFFSET 0x0f00 /* Software Generated Interrupt Register */ /* 0x0f0c-0x0fcc: Reserved */ @@ -178,6 +178,7 @@ /* 0x0f04-0x0ffc: Reserved */ /* GIC Register Addresses ***************************************************/ + /* The Interrupt Controller is a single functional unit that is located in a * Cortex-A9 MPCore design. There is one interrupt interface per Cortex-A9 * processor. Registers are memory mapped and accessed through a chip- @@ -222,38 +223,42 @@ /* CPU Interface Control Register -- without security extensions */ -#define GIC_ICCICR_ENABLE (1 << 0) /* Bit 0: Enable the CPU interface for this GIC */ +#define GIC_ICCICR_ENABLE (1 << 0) /* Bit 0: Enable the CPU interface for this GIC */ /* Bits 1-31: Reserved */ -/* CPU Interface Control Register -- with security extensions, non-secure copy */ +/* CPU Interface Control Register -- with security extensions, + * non-secure copy + */ -#define GIC_ICCICRU_ENABLEGRP1 (1 << 0) /* Bit 0: Enable Group 1 interrupts for the CPU */ +#define GIC_ICCICRU_ENABLEGRP1 (1 << 0) /* Bit 0: Enable Group 1 interrupts for the CPU */ /* Bits 1-4: Reserved */ -#define GIC_ICCICRU_FIQBYPDISGRP1 (1 << 5) /* Bit 5: FIQ disabled for CPU Group 1 */ -#define GIC_ICCICRU_IRQBYPDISGRP1 (1 << 6) /* Bit 6: IRQ disabled for CPU Group 1 */ +#define GIC_ICCICRU_FIQBYPDISGRP1 (1 << 5) /* Bit 5: FIQ disabled for CPU Group 1 */ +#define GIC_ICCICRU_IRQBYPDISGRP1 (1 << 6) /* Bit 6: IRQ disabled for CPU Group 1 */ /* Bits 7-8: Reserved */ -#define GIC_ICCICRU_EOIMODENS (1 << 9) /* Bit 9: Control EIOIR access (non-secure) */ +#define GIC_ICCICRU_EOIMODENS (1 << 9) /* Bit 9: Control EIOIR access (non-secure) */ /* Bits 10-31: Reserved */ -/* CPU Interface Control Register -- with security extensions, secure copy */ +/* CPU Interface Control Register -- with security extensions, + * secure copy + */ -#define GIC_ICCICRS_ENABLEGRP0 (1 << 0) /* Bit 0: Enable Group 0 interrupts for the CPU */ -#define GIC_ICCICRS_ENABLEGRP1 (1 << 1) /* Bit 1: Enable Group 1 interrupts for the CPU */ -#define GIC_ICCICRS_ACKTCTL (1 << 2) /* Bit 2: Group 1 interrupt activation control */ -#define GIC_ICCICRS_FIQEN (1 << 3) /* Bit 3: Signal Group 0 via FIQ */ -#define GIC_ICCICRS_CBPR (1 << 4) /* Bit 4: Control Group 0/1 Pre-emption */ -#define GIC_ICCICRS_FIQBYPDISGRP0 (1 << 5) /* Bit 5: FIQ disabled for CPU Group 0 */ -#define GIC_ICCICRS_IRQBYPDISGRP0 (1 << 6) /* Bit 6: IRQ disabled for CPU Group 0 */ -#define GIC_ICCICRS_FIQBYPDISGRP1 (1 << 7) /* Bit 5: FIQ disabled for CPU Group 1 */ -#define GIC_ICCICRS_IRQBYPDISGRP1 (1 << 8) /* Bit 6: IRQ disabled for CPU Group 1 */ -#define GIC_ICCICRS_EOIMODES (1 << 9) /* Bit 6: Control EIOIR access (secure) */ -#define GIC_ICCICRS_EOIMODENS (1 << 10) /* Bit 10: Control EIOIR access (non-secure) */ +#define GIC_ICCICRS_ENABLEGRP0 (1 << 0) /* Bit 0: Enable Group 0 interrupts for the CPU */ +#define GIC_ICCICRS_ENABLEGRP1 (1 << 1) /* Bit 1: Enable Group 1 interrupts for the CPU */ +#define GIC_ICCICRS_ACKTCTL (1 << 2) /* Bit 2: Group 1 interrupt activation control */ +#define GIC_ICCICRS_FIQEN (1 << 3) /* Bit 3: Signal Group 0 via FIQ */ +#define GIC_ICCICRS_CBPR (1 << 4) /* Bit 4: Control Group 0/1 Pre-emption */ +#define GIC_ICCICRS_FIQBYPDISGRP0 (1 << 5) /* Bit 5: FIQ disabled for CPU Group 0 */ +#define GIC_ICCICRS_IRQBYPDISGRP0 (1 << 6) /* Bit 6: IRQ disabled for CPU Group 0 */ +#define GIC_ICCICRS_FIQBYPDISGRP1 (1 << 7) /* Bit 5: FIQ disabled for CPU Group 1 */ +#define GIC_ICCICRS_IRQBYPDISGRP1 (1 << 8) /* Bit 6: IRQ disabled for CPU Group 1 */ +#define GIC_ICCICRS_EOIMODES (1 << 9) /* Bit 6: Control EIOIR access (secure) */ +#define GIC_ICCICRS_EOIMODENS (1 << 10) /* Bit 10: Control EIOIR access (non-secure) */ /* Bits 11-31: Reserved */ @@ -274,25 +279,25 @@ * point settings make sense. */ -#define GIC_ICCBPR_SHIFT (0) /* Bits 0-2: Binary point */ -#define GIC_ICCBPR_MASK (7 << GIC_ICCBPR_SHIFT) -#define GIC_ICCBPR_1_7 (0 << GIC_ICCBPR_SHIFT) /* Priority bits [7:1] compared for pre-emption */ -#define GIC_ICCBPR_2_7 (1 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */ -#define GIC_ICCBPR_3_7 (2 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */ -#define GIC_ICCBPR_4_7 (3 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */ -#define GIC_ICCBPR_5_7 (4 << GIC_ICCBPR_SHIFT) /* Priority bits [7:5] compared for pre-emption */ -#define GIC_ICCBPR_6_7 (5 << GIC_ICCBPR_SHIFT) /* Priority bits [7:6] compared for pre-emption */ -#define GIC_ICCBPR_7_7 (6 << GIC_ICCBPR_SHIFT) /* Priority bit [7] compared for pre-emption */ -#define GIC_ICCBPR_NOPREMPT (7 << GIC_ICCBPR_SHIFT) /* No pre-emption is performed */ +#define GIC_ICCBPR_SHIFT (0) /* Bits 0-2: Binary point */ +#define GIC_ICCBPR_MASK (7 << GIC_ICCBPR_SHIFT) +#define GIC_ICCBPR_1_7 (0 << GIC_ICCBPR_SHIFT) /* Priority bits [7:1] compared for pre-emption */ +#define GIC_ICCBPR_2_7 (1 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */ +#define GIC_ICCBPR_3_7 (2 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */ +#define GIC_ICCBPR_4_7 (3 << GIC_ICCBPR_SHIFT) /* Priority bits [7:2] compared for pre-emption */ +#define GIC_ICCBPR_5_7 (4 << GIC_ICCBPR_SHIFT) /* Priority bits [7:5] compared for pre-emption */ +#define GIC_ICCBPR_6_7 (5 << GIC_ICCBPR_SHIFT) /* Priority bits [7:6] compared for pre-emption */ +#define GIC_ICCBPR_7_7 (6 << GIC_ICCBPR_SHIFT) /* Priority bit [7] compared for pre-emption */ +#define GIC_ICCBPR_NOPREMPT (7 << GIC_ICCBPR_SHIFT) /* No pre-emption is performed */ /* Bits 3-31: Reserved */ /* Interrupt Acknowledge Register */ -#define GIC_ICCIAR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ +#define GIC_ICCIAR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ #define GIC_ICCIAR_INTID_MASK (0x3ff << GIC_ICCIAR_INTID_SHIFT) #define GIC_ICCIAR_INTID(n) ((uint32_t)(n) << GIC_ICCIAR_INTID_SHIFT) -#define GIC_ICCIAR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */ +#define GIC_ICCIAR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */ #define GIC_ICCIAR_CPUSRC_MASK (7 << GIC_ICCIAR_CPUSRC_SHIFT) #define GIC_ICCIAR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCIAR_CPUSRC_SHIFT) @@ -302,10 +307,10 @@ #define GIC_ICCEOIR_SPURIOUS (0x3ff) -#define GIC_ICCEOIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ +#define GIC_ICCEOIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ #define GIC_ICCEOIR_INTID_MASK (0x3ff << GIC_ICCEOIR_INTID_SHIFT) #define GIC_ICCEOIR_INTID(n) ((uint32_t)(n) << GIC_ICCEOIR_INTID_SHIFT) -#define GIC_ICCEOIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */ +#define GIC_ICCEOIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */ #define GIC_ICCEOIR_CPUSRC_MASK (7 << GIC_ICCEOIR_CPUSRC_SHIFT) #define GIC_ICCEOIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCEOIR_CPUSRC_SHIFT) @@ -315,7 +320,7 @@ /* Bits 0-3: Reserved */ -#define GIC_ICCRPR_PRIO_SHIFT (4) /* Bits 4-7: Priority mask */ +#define GIC_ICCRPR_PRIO_SHIFT (4) /* Bits 4-7: Priority mask */ #define GIC_ICCRPR_PRIO_MASK (15 << GIC_ICCRPR_PRIO_SHIFT) #define GIC_ICCRPR_PRIO_VALUE(n) ((uint32_t)(n) << GIC_ICCRPR_PRIO_SHIFT) @@ -323,10 +328,10 @@ /* Highest Pending Interrupt Register */ -#define GIC_ICCHPIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ +#define GIC_ICCHPIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ #define GIC_ICCHPIR_INTID_MASK (0x3ff << GIC_ICCHPIR_INTID_SHIFT) #define GIC_ICCHPIR_INTID(n) ((uint32_t)(n) << GIC_ICCHPIR_INTID_SHIFT) -#define GIC_ICCHPIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */ +#define GIC_ICCHPIR_CPUSRC_SHIFT (10) /* Bits 10-12: CPU source ID */ #define GIC_ICCHPIR_CPUSRC_MASK (7 << GIC_ICCHPIR_CPUSRC_SHIFT) #define GIC_ICCHPIR_CPUSRC(n) ((uint32_t)(n) << GIC_ICCHPIR_CPUSRC_SHIFT) @@ -334,46 +339,46 @@ /* CPU Interface Implementer ID Register */ -#define GIC_ICCIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */ +#define GIC_ICCIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */ #define GIC_ICCIDR_IMPL_MASK (0xfff << GIC_ICCIDR_IMPL_SHIFT) -#define GIC_ICCIDR_REVISION_SHIFT (12) /* Bits 12-15: Revision number */ +#define GIC_ICCIDR_REVISION_SHIFT (12) /* Bits 12-15: Revision number */ #define GIC_ICCIDR_REVISION_MASK (15 << GIC_ICCIDR_REVISION_SHIFT) -#define GIC_ICCIDR_ARCHNO_SHIFT (16) /* Bits 16-19: Architecture number */ +#define GIC_ICCIDR_ARCHNO_SHIFT (16) /* Bits 16-19: Architecture number */ #define GIC_ICCIDR_ARCHNO_MASK (15 << GIC_ICCIDR_ARCHNO_SHIFT) -#define GIC_ICCIDR_PARTNO_SHIFT (20) /* Bits 20-31: Part number */ +#define GIC_ICCIDR_PARTNO_SHIFT (20) /* Bits 20-31: Part number */ #define GIC_ICCIDR_PARTNO_MASK (0xfff << GIC_ICCIDR_PARTNO_SHIFT) /* Distributor Registers */ /* Distributor Control Register */ -#define GIC_ICDDCR_NONSECENAB (1 << 0) /* Bit 0: Enable distributor for Non-secure interrupts */ -#define GIC_ICDDCR_SECENABLE (1 << 1) /* Bit 1: Enable distributor for Secure interrupts */ +#define GIC_ICDDCR_NONSECENAB (1 << 0) /* Bit 0: Enable distributor for Non-secure interrupts */ +#define GIC_ICDDCR_SECENABLE (1 << 1) /* Bit 1: Enable distributor for Secure interrupts */ /* Bits 2-31: Reserved */ /* Interrupt Controller Type Register */ -#define GIC_ICDICTR_ITLINES_SHIFT (0) /* Bits 0-4: It lines number */ +#define GIC_ICDICTR_ITLINES_SHIFT (0) /* Bits 0-4: It lines number */ #define GIC_ICDICTR_ITLINES_MASK (0x1f << GIC_ICDICTR_ITLINES_SHIFT) -#define GIC_ICDICTR_CPUNO_SHIFT (5) /* Bits 5-7: CPU number */ +#define GIC_ICDICTR_CPUNO_SHIFT (5) /* Bits 5-7: CPU number */ #define GIC_ICDICTR_CPUNO_MASK (7 << GIC_ICDICTR_CPUNO_SHIFT) /* Bits 8-9: Reserved */ -#define GIC_ICDICTR_SECEXTNS (1 << 10) /* Bit 10: Number of security domains */ -#define GIC_ICDICTR_LSPI_SHIFT (11) /* Bits 11-15: Number of Lockable Shared Peripheral Interrupts */ +#define GIC_ICDICTR_SECEXTNS (1 << 10) /* Bit 10: Number of security domains */ +#define GIC_ICDICTR_LSPI_SHIFT (11) /* Bits 11-15: Number of Lockable Shared Peripheral Interrupts */ #define GIC_ICDICTR_LSPI_MASK (0x1f << GIC_ICDICTR_LSPI_SHIFT) /* Bits 16-31: Reserved */ /* Distributor Implementer ID Register */ -#define GIC_ICDIIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */ +#define GIC_ICDIIDR_IMPL_SHIFT (0) /* Bits 0-11: Implementer */ #define GIC_ICDIIDR_IMPL_MASK (0xfff << GIC_ICDIIDR_IMPL_SHIFT) -#define GIC_ICDIIDR_REVISION_SHIFT (12) /* Bits 12-23: Revision number */ +#define GIC_ICDIIDR_REVISION_SHIFT (12) /* Bits 12-23: Revision number */ #define GIC_ICDIIDR_REVISION_MASK (0xfff << GIC_ICDIIDR_REVISION_SHIFT) -#define GIC_ICDIIDR_VERSION_SHIFT (24) /* Bits 24-31: Iimplementer version */ +#define GIC_ICDIIDR_VERSION_SHIFT (24) /* Bits 24-31: Iimplementer version */ #define GIC_ICDIIDR_VERSION_MASK (0xff << GIC_ICDIIDR_VERSION_SHIFT) /* Interrupt Security Registers: 0x0080-0x009c */ @@ -382,16 +387,16 @@ /* Interrupt Set-Enable. * - * NOTE: In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits - * in the ICDISERn are read as one, write ignored + * NOTE: In the Cortex-A9 MPCore, SGIs are always enabled. + * The corresponding bits in the ICDISERn are read as one, write ignored */ #define GIC_ICDISER_INT(n) GIC_MASK32(n) /* Interrupt Clear-Enable. * - * NOTE: In the Cortex-A9 MPCore, SGIs are always enabled. The corresponding bits - * in the ICDICERn are read as one, write ignored + * NOTE: In the Cortex-A9 MPCore, SGIs are always enabled. + * The corresponding bits in the ICDICERn are read as one, write ignored */ #define GIC_ICDICER_INT(n) GIC_MASK32(n) @@ -427,10 +432,10 @@ /* Interrupt Configuration Register */ -#define INT_ICDICFR_NN 0 /* Bit n: 0= N-N Model */ -#define INT_ICDICFR_1N 1 /* Bit n: 1= 1-N Model */ -#define INT_ICDICFR_LEVEL 0 /* Bit n+1: 0=Level sensitive */ -#define INT_ICDICFR_EDGE 2 /* Bit n+2: 1=Edge sensitive */ +#define INT_ICDICFR_NN 0 /* Bit n: 0= N-N Model */ +#define INT_ICDICFR_1N 1 /* Bit n: 1= 1-N Model */ +#define INT_ICDICFR_LEVEL 0 /* Bit n+1: 0=Level sensitive */ +#define INT_ICDICFR_EDGE 2 /* Bit n+2: 1=Edge sensitive */ #define GIC_ICDICFR_ID_SHIFT(n) GIC_SHIFT16(n) #define GIC_ICDICFR_ID_MASK(n) GIC_MASK16(n) @@ -438,12 +443,12 @@ /* PPI Status Register */ -#define GIC_ICDPPISR_PPI(n) (1 << ((n) + 11)) /* Bits 11-15: PPI(n) status, n=0-4 */ -#define GIC_ICDPPISR_GTM (1 << 11) /* Bit 11: PPI[0], Global Timer */ -#define GIC_ICDPPISR_NFIQ (1 << 12) /* Bit 12: PPI[1], FIQ, active low */ -#define GIC_ICDPPISR_PTM (1 << 13) /* Bit 13: PPI[2], Private Timer */ -#define GIC_ICDPPISR_PWDT (1 << 14) /* Bit 14: PPI[3], Private Watchdog */ -#define GIC_ICDPPISR_NIRQ (1 << 15) /* Bit 15: PPI[3], IRQ, active low */ +#define GIC_ICDPPISR_PPI(n) (1 << ((n) + 11)) /* Bits 11-15: PPI(n) status, n=0-4 */ +#define GIC_ICDPPISR_GTM (1 << 11) /* Bit 11: PPI[0], Global Timer */ +#define GIC_ICDPPISR_NFIQ (1 << 12) /* Bit 12: PPI[1], FIQ, active low */ +#define GIC_ICDPPISR_PTM (1 << 13) /* Bit 13: PPI[2], Private Timer */ +#define GIC_ICDPPISR_PWDT (1 << 14) /* Bit 14: PPI[3], Private Watchdog */ +#define GIC_ICDPPISR_NIRQ (1 << 15) /* Bit 15: PPI[3], IRQ, active low */ /* SPI Status Registers */ @@ -451,23 +456,23 @@ /* Software Generated Interrupt Register */ -#define GIC_ICDSGIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ +#define GIC_ICDSGIR_INTID_SHIFT (0) /* Bits 0-9: Interrupt ID */ #define GIC_ICDSGIR_INTID_MASK (0x3ff << GIC_ICDSGIR_INTID_SHIFT) #define GIC_ICDSGIR_INTID(n) ((uint32_t)(n) << GIC_ICDSGIR_INTID_SHIFT) /* Bits 10-15: Reserved */ -#define GIC_ICDSGIR_CPUTARGET_SHIFT (16) /* Bits 16-23: CPU target */ +#define GIC_ICDSGIR_CPUTARGET_SHIFT (16) /* Bits 16-23: CPU target */ #define GIC_ICDSGIR_CPUTARGET_MASK (0xff << GIC_ICDSGIR_CPUTARGET_SHIFT) #define GIC_ICDSGIR_CPUTARGET(n) ((uint32_t)(n) << GIC_ICDSGIR_CPUTARGET_SHIFT) /* Bits 26-31: Reserved */ -#define GIC_ICDSGIR_TGTFILTER_SHIFT (24) /* Bits 24-25: Target filter */ -#define GIC_ICDSGIR_TGTFILTER_MASK (3 << GIC_ICDSGIR_TGTFILTER_SHIFT) -#define GIC_ICDSGIR_TGTFILTER_LIST (0 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt sent to CPUs CPU target list */ -#define GIC_ICDSGIR_TGTFILTER_OTHER (1 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to all but requesting CPU */ -#define GIC_ICDSGIR_TGTFILTER_THIS (2 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to requesting CPU only */ +#define GIC_ICDSGIR_TGTFILTER_SHIFT (24) /* Bits 24-25: Target filter */ +#define GIC_ICDSGIR_TGTFILTER_MASK (3 << GIC_ICDSGIR_TGTFILTER_SHIFT) +#define GIC_ICDSGIR_TGTFILTER_LIST (0 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt sent to CPUs CPU target list */ +#define GIC_ICDSGIR_TGTFILTER_OTHER (1 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to all but requesting CPU */ +#define GIC_ICDSGIR_TGTFILTER_THIS (2 << GIC_ICDSGIR_TGTFILTER_SHIFT) /* Interrupt is sent to requesting CPU only */ /* Interrupt IDs ************************************************************/ @@ -498,32 +503,32 @@ * task management. */ -#define GIC_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */ -#define GIC_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */ -#define GIC_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */ -#define GIC_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */ -#define GIC_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */ -#define GIC_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */ -#define GIC_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */ -#define GIC_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */ -#define GIC_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */ -#define GIC_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */ -#define GIC_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */ -#define GIC_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */ -#define GIC_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */ -#define GIC_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */ -#define GIC_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */ -#define GIC_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */ +#define GIC_IRQ_SGI0 0 /* Software Generated Interrupt (SGI) 0 */ +#define GIC_IRQ_SGI1 1 /* Software Generated Interrupt (SGI) 1 */ +#define GIC_IRQ_SGI2 2 /* Software Generated Interrupt (SGI) 2 */ +#define GIC_IRQ_SGI3 3 /* Software Generated Interrupt (SGI) 3 */ +#define GIC_IRQ_SGI4 4 /* Software Generated Interrupt (SGI) 4 */ +#define GIC_IRQ_SGI5 5 /* Software Generated Interrupt (SGI) 5 */ +#define GIC_IRQ_SGI6 6 /* Software Generated Interrupt (SGI) 6 */ +#define GIC_IRQ_SGI7 7 /* Software Generated Interrupt (SGI) 7 */ +#define GIC_IRQ_SGI8 8 /* Software Generated Interrupt (SGI) 8 */ +#define GIC_IRQ_SGI9 9 /* Software Generated Interrupt (SGI) 9 */ +#define GIC_IRQ_SGI10 10 /* Software Generated Interrupt (SGI) 10 */ +#define GIC_IRQ_SGI11 11 /* Software Generated Interrupt (SGI) 11 */ +#define GIC_IRQ_SGI12 12 /* Software Generated Interrupt (SGI) 12 */ +#define GIC_IRQ_SGI13 13 /* Software Generated Interrupt (SGI) 13 */ +#define GIC_IRQ_SGI14 14 /* Software Generated Interrupt (SGI) 14 */ +#define GIC_IRQ_SGI15 15 /* Software Generated Interrupt (SGI) 15 */ -#define GIC_IRQ_GTM 27 /* Global Timer (GTM) PPI(0) */ -#define GIC_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(1) */ -#define GIC_IRQ_PTM 29 /* Private Timer (PTM) PPI(2) */ -#define GIC_IRQ_WDT 30 /* Watchdog Timer (WDT) PPI(3) */ -#define GIC_IRQ_IRQ 31 /* Interrupt Request (nIRQ) PPI(4) */ +#define GIC_IRQ_GTM 27 /* Global Timer (GTM) PPI(0) */ +#define GIC_IRQ_FIQ 28 /* Fast Interrupt Request (nFIQ) PPI(1) */ +#define GIC_IRQ_PTM 29 /* Private Timer (PTM) PPI(2) */ +#define GIC_IRQ_WDT 30 /* Watchdog Timer (WDT) PPI(3) */ +#define GIC_IRQ_IRQ 31 /* Interrupt Request (nIRQ) PPI(4) */ /* Shared Peripheral Interrupts (SPI) follow */ -#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */ +#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */ /**************************************************************************** * Public Function Prototypes @@ -659,7 +664,7 @@ int arm_pause_handler(int irq, FAR void *context, FAR void *arg); #ifdef __cplusplus } #endif -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_ARMV7R_HAVE_GICv2 */ -#endif /* __ARCH_ARM_SRC_ARMV7_R_GIC_H */ +#endif /* CONFIG_ARMV7R_HAVE_GICv2 */ +#endif /* __ARCH_ARM_SRC_ARMV7_R_GIC_H */ diff --git a/arch/arm/src/armv7-r/l2cc_pl310.h b/arch/arm/src/armv7-r/l2cc_pl310.h index 5fc6d9ce96..00c3e22e7f 100644 --- a/arch/arm/src/armv7-r/l2cc_pl310.h +++ b/arch/arm/src/armv7-r/l2cc_pl310.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/l2cc_pl310.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,7 +16,7 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2, * Technical Reference Manual, ARM DDI 0246F (ID011711), ARM @@ -25,9 +25,9 @@ #ifndef __ARCH_ARM_SRC_ARMV7_R_L2CC_PL310_H #define __ARCH_ARM_SRC_ARMV7_R_L2CC_PL310_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -37,10 +37,11 @@ #include "chip/chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* General Definitions **************************************************************/ + ****************************************************************************/ + +/* General Definitions ******************************************************/ #define PL310_CACHE_LINE_SIZE 32 @@ -50,7 +51,7 @@ # define PL310_NLOCKREGS 1 #endif -/* L2CC Register Offsets ************************************************************/ +/* L2CC Register Offsets ****************************************************/ #define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */ #define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */ @@ -86,13 +87,15 @@ #define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */ /* 0x0800-0x08fc Reserved */ -/* Data and Instruction Lockdown registers where n=0-7. The registers for n > 0 are - * implemented if the option pl310_LOCKDOWN_BY_MASTER is enabled. Otherwise, they are - * unused +/* Data and Instruction Lockdown registers where n=0-7. + * The registers for n > 0 are implemented if the option + * pl310_LOCKDOWN_BY_MASTER is enabled. + * Otherwise, they are unused */ #define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */ #define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */ + /* 0x0940-0x0f4c Reserved */ #ifdef CONFIG_PL310_LOCKDOWN_BY_LINE # define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */ @@ -108,7 +111,7 @@ /* 0x0f64-0x0f7c Reserved */ #define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */ -/* L2CC Register Addresses **********************************************************/ +/* L2CC Register Addresses **************************************************/ #define L2CC_IDR (L2CC_BASE+L2CC_IDR_OFFSET) #define L2CC_TYPR (L2CC_BASE+L2CC_TYPR_OFFSET) @@ -148,7 +151,7 @@ #define L2CC_PCR (L2CC_BASE+L2CC_PCR_OFFSET) #define L2CC_POWCR (L2CC_BASE+L2CC_POWCR_OFFSET) -/* L2CC Register Bit Definitions ****************************************************/ +/* L2CC Register Bit Definitions ********************************************/ /* Cache ID Register (32-bit ID) */ @@ -200,6 +203,7 @@ # define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */ # define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */ # define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */ + #define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */ #define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */ #define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */ @@ -241,13 +245,13 @@ /* Event Counter 1 Configuration Register */ - #define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */ #define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT) # define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */ # define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */ # define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */ # define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */ + #define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ #define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT) # define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */ @@ -275,6 +279,7 @@ # define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */ # define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */ # define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */ + #define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */ #define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT) # define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */ @@ -295,10 +300,11 @@ # define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */ /* Event Counter 1 Value Register (32-bit value) */ + /* Event Counter 0 Value Register (32-bit value) */ -/* Interrupt Mask Register, Masked Interrupt Status Register, Raw Interrupt Status - * Register, and Interrupt Clear Register. +/* Interrupt Mask Register, Masked Interrupt Status Register, + * Raw Interrupt Status Register, and Interrupt Clear Register. */ #define L2CC_INT_ECNTR (1 << 0) /* Bit 0: Event Counter 1/0 Overflow Increment */ diff --git a/arch/arm/src/armv7-r/mpcore.h b/arch/arm/src/armv7-r/mpcore.h index 18e02d4b54..85f8f7915c 100644 --- a/arch/arm/src/armv7-r/mpcore.h +++ b/arch/arm/src/armv7-r/mpcore.h @@ -30,7 +30,7 @@ * Included Files ****************************************************************************/ -#include "chip.h" /* For CHIP_MPCORE_VBASE */ +#include "chip.h" /* For CHIP_MPCORE_VBASE */ /**************************************************************************** * Pre-processor Definitions @@ -44,13 +44,15 @@ /* Peripheral Base Offsets **************************************************/ -#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */ -#define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt controller interface */ -#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */ +#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */ +#define MPCORE_ICC_OFFSET 0x2000 /* 0x0000-0x00FC Interrupt controller interface */ +#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */ + /* 0x0300-0x05ff Reserved */ -#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */ +#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */ + /* 0x0700-0x07ff Reserved */ -#define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */ +#define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */ /* Peripheral Base Addresses ************************************************/ @@ -60,4 +62,4 @@ #define MPCORE_PTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_PTM_OFFSET) #define MPCORE_ICD_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET) -#endif /* __ARCH_ARM_SRC_ARMV7_R_MPCORE_H */ +#endif /* __ARCH_ARM_SRC_ARMV7_R_MPCORE_H */ diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 00ca72b0c8..e4ccc98735 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -89,6 +89,7 @@ # define MPU_RACR_AP_RWRW (3 << MPU_RACR_AP_SHIFT) /* PL0:RW PL1:RW */ # define MPU_RACR_AP_RONO (5 << MPU_RACR_AP_SHIFT) /* PL0:RO PL1:None */ # define MPU_RACR_AP_RORO (6 << MPU_RACR_AP_SHIFT) /* PL0:RO PL1:RO */ + #define MPU_RACR_XN (1 << 12) /* Bit 12: Instruction access disable */ /* MPU Region Number Register */ @@ -160,8 +161,8 @@ uint8_t mpu_log2regionfloor(size_t size); * * Description: * Given (1) the offset to the beginning of valid data, (2) the size of the - * memory to be mapped and (2) the log2 size of the mapping to use, determine - * the minimal sub-region set to span that memory region. + * memory to be mapped and (2) the log2 size of the mapping to use, + * determine the minimal sub-region set to span that memory region. * * Assumption: * l2size has the same properties as the return value from @@ -509,8 +510,8 @@ static inline void mpu_priv_noncache(uintptr_t base, size_t size) MPU_RACR_XN; /* Instruction access disable */ mpu_set_dracr(regval); - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */ + regval = MPU_RASR_ENABLE | /* Enable region */ + MPU_RASR_RSIZE_LOG2((uint32_t)l2size) | /* Region size */ ((uint32_t)subregions << MPU_RASR_SRD_SHIFT); /* Sub-regions */ mpu_set_drsr(regval); } diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h index a458852b19..d5b6039ce9 100644 --- a/arch/arm/src/armv7-r/sctlr.h +++ b/arch/arm/src/armv7-r/sctlr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/sctlr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,27 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ /* References: * - * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright - * 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414) + * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", + * Copyright 1996-1998, 2000, 2004-2012 ARM. + * All rights reserved. ARM DDI 0406C.c (ID051414) */ #ifndef __ARCH_ARM_SRC_ARMV7_R_SCTLR_H #define __ARCH_ARM_SRC_ARMV7_R_SCTLR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* CP15 c0 Registers ****************************************************************/ + ****************************************************************************/ + +/* CP15 c0 Registers ********************************************************/ /* Main ID Register (MIDR): CRn=c0, opc1=0, CRm=c0, opc2=0 * TODO: To be provided @@ -77,26 +79,38 @@ * TODO: To be provided */ -/* Memory Model Features Register 0 (ID_MMFR0): CRn=c0, opc1=0, CRm=c1, opc2=4 - * Memory Model Features Register 1 (ID_MMFR1): CRn=c0, opc1=0, CRm=c1, opc2=5 - * Memory Model Features Register 2 (ID_MMFR2): CRn=c0, opc1=0, CRm=c1, opc2=6 - * Memory Model Features Register 3 (ID_MMFR3): CRn=c0, opc1=0, CRm=c1, opc2=7 +/* Memory Model Features Register 0 (ID_MMFR0): + * CRn=c0, opc1=0, CRm=c1, opc2=4 + * Memory Model Features Register 1 (ID_MMFR1): + * CRn=c0, opc1=0, CRm=c1, opc2=5 + * Memory Model Features Register 2 (ID_MMFR2): + * CRn=c0, opc1=0, CRm=c1, opc2=6 + * Memory Model Features Register 3 (ID_MMFR3): + * CRn=c0, opc1=0, CRm=c1, opc2=7 * TODO: To be provided */ -/* Instruction Set Attributes Register 0 (ID_ISAR0): CRn=c0, opc1=0, CRm=c2, opc2=0 - * Instruction Set Attributes Register 1 (ID_ISAR1): CRn=c0, opc1=0, CRm=c2, opc2=1 - * Instruction Set Attributes Register 2 (ID_ISAR2): CRn=c0, opc1=0, CRm=c2, opc2=2 - * Instruction Set Attributes Register 3 (ID_ISAR3): CRn=c0, opc1=0, CRm=c2, opc2=3 - * Instruction Set Attributes Register 4 (ID_ISAR4): CRn=c0, opc1=0, CRm=c2, opc2=4 - * Instruction Set Attributes Register 5 (ID_ISAR5): CRn=c0, opc1=0, CRm=c2, opc2=5 - * Instruction Set Attributes Register 6-7 (ID_ISAR6-7). Reserved. +/* Instruction Set Attributes Register 0 (ID_ISAR0): + * CRn=c0, opc1=0, CRm=c2, opc2=0 + * Instruction Set Attributes Register 1 (ID_ISAR1): + * CRn=c0, opc1=0, CRm=c2, opc2=1 + * Instruction Set Attributes Register 2 (ID_ISAR2): + * CRn=c0, opc1=0, CRm=c2, opc2=2 + * Instruction Set Attributes Register 3 (ID_ISAR3): + * CRn=c0, opc1=0, CRm=c2, opc2=3 + * Instruction Set Attributes Register 4 (ID_ISAR4): + * CRn=c0, opc1=0, CRm=c2, opc2=4 + * Instruction Set Attributes Register 5 (ID_ISAR5): + * CRn=c0, opc1=0, CRm=c2, opc2=5 + * Instruction Set Attributes Register 6-7 (ID_ISAR6-7). + * Reserved. * TODO: Others to be provided */ /* Reserved: CRn=c0, opc1=0, CRm=c3-c7, opc2=* */ -/* Cache Size Identification Register (CCSIDR): CRn=c0, opc1=1, CRm=c0, opc2=0 +/* Cache Size Identification Register (CCSIDR): + * CRn=c0, opc1=1, CRm=c0, opc2=0 * TODO: To be provided */ @@ -112,7 +126,8 @@ * TODO: To be provided */ -/* CP15 c1 Registers ****************************************************************/ +/* CP15 c1 Registers ********************************************************/ + /* System Control Register (SCTLR): CRn=c1, opc1=0, CRm=c0, opc2=0 */ @@ -147,14 +162,17 @@ * Implementation defined */ -/* Coprocessor Access Control Register (CPACR): CRn=c1, opc1=0, CRm=c0, opc2=2 +/* Coprocessor Access Control Register (CPACR): + * CRn=c1, opc1=0, CRm=c0, opc2=2 * TODO: To be provided */ -/* CP15 c2-c4 Registers *************************************************************/ +/* CP15 c2-c4 Registers *****************************************************/ + /* Not used on ARMv7-R */ -/* CP15 c5 Registers ****************************************************************/ +/* CP15 c5 Registers ********************************************************/ + /* Data Fault Status Register (DFSR): CRn=c5, opc1=0, CRm=c0, opc2=0 * TODO: To be provided */ @@ -171,7 +189,7 @@ * TODO: To be provided */ -/* CP15 c6 Registers ****************************************************************/ +/* CP15 c6 Registers ********************************************************/ /* Data Fault Address Register(DFAR): CRn=c6, opc1=0, CRm=c0, opc2=0 * @@ -180,46 +198,56 @@ /* Instruction Fault Address Register(IFAR): CRn=c6, opc1=0, CRm=c0, opc2=1 * - * Holds the MVA of the faulting address of the instruction that caused a prefetch - * abort. + * Holds the MVA of the faulting address of the instruction that caused a + * prefetch abort. */ /* Data Region Base Address Register (DRBAR): CRn=c6, opc1=0, CRm=c1, opc2=0 * TODO: To be provided */ -/* Instruction Region Base Address Register (IRBAR): CRn=c6, opc1=0, CRm=c1, opc2=1 +/* Instruction Region Base Address Register (IRBAR): + * CRn=c6, opc1=0, CRm=c1, opc2=1 * TODO: To be provided */ -/* Data Region Size and Enable Register (DRSR): CRn=c6, opc1=0, CRm=c1, opc2=2 +/* Data Region Size and Enable Register (DRSR): + * CRn=c6, opc1=0, CRm=c1, opc2=2 * TODO: To be provided */ -/* Instruction Region Size and Enable Register (IRSR): CRn=c6, opc1=0, CRm=c1, opc2=3 +/* Instruction Region Size and Enable Register (IRSR): + * CRn=c6, opc1=0, CRm=c1, opc2=3 * TODO: To be provided */ -/* Data Region Access Control Register (DRACR): CRn=c6, opc1=0, CRm=c1, opc2=4 +/* Data Region Access Control Register (DRACR): + * CRn=c6, opc1=0, CRm=c1, opc2=4 * TODO: To be provided */ -/* Instruction Region Access Control Register (IRACR): CRn=c6, opc1=0, CRm=c1, opc2=5 +/* Instruction Region Access Control Register (IRACR): + * CRn=c6, opc1=0, CRm=c1, opc2=5 * TODO: To be provided */ -/* MPU Region Number Register (RGNR): CRn=c6, opc1=0, CRm=c2, opc2=0 +/* MPU Region Number Register (RGNR): + * CRn=c6, opc1=0, CRm=c2, opc2=0 * TODO: To be provided */ -/* CP15 c7 Registers ****************************************************************/ +/* CP15 c7 Registers ********************************************************/ + /* See cp15_cacheops.h */ -/* CP15 c8 Registers ****************************************************************/ +/* CP15 c8 Registers ********************************************************/ + /* Not used on ARMv7-R */ -/* CP15 c9 Registers ****************************************************************/ -/* 32-bit Performance Monitors Control Register (PMCR): CRn=c9, opc1=0, CRm=c12, opc2=0 +/* CP15 c9 Registers ********************************************************/ + +/* 32-bit Performance Monitors Control Register (PMCR): + * CRn=c9, opc1=0, CRm=c12, opc2=0 * TODO: To be provided */ @@ -236,68 +264,84 @@ #define PCMR_IMP_SHIFT (24) /* Bits 24-31: Implementer code */ #define PCMR_IMP_MASK (0xff << PCMR_IMP_SHIFT) -/* 32-bit Performance Monitors Count Enable Set register (PMCNTENSET): CRn=c9, opc1=0, CRm=c12, opc2=1 +/* 32-bit Performance Monitors Count Enable Set register (PMCNTENSET): + * CRn=c9, opc1=0, CRm=c12, opc2=1 * TODO: To be provided */ -/* 32-bit Performance Monitors Count Enable Clear register (PMCNTENCLR): CRn=c9, opc1=0, CRm=c12, opc2=2 +/* 32-bit Performance Monitors Count Enable Clear register (PMCNTENCLR): + * CRn=c9, opc1=0, CRm=c12, opc2=2 * TODO: To be provided */ -/* 32-bit Performance Monitors Overflow Flag Status Register (PMOVSR): CRn=c9, opc1=0, CRm=c12, opc2=3 +/* 32-bit Performance Monitors Overflow Flag Status Register (PMOVSR): + * CRn=c9, opc1=0, CRm=c12, opc2=3 * TODO: To be provided */ -/* 32-bit Performance Monitors Software Increment register (PMSWINC): CRn=c9, opc1=0, CRm=c12, opc2=4 +/* 32-bit Performance Monitors Software Increment register (PMSWINC): + * CRn=c9, opc1=0, CRm=c12, opc2=4 * TODO: To be provided */ -/* 32-bit Performance Monitors Event Counter Selection Register (PMSELR): CRn=c9, opc1=0, CRm=c12, opc2=5 +/* 32-bit Performance Monitors Event Counter Selection Register (PMSELR): + * CRn=c9, opc1=0, CRm=c12, opc2=5 * TODO: To be provided */ -/* 32-bit Performance Monitors Common Event Identification (PMCEID0): CRn=c9, opc1=0, CRm=c12, opc2=6 +/* 32-bit Performance Monitors Common Event Identification (PMCEID0): + * CRn=c9, opc1=0, CRm=c12, opc2=6 * TODO: To be provided */ -/* 32-bit Performance Monitors Common Event Identification (PMCEID1): CRn=c9, opc1=0, CRm=c12, opc2=7 +/* 32-bit Performance Monitors Common Event Identification (PMCEID1): + * CRn=c9, opc1=0, CRm=c12, opc2=7 * TODO: To be provided */ -/* 32-bit Performance Monitors Cycle Count Register (PMCCNTR): CRn=c9, opc1=0, CRm=c13, opc2=0 +/* 32-bit Performance Monitors Cycle Count Register (PMCCNTR): + * CRn=c9, opc1=0, CRm=c13, opc2=0 * TODO: To be provided */ -/* 32-bit Performance Monitors Event Type Select Register (PMXEVTYPER): CRn=c9, opc1=0, CRm=c13, opc2=1 +/* 32-bit Performance Monitors Event Type Select Register (PMXEVTYPER): + * CRn=c9, opc1=0, CRm=c13, opc2=1 * TODO: To be provided */ -/* 32-bit Performance Monitors Event Count Register (PMXEVCNTR): CRn=c9, opc1=0, CRm=c13, opc2=2 +/* 32-bit Performance Monitors Event Count Register (PMXEVCNTR): + * CRn=c9, opc1=0, CRm=c13, opc2=2 * TODO: To be provided */ -/* 32-bit Performance Monitors User Enable Register (PMUSERENR): CRn=c9, opc1=0, CRm=c14, opc2=0 +/* 32-bit Performance Monitors User Enable Register (PMUSERENR): + * CRn=c9, opc1=0, CRm=c14, opc2=0 * TODO: To be provided */ -/* 32-bit Performance Monitors Interrupt Enable Set register (PMINTENSET): CRn=c9, opc1=0, CRm=c14, opc2=1 +/* 32-bit Performance Monitors Interrupt Enable Set register (PMINTENSET): + * CRn=c9, opc1=0, CRm=c14, opc2=1 * TODO: To be provided */ -/* 32-bit Performance Monitors Interrupt Enable Clear register (PMINTENCLR): CRn=c9, opc1=0, CRm=c14, opc2=2 +/* 32-bit Performance Monitors Interrupt Enable Clear register (PMINTENCLR): + * CRn=c9, opc1=0, CRm=c14, opc2=2 * TODO: To be provided */ -/* CP15 c10 Registers ***************************************************************/ +/* CP15 c10 Registers *******************************************************/ + /* Not used on ARMv7-R */ -/* CP15 c11 Registers ***************************************************************/ +/* CP15 c11 Registers *******************************************************/ + /* Reserved for implementation defined DMA functions */ -/* CP15 c12 Registers ***************************************************************/ +/* CP15 c12 Registers *******************************************************/ + /* Not used on ARMv7-R */ -/* CP15 c13 Registers ***************************************************************/ +/* CP15 c13 Registers *******************************************************/ /* Context ID Register (CONTEXTIDR): CRn=c13, opc1=0, CRm=c0, opc2=1 * 32-Bit ContextID value. @@ -315,7 +359,7 @@ * TODO: To be provided */ -/* CP15 c14 Registers ***************************************************************/ +/* CP15 c14 Registers *******************************************************/ /* Counter Frequency register (CNTFRQ): CRn=c14, opc1=0, CRm=c0, opc2=0 * TODO: To be provided @@ -325,11 +369,13 @@ * TODO: To be provided */ -/* PL1 Physical TimerValue register (CNTP_TVAL): CRn=c14, opc1=0, CRm=c2, opc2=0 +/* PL1 Physical TimerValue register (CNTP_TVAL): + * CRn=c14, opc1=0, CRm=c2, opc2=0 * TODO: To be provided */ -/* PL1 Physical Timer Control register (CNTP_CTL): CRn=c14, opc1=0, CRm=c2, opc2=0 +/* PL1 Physical Timer Control register (CNTP_CTL): + * CRn=c14, opc1=0, CRm=c2, opc2=0 * TODO: To be provided */ @@ -349,20 +395,23 @@ * TODO: To be provided */ -/* PL1 Physical Timer CompareValue register (CNTP_CVAL): CRn=c14, opc1=2, CRm=c14, opc2=n +/* PL1 Physical Timer CompareValue register (CNTP_CVAL): + * CRn=c14, opc1=2, CRm=c14, opc2=n * TODO: To be provided */ -/* Virtual Timer CompareValue register (CNTV_CVAL): CRn=c14, opc1=3, CRm=c14, opc2=n +/* Virtual Timer CompareValue register (CNTV_CVAL): + * CRn=c14, opc1=3, CRm=c14, opc2=n * TODO: To be provided */ -/* CP15 c15 Registers ***************************************************************/ +/* CP15 c15 Registers *******************************************************/ + /* Implementation defined */ -/************************************************************************************ +/**************************************************************************** * Assembly Macros - ************************************************************************************/ + ****************************************************************************/ #ifdef __ASSEMBLY__ @@ -391,9 +440,9 @@ .endm #endif /* __ASSEMBLY__ */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/arm/src/armv7-r/svcall.h b/arch/arm/src/armv7-r/svcall.h index 51a5d26c01..0b9a049995 100644 --- a/arch/arm/src/armv7-r/svcall.h +++ b/arch/arm/src/armv7-r/svcall.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/armv7-r/svcall.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_ARMV7_R_SVCALL_H #define __ARCH_ARM_SRC_ARMV7_R_SVCALL_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -33,14 +33,15 @@ #ifdef CONFIG_LIB_SYSCALL -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ -/* This logic uses one system call for the syscall return. So a minimum of one - * syscall values must be reserved. If CONFIG_BUILD_PROTECTED is defined, then four +/* This logic uses one system call for the syscall return. + * So a minimum of one syscall values must be reserved. + * If CONFIG_BUILD_PROTECTED is defined, then four * more syscall values must be reserved. */ @@ -58,7 +59,7 @@ # endif #endif -/* Cortex-R system calls ************************************************************/ +/* Cortex-R system calls ****************************************************/ /* SYS call 0: * @@ -93,7 +94,8 @@ /* SYS call 4: * - * void signal_handler(_sa_sigaction_t sighand, int signo, FAR siginfo_t *info, + * void signal_handler(_sa_sigaction_t sighand, int signo, + * FAR siginfo_t *info, * FAR void *ucontext); */ @@ -108,9 +110,9 @@ #endif /* CONFIG_BUILD_PROTECTED */ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #endif /* CONFIG_LIB_SYSCALL */ #endif /* __ARCH_ARM_SRC_ARMV7_R_SVCALL_H */