Revert "STM32 serial: Make input hardware flow-control work with RX DMA. From Jussi Kivilinna"
This reverts commit 265af481209d60033f7cd4c4216048b1ce3eb435. Conflicts: arch/arm/src/stm32/stm32_serial.c
This commit is contained in:
David Sidrane
parent
8b81cf5c7e
commit
df9ae3c13f
@ -208,7 +208,7 @@
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# error "Unknown STM32 DMA"
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# endif
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/* DMA control words */
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/* DMA control word */
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# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define SERIAL_DMA_CONTROL_WORD \
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@ -220,16 +220,6 @@
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CONFIG_USART_DMAPRIO | \
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DMA_SCR_PBURST_SINGLE | \
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DMA_SCR_MBURST_SINGLE)
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# ifdef CONFIG_SERIAL_IFLOWCONTROL
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# define SERIAL_DMA_IFLOW_CONTROL_WORD \
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(DMA_SCR_DIR_P2M | \
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DMA_SCR_MINC | \
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DMA_SCR_PSIZE_8BITS | \
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DMA_SCR_MSIZE_8BITS | \
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CONFIG_USART_DMAPRIO | \
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DMA_SCR_PBURST_SINGLE | \
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DMA_SCR_MBURST_SINGLE)
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# endif
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# else
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# define SERIAL_DMA_CONTROL_WORD \
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(DMA_CCR_CIRC | \
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@ -237,13 +227,6 @@
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DMA_CCR_PSIZE_8BITS | \
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DMA_CCR_MSIZE_8BITS | \
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CONFIG_USART_DMAPRIO)
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# ifdef CONFIG_SERIAL_IFLOWCONTROL
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# define SERIAL_DMA_IFLOW_CONTROL_WORD \
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(DMA_CCR_MINC | \
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DMA_CCR_PSIZE_8BITS | \
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DMA_CCR_MSIZE_8BITS | \
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CONFIG_USART_DMAPRIO)
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# endif
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# endif
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#endif
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@ -1608,28 +1591,13 @@ static int up_dma_setup(struct uart_dev_s *dev)
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priv->rxdma = stm32_dmachannel(priv->rxdma_channel);
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow)
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{
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/* Configure for non-circular DMA reception into the RX FIFO */
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/* Configure for circular DMA reception into the RX fifo */
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stm32_dmasetup(priv->rxdma,
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priv->usartbase + STM32_USART_RDR_OFFSET,
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(uint32_t)priv->rxfifo,
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RXDMA_BUFFER_SIZE,
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SERIAL_DMA_IFLOW_CONTROL_WORD);
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}
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else
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#endif
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{
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/* Configure for circular DMA reception into the RX FIFO */
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stm32_dmasetup(priv->rxdma,
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priv->usartbase + STM32_USART_RDR_OFFSET,
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(uint32_t)priv->rxfifo,
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RXDMA_BUFFER_SIZE,
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SERIAL_DMA_CONTROL_WORD);
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}
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stm32_dmasetup(priv->rxdma,
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priv->usartbase + STM32_USART_RDR_OFFSET,
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(uint32_t)priv->rxfifo,
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RXDMA_BUFFER_SIZE,
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SERIAL_DMA_CONTROL_WORD);
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/* Reset our DMA shadow pointer to match the address just
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* programmed above.
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@ -1643,26 +1611,12 @@ static int up_dma_setup(struct uart_dev_s *dev)
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regval |= USART_CR3_DMAR;
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up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow)
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{
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/* Start the DMA channel, and arrange for callbacks at the full point
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* in the FIFO. After buffer gets full, hardware flow-control kicks
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* in and DMA transfer is stopped.
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*/
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/* Start the DMA channel, and arrange for callbacks at the half and
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* full points in the FIFO. This ensures that we have half a FIFO
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* worth of time to claim bytes before they are overwritten.
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*/
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stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, false);
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}
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else
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#endif
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{
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/* Start the DMA channel, and arrange for callbacks at the half and
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* full points in the FIFO. This ensures that we have half a FIFO
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* worth of time to claim bytes before they are overwritten.
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*/
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stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
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}
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stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
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return OK;
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}
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@ -1817,7 +1771,7 @@ static void up_detach(struct uart_dev_s *dev)
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* interrupt received on the 'irq' It should call uart_transmitchars or
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* uart_receivechar to perform the appropriate data transfers. The
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* interrupt handling logic must be able to map the 'irq' number into the
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* appropriate uart_dev_s structure in order to call these functions.
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* approprite uart_dev_s structure in order to call these functions.
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*
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****************************************************************************/
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@ -2316,9 +2270,9 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
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unsigned int nbuffered, bool upper)
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{
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struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
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uint16_t ie;
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#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
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defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
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#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
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if (priv->iflow && (priv->rts_gpio != 0))
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{
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/* Assert/de-assert nRTS set it high resume/stop sending */
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@ -2346,7 +2300,9 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
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* enable Rx interrupts.
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*/
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uart_disablerxint(dev);
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ie = priv->ie;
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ie &= ~USART_CR1_RXNEIE;
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up_restoreusartint(priv, ie);
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return true;
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}
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@ -2359,7 +2315,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
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* received.
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*/
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uart_enablerxint(dev);
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up_rxint(dev, true);
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}
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}
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#endif
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@ -2391,18 +2347,7 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
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priv->rxdmanext++;
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if (priv->rxdmanext == RXDMA_BUFFER_SIZE)
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{
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow)
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{
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/* RX DMA buffer full. RX paused, RTS line pulled up to prevent
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* more input data from other end.
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*/
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}
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else
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#endif
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{
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priv->rxdmanext = 0;
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}
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priv->rxdmanext = 0;
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}
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}
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@ -2410,40 +2355,6 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
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}
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#endif
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/****************************************************************************
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* Name: up_dma_reenable
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*
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* Description:
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* Call to re-enable RX DMA.
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*
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****************************************************************************/
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#if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL)
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static void up_dma_reenable(struct up_dev_s *priv)
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{
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/* Configure for non-circular DMA reception into the RX fifo */
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stm32_dmasetup(priv->rxdma,
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priv->usartbase + STM32_USART_RDR_OFFSET,
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(uint32_t)priv->rxfifo,
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RXDMA_BUFFER_SIZE,
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SERIAL_DMA_IFLOW_CONTROL_WORD);
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/* Reset our DMA shadow pointer to match the address just
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* programmed above.
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*/
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priv->rxdmanext = 0;
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/* Start the DMA channel, and arrange for callbacks at the full point in
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* the FIFO. After buffer gets full, hardware flow-control kicks in and
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* DMA transfer is stopped.
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*/
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stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, false);
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}
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#endif
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/****************************************************************************
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* Name: up_dma_rxint
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*
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@ -2466,15 +2377,6 @@ static void up_dma_rxint(struct uart_dev_s *dev, bool enable)
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*/
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priv->rxenable = enable;
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow && priv->rxenable && (priv->rxdmanext == RXDMA_BUFFER_SIZE))
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{
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/* Re-enable RX DMA. */
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up_dma_reenable(priv);
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}
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#endif
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}
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#endif
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@ -2510,14 +2412,10 @@ static bool up_dma_rxavailable(struct uart_dev_s *dev)
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static void up_send(struct uart_dev_s *dev, int ch)
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{
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struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
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#ifdef HAVE_RS485
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if (priv->rs485_dir_gpio != 0)
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{
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stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
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}
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stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
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#endif
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up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch);
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}
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@ -2683,16 +2581,6 @@ static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
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if (priv->rxenable && up_dma_rxavailable(&priv->dev))
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{
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uart_recvchars(&priv->dev);
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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if (priv->iflow && priv->rxenable &&
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(priv->rxdmanext == RXDMA_BUFFER_SIZE))
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{
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/* Re-enable RX DMA. */
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up_dma_reenable(priv);
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}
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#endif
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}
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}
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#endif
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@ -2707,7 +2595,7 @@ static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
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* Input Parameters:
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*
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* cb - Returned to the driver. The driver version of the callback
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* structure may include additional, driver-specific state data at
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* strucure may include additional, driver-specific state data at
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* the end of the structure.
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*
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* pmstate - Identifies the new PM state
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@ -2773,7 +2661,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
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* Input Parameters:
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*
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* cb - Returned to the driver. The driver version of the callback
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* structure may include additional, driver-specific state data at
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* strucure may include additional, driver-specific state data at
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* the end of the structure.
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*
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* pmstate - Identifies the new PM state
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@ -2791,6 +2679,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
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* return non-zero values when reverting back to higher power
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* consumption modes!
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*
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*
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****************************************************************************/
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#ifdef CONFIG_PM
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