arch/arm/src/tiva/hardware: Add CC13x0, CC13x2, and cc6x2 DDI header file.
This commit is contained in:
Gregory Nutt
parent
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commit
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223
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h
Normal file
223
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h
Normal file
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/****************************************************************************
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* arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI_H
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/****************************************************************************
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* This file contains macros for controlling the DDI master and
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* accessing DDI Slave registers via the DDI Master.
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*
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* There are 3 categories of macros in this file:
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* - macros that provide an offsets to and addresses of a register located
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* within the DDI Master itself.
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* - macros that define bits or bitfields within the DDI Master Registers.
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* - macros that provide an "instruction offset" that are used when
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* accessing a DDI Slave.
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*
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* The macros that that provide DDI Master register offsets and define bits
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* and bitfields for those registers are the typical macros that appear in
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* most register definition header files. In the following example
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* TIVA_DDI_CFG_OFFSET is a macro for a register offset, TIVA_DDI_CFG is
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* the corresponding macro for a register address, and DDI_CFG_WAITFORACK
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* is a macro for a bit in that register. This example code will set the
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* WAITFORACK bit in register TVIA_DDI_CFG of the DDI Master. (Note: this
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* access the Master not the Slave).
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*
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* uint32_t regval;
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* regval = getreg32(TIVA_DDI_CFG);
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* regval |= DDI_CFG_WAITFORACK
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* putreg32(regval, TIVA_DDI_CFG);
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*
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* The "instruction offset" macros are used to pass an instruction to
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* the DDI Master when accessing DDI slave registers. These macros are
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* only used when accessing DDI Slave Registers. (Remember DDI
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* Master Registers are accessed normally).
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*
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* The instructions supported when accessing a DDI Slave Register follow:
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* - Direct Access to a DDI Slave register. I.e. read or write the
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* register.
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* - Set the specified bits in a DDI Slave register.
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* - Clear the specified bits in a DDI Slave register.
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* - Mask write of 4 bits to the a DDI Slave register.
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* - Mask write of 8 bits to the a DDI Slave register.
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* - Mask write of 16 bits to the a DDI Slave register.
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*
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* Note: only the "Direct Access" offset should be used when reading
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* a DDI Slave register. Only 8- and 16-bit reads are supported.
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*
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* The generic format of using this marcos for a read follows:
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*
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* - Read low 16-bits in DDI_SLAVE_OFF
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*
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* myushortvar = getreg16(TIVA_DDI_DIR + DDI_SLAVE_OFF);
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*
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* - Read high 16-bits in DDI_SLAVE_OFF add 2 for data[31:16]
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*
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* myushortvar = getreg16(TIVA_DDI_DIR + DDI_SLAVE_OFF + 2);
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*
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* - Read data[31:24] byte in DDI_SLAVE_OFF add 3 for data[31:24]
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*
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* myuchar = getreg9(TIVA_DDI_DIR + DDI_SLAVE_OFF + 3);
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*
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* Notes: In the above example:
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*
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* - Where TIVA_DDI_DIR is address of the of the Direct Access
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* instruction.
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* - DDI_SLAVE_OFF is the DDI Slave offset defined in the
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* cc13x2_cc25x2_<ddi_slave>.h header file (e.g.
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* cc13x2_cc25x2_osc_top.h for the OSCSC oscillator modules.
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*
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* Writes can use any of the "instruction macros".
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* The following examples do a "direct write" to DDI Slave register
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* DDI_SLAVE_OFF using different size operands:
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*
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* DIRECT WRITES
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* - Write 32-bits aligned
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*
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* putreg32(0x12345678, TIVA_DDI_DIR + DDI_SLAVE_OFF);
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*
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* - Write 16-bits aligned to high 16-bits then low 16-bits
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* Add 2 to get to high 16-bits.
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*
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* putreg16(0xabcd, TIVA_DDI_DIR + DDI_SLAVE_OFF + 2);
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* putreg16(0xef01, TIVA_DDI_DIR + DDI_SLAVE_OFF);
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*
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* - Write each byte at DDI_SLAVE_OFF, one at a time.
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* Add 1,2,or 3 to get to bytes 1,2, or 3.
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*
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF) = 0x33;
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF + 1) = 0x44;
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF + 2) = 0x55;
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF + 3) = 0x66;
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*
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* SET/CLR
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*
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* The set and clear functions behave similarly to each other. Each
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* can be performed on an 8-, 16-, or 32-bit operand.
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* Examples follow:
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*
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* - Set all odd bits in a 32-bit words
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*
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* putreg32(0xaaaaaaaa, TIVA_DDI_SET + DDI_SLAVE_OFF);
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*
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* - Clear all bits in byte 2 (data[23:16]) using 32-bit operand
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*
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* putreg32(0x00ff0000, TIVA_DDI_CLR + DDI_SLAVE_OFF);
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*
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* - Set even bits in byte 2 (data[23:16]) using 8-bit operand
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*
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* putreg8(0x55, TIVA_DDI_CLR + DDI_SLAVE_OFF + 2);
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*
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* MASKED WRITES
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*
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* The mask writes are a bit different. They operate on nibbles,
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* bytes, and 16-bit elements. Two operands are required; a 'mask'
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* and 'data'; The operands are concatenated and written to the master.
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* e.g. the mask and data are combined as follows for a 16 bit masked
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* write: (mask << 16) | data; Examples follow:
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*
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* - Write 5555 to low 16-bits of DDI_SLAVE_OFF register
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* a long write is needed (32-bits).
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*
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* putreg32(0xffff5555, TIVA_DDI_MASK16B + DDI_SLAVE_OFF);
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*
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* - Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register
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* Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff!
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*
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* putreg32(0x01ff01aa, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 4);
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*
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* - Do an 8 bit masked write of 00 to low byte of register (data[7:0]).
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* a short write is needed (16-bits).
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*
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* putreg16(0xff00, TIVA_DDI_MASK16B + DDI_SLAVE_OFF);
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*
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* - Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]).
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* add 2 to get to byte 1.
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*
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* putreg16(0xff11, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 2);
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*
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* - Do an 8 bit masked write of 33 to high byte of register (data[31:24]).
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* add 6 to get to byte 3.
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*
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* putreg16(0xff33, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 6);
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*
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* - Do an 4 bit masked write (Nibble) of 7 to data[3:0]).
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* Byte write is needed.
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*
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* putreg8(0xf7, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + DDI_MASK16B_OFFSET);
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*
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* - Do an 4 bit masked write of 4 to data[7:4]).
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* Add 1 for next nibble
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*
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* putreg8(0xf4, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 1);
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/tiva_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* DDI Register Offsets *****************************************************/
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#define TIVA_DDI_DIR_OFFSET 0x0000 /* Offset for the direct access instruction */
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#define TIVA_DDI_SET_OFFSET 0x0040 /* Offset for 'Set' instruction */
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#define TIVA_DDI_CLR_OFFSET 0x0080 /* Offset for 'Clear' instruction */
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#define TIVA_DDI_MASK4B_OFFSET 0x0100 /* Offset for 4-bit masked access */
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#define TIVA_DDI_MASK8B_OFFSET 0x0180 /* Offset for 8-bit masked access */
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#define TIVA_DDI_MASK16B_OFFSET 0x0200 /* Offset for 16-bit masked access */
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/* DDI Register Addresses ***************************************************/
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#define TIVA_DDI_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET)
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#define TIVA_DDI_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET)
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#define TIVA_DDI_CLR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_CLR_OFFSET)
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#define TIVA_DDI_MASK4B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET)
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#define TIVA_DDI_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET)
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#define TIVA_DDI_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET)
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#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI_H */
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223
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi.h
Normal file
223
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi.h
Normal file
@ -0,0 +1,223 @@
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/****************************************************************************
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* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Technical content derives from a TI header file that has a compatible BSD license:
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*
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* Copyright (c) 2015-2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI_H
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#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI_H
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/****************************************************************************
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* This file contains macros for controlling the DDI master and
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* accessing DDI Slave registers via the DDI Master.
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*
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* There are 3 categories of macros in this file:
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* - macros that provide an offsets to and addresses of a register located
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* within the DDI Master itself.
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* - macros that define bits or bitfields within the DDI Master Registers.
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* - macros that provide an "instruction offset" that are used when
|
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* accessing a DDI Slave.
|
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*
|
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* The macros that that provide DDI Master register offsets and define bits
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* and bitfields for those registers are the typical macros that appear in
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* most register definition header files. In the following example
|
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* TIVA_DDI_CFG_OFFSET is a macro for a register offset, TIVA_DDI_CFG is
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* the corresponding macro for a register address, and DDI_CFG_WAITFORACK
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* is a macro for a bit in that register. This example code will set the
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* WAITFORACK bit in register TVIA_DDI_CFG of the DDI Master. (Note: this
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* access the Master not the Slave).
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*
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* uint32_t regval;
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* regval = getreg32(TIVA_DDI_CFG);
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* regval |= DDI_CFG_WAITFORACK
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* putreg32(regval, TIVA_DDI_CFG);
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*
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* The "instruction offset" macros are used to pass an instruction to
|
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* the DDI Master when accessing DDI slave registers. These macros are
|
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* only used when accessing DDI Slave Registers. (Remember DDI
|
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* Master Registers are accessed normally).
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*
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* The instructions supported when accessing a DDI Slave Register follow:
|
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* - Direct Access to a DDI Slave register. I.e. read or write the
|
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* register.
|
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* - Set the specified bits in a DDI Slave register.
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* - Clear the specified bits in a DDI Slave register.
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* - Mask write of 4 bits to the a DDI Slave register.
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* - Mask write of 8 bits to the a DDI Slave register.
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* - Mask write of 16 bits to the a DDI Slave register.
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*
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* Note: only the "Direct Access" offset should be used when reading
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* a DDI Slave register. Only 8- and 16-bit reads are supported.
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*
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* The generic format of using this marcos for a read follows:
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*
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* - Read low 16-bits in DDI_SLAVE_OFF
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*
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* myushortvar = getreg16(TIVA_DDI_DIR + DDI_SLAVE_OFF);
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*
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* - Read high 16-bits in DDI_SLAVE_OFF add 2 for data[31:16]
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*
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* myushortvar = getreg16(TIVA_DDI_DIR + DDI_SLAVE_OFF + 2);
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*
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* - Read data[31:24] byte in DDI_SLAVE_OFF add 3 for data[31:24]
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*
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* myuchar = getreg9(TIVA_DDI_DIR + DDI_SLAVE_OFF + 3);
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*
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* Notes: In the above example:
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*
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* - Where TIVA_DDI_DIR is address of the of the Direct Access
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* instruction.
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* - DDI_SLAVE_OFF is the DDI Slave offset defined in the
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* cc13x2_cc25x2_<ddi_slave>.h header file (e.g.
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* cc13x2_cc25x2_osc_top.h for the OSCSC oscillator modules.
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*
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* Writes can use any of the "instruction macros".
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* The following examples do a "direct write" to DDI Slave register
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* DDI_SLAVE_OFF using different size operands:
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*
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* DIRECT WRITES
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* - Write 32-bits aligned
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*
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* putreg32(0x12345678, TIVA_DDI_DIR + DDI_SLAVE_OFF);
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*
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* - Write 16-bits aligned to high 16-bits then low 16-bits
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* Add 2 to get to high 16-bits.
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*
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* putreg16(0xabcd, TIVA_DDI_DIR + DDI_SLAVE_OFF + 2);
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* putreg16(0xef01, TIVA_DDI_DIR + DDI_SLAVE_OFF);
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*
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* - Write each byte at DDI_SLAVE_OFF, one at a time.
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* Add 1,2,or 3 to get to bytes 1,2, or 3.
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*
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF) = 0x33;
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF + 1) = 0x44;
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF + 2) = 0x55;
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* putreg8(TIVA_DDI_DIR + DDI_SLAVE_OFF + 3) = 0x66;
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*
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* SET/CLR
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*
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* The set and clear functions behave similarly to each other. Each
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* can be performed on an 8-, 16-, or 32-bit operand.
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* Examples follow:
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*
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* - Set all odd bits in a 32-bit words
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*
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* putreg32(0xaaaaaaaa, TIVA_DDI_SET + DDI_SLAVE_OFF);
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*
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* - Clear all bits in byte 2 (data[23:16]) using 32-bit operand
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*
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* putreg32(0x00ff0000, TIVA_DDI_CLR + DDI_SLAVE_OFF);
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*
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* - Set even bits in byte 2 (data[23:16]) using 8-bit operand
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*
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* putreg8(0x55, TIVA_DDI_CLR + DDI_SLAVE_OFF + 2);
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*
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* MASKED WRITES
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*
|
||||
* The mask writes are a bit different. They operate on nibbles,
|
||||
* bytes, and 16-bit elements. Two operands are required; a 'mask'
|
||||
* and 'data'; The operands are concatenated and written to the master.
|
||||
* e.g. the mask and data are combined as follows for a 16 bit masked
|
||||
* write: (mask << 16) | data; Examples follow:
|
||||
*
|
||||
* - Write 5555 to low 16-bits of DDI_SLAVE_OFF register
|
||||
* a long write is needed (32-bits).
|
||||
*
|
||||
* putreg32(0xffff5555, TIVA_DDI_MASK16B + DDI_SLAVE_OFF);
|
||||
*
|
||||
* - Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register
|
||||
* Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff!
|
||||
*
|
||||
* putreg32(0x01ff01aa, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 4);
|
||||
*
|
||||
* - Do an 8 bit masked write of 00 to low byte of register (data[7:0]).
|
||||
* a short write is needed (16-bits).
|
||||
*
|
||||
* putreg16(0xff00, TIVA_DDI_MASK16B + DDI_SLAVE_OFF);
|
||||
*
|
||||
* - Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]).
|
||||
* add 2 to get to byte 1.
|
||||
*
|
||||
* putreg16(0xff11, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 2);
|
||||
*
|
||||
* - Do an 8 bit masked write of 33 to high byte of register (data[31:24]).
|
||||
* add 6 to get to byte 3.
|
||||
*
|
||||
* putreg16(0xff33, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 6);
|
||||
*
|
||||
* - Do an 4 bit masked write (Nibble) of 7 to data[3:0]).
|
||||
* Byte write is needed.
|
||||
*
|
||||
* putreg8(0xf7, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + DDI_MASK16B_OFFSET);
|
||||
*
|
||||
* - Do an 4 bit masked write of 4 to data[7:4]).
|
||||
* Add 1 for next nibble
|
||||
*
|
||||
* putreg8(0xf4, TIVA_DDI_MASK16B + DDI_SLAVE_OFF + 1);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/tiva_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* DDI Register Offsets *****************************************************/
|
||||
|
||||
#define TIVA_DDI_DIR_OFFSET 0x0000 /* Offset for the direct access instruction */
|
||||
#define TIVA_DDI_SET_OFFSET 0x0080 /* Offset for 'Set' instruction */
|
||||
#define TIVA_DDI_CLR_OFFSET 0x0100 /* Offset for 'Clear' instruction */
|
||||
#define TIVA_DDI_MASK4B_OFFSET 0x0200 /* Offset for 4-bit masked access */
|
||||
#define TIVA_DDI_MASK8B_OFFSET 0x0300 /* Offset for 8-bit masked access */
|
||||
#define TIVA_DDI_MASK16B_OFFSET 0x0400 /* Offset for 16-bit masked access */
|
||||
|
||||
/* DDI Register Addresses ***************************************************/
|
||||
|
||||
#define TIVA_DDI_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET)
|
||||
#define TIVA_DDI_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET)
|
||||
#define TIVA_DDI_CLR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_CLR_OFFSET)
|
||||
#define TIVA_DDI_MASK4B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK4B_OFFSET)
|
||||
#define TIVA_DDI_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET)
|
||||
#define TIVA_DDI_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI_H */
|
||||
Loading…
Reference in New Issue
Block a user