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arch/arm/src/stm32f0l0g0/stm32g0_rcc.c: Fixes some problems found in build testing.

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This commit is contained in:
Mateusz Szafoni 2019-05-31 09:22:07 -06:00 committed by Gregory Nutt
parent 0ceac9a969
commit dffed7ab51
2 changed files with 3 additions and 7 deletions
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9
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
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@ -87,12 +87,9 @@ static inline void rcc_reset(void)
putreg32(RCC_PLLCFGR_RESET, STM32_RCC_PLLCFG);
#if 1
/* DBG clock enable */
regval |= RCC_APB1ENR_DBGEN;
#endif
regval = RCC_APB1ENR_DBGEN;
putreg32(regval, STM32_RCC_APB1ENR);
}
@ -517,7 +514,7 @@ static void stm32_stdclockconfig(void)
}
#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSI)
/* The PLL is using the HSI, or the HSI is the system clock. In either
* case, we need to enable HSI clocking.
@ -535,7 +532,7 @@ static void stm32_stdclockconfig(void)
#endif
#warning TODO: cofnigure flash latency
#warning TODO: configure flash latency
UNUSED(flash_1ws);
/* Set the HCLK source/divider */

1
configs/nucleo-g071rb/nsh/defconfig
View File

@ -22,7 +22,6 @@ CONFIG_DISABLE_POLL=y
CONFIG_DISABLE_POSIX_TIMERS=y
CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_EXPERIMENTAL=y
CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=8
CONFIG_MAX_WDOGPARMS=2