diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
index 1c671ab13c..b4c1c83bbc 100644
--- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
@@ -87,12 +87,9 @@ static inline void rcc_reset(void)
 
   putreg32(RCC_PLLCFGR_RESET, STM32_RCC_PLLCFG);
 
-#if 1
   /* DBG clock enable */
 
-  regval |= RCC_APB1ENR_DBGEN;
-#endif
-
+  regval = RCC_APB1ENR_DBGEN;
   putreg32(regval, STM32_RCC_APB1ENR);
 }
 
@@ -517,7 +514,7 @@ static void stm32_stdclockconfig(void)
     }
 
 #elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
-      ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
+      ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSI)
 
   /* The PLL is using the HSI, or the HSI is the system clock.  In either
    * case, we need to enable HSI clocking.
@@ -535,7 +532,7 @@ static void stm32_stdclockconfig(void)
 
 #endif
 
-#warning TODO: cofnigure flash latency
+#warning TODO: configure flash latency
   UNUSED(flash_1ws);
 
   /* Set the HCLK source/divider */
diff --git a/configs/nucleo-g071rb/nsh/defconfig b/configs/nucleo-g071rb/nsh/defconfig
index ea3f5afb48..377db0e679 100644
--- a/configs/nucleo-g071rb/nsh/defconfig
+++ b/configs/nucleo-g071rb/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_EXAMPLES_HELLO=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2