ARMv7-R: Remove some CONFIG_PAGING logic left over from ARMv7-A leverage
This commit is contained in:
Gregory Nutt
parent
e1b1f80237
commit
e0214f9d62
@ -58,23 +58,6 @@
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#include "sched/sched.h"
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#include "up_internal.h"
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#ifdef CONFIG_PAGING
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# include <nuttx/page.h>
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# include "arm.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -84,10 +67,6 @@
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*
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* Input parameters:
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* regs - The standard, ARM register save array.
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*
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* If CONFIG_PAGING is selected in the NuttX configuration file, then these
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* additional input values are expected:
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*
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* dfar - Fault address register.
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* dfsr - Fault status register.
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*
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@ -97,89 +76,6 @@
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
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{
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DFAR struct tcb_s *tcb = (DFAR struct tcb_s *)g_readytorun.head;
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uint32_t *savestate;
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/* Save the saved processor context in current_regs where it can be accessed
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* for register dumps and possibly context switching.
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*/
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savestate = (uint32_t *)current_regs;
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current_regs = regs;
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/* In the NuttX on-demand paging implementation, only the read-only, .text
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* section is paged. However, the ARM compiler generated PC-relative data
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* fetches from within the .text sections. Also, it is customary to locate
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* read-only data (.rodata) within the same section as .text so that it
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* does not require copying to RAM. Misses in either of these case should
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* cause a data abort.
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*
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* We are only interested in data aborts due to page translations faults.
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* Sections should already be in place and permissions should already be
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* be set correctly (to read-only) so any other data abort reason is a
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* fatal error.
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*/
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pglldbg("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
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if ((dfsr & FSR_MASK) != FSR_PAGE)
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{
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goto segfault;
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}
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/* Check the (virtual) address of data that caused the data abort. When
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* the exception occurred, this address was provided in the DFAR register.
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* (It has not yet been saved in the register context save area).
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*/
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pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
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if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
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{
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goto segfault;
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}
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/* Save the offending data address as the fault address in the TCB of
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* the currently task. This fault address is also used by the prefetch
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* abort handling; this will allow common paging logic for both
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* prefetch and data aborts.
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*/
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tcb->xcp.dfar = regs[REG_R15];
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/* Call pg_miss() to schedule the page fill. A consequences of this
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* call are:
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*
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* (1) The currently executing task will be blocked and saved on
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* on the g_waitingforfill task list.
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* (2) An interrupt-level context switch will occur so that when
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* this function returns, it will return to a different task,
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* most likely the page fill worker thread.
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* (3) The page fill worker task has been signalled and should
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* execute immediately when we return from this exception.
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*/
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pg_miss();
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/* Restore the previous value of current_regs. NULL would indicate that
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* we are no longer in an interrupt handler. It will be non-NULL if we
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* are returning from a nested interrupt.
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*/
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current_regs = savestate;
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return regs;
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segfault:
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lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
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regs[REG_PC], dfar, dfsr);
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PANIC();
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return regs; /* To keep the compiler happy */
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}
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#else /* CONFIG_PAGING */
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uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
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{
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/* Save the saved processor context in current_regs where it can be accessed
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@ -195,5 +91,3 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
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PANIC();
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return regs; /* To keep the compiler happy */
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}
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#endif /* CONFIG_PAGING */
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@ -54,9 +54,6 @@
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#include <debug.h>
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#include <nuttx/irq.h>
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#ifdef CONFIG_PAGING
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# include <nuttx/page.h>
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#endif
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#include "sched/sched.h"
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#include "up_internal.h"
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@ -87,75 +84,6 @@
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*
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****************************************************************************/
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#ifdef CONFIG_PAGING
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uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
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{
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uint32_t *savestate;
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/* Save the saved processor context in current_regs where it can be accessed
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* for register dumps and possibly context switching.
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*/
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savestate = (uint32_t *)current_regs;
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current_regs = regs;
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/* Get the (virtual) address of instruction that caused the prefetch abort.
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* When the exception occurred, this address was provided in the lr register
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* and this value was saved in the context save area as the PC at the
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* REG_R15 index.
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*
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* Check to see if this miss address is within the configured range of
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* virtual addresses.
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*/
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pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
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regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
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if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
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{
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/* Save the offending PC as the fault address in the TCB of the currently
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* executing task. This value is, of course, already known in regs[REG_R15],
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* but saving it in this location will allow common paging logic for both
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* prefetch and data aborts.
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*/
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FAR struct tcb_s *tcb = (FAR struct tcb_s *)g_readytorun.head;
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tcb->xcp.far = regs[REG_R15];
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/* Call pg_miss() to schedule the page fill. A consequences of this
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* call are:
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*
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* (1) The currently executing task will be blocked and saved on
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* on the g_waitingforfill task list.
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* (2) An interrupt-level context switch will occur so that when
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* this function returns, it will return to a different task,
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* most likely the page fill worker thread.
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* (3) The page fill worker task has been signalled and should
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* execute immediately when we return from this exception.
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*/
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pg_miss();
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/* Restore the previous value of current_regs. NULL would indicate that
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* we are no longer in an interrupt handler. It will be non-NULL if we
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* are returning from a nested interrupt.
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*/
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current_regs = savestate;
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}
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else
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{
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lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
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regs[REG_PC], ifar, ifsr);
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PANIC();
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}
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return regs;
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}
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#else /* CONFIG_PAGING */
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uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
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{
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/* Save the saved processor context in current_regs where it can be accessed
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@ -171,5 +99,3 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
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PANIC();
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return regs; /* To keep the compiler happy */
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}
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#endif /* CONFIG_PAGING */
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