Tiva: Updates to system control regiser definitions
This commit is contained in:
Gregory Nutt
parent
bb7809f346
commit
e0678813c1
@ -465,49 +465,308 @@
|
||||
/* System Control Registers (System Control Offset) */
|
||||
|
||||
/* Device Identification 0 */
|
||||
#define SYSCON_DID0_
|
||||
|
||||
#define SYSCON_DID0_MINOR_SHIFT 0 /* Bits 0-7: Minor Revision of the device */
|
||||
#define SYSCON_DID0_MINOR_MASK (0xff << SYSCON_DID0_MINOR_SHIFT)
|
||||
# define SYSCON_DID0_MIN_0 (0 << SYSCON_DID0_MINOR_SHIFT) /* Initial device or revision */
|
||||
# define SYSCON_DID0_MIN_1 (1 << SYSCON_DID0_MINOR_SHIFT) /* First metal layer change */
|
||||
# define SYSCON_DID0_MIN_2 (2 << SYSCON_DID0_MINOR_SHIFT) /* Second metal layer change */
|
||||
#define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 8-15: Major Revision of the device */
|
||||
#define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT)
|
||||
# define SYSCON_DID0_MAJ_REVA (0 << SYSCON_DID0_MAJOR_SHIFT) /* Revision A */
|
||||
# define SYSCON_DID0_MAJ_REVB (1 << SYSCON_DID0_MAJOR_SHIFT) /* Revision B */
|
||||
# define SYSCON_DID0_MAJ_REVC (2 << SYSCON_DID0_MAJOR_SHIFT) /* Revision C */
|
||||
#define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 16-23: Device Class */
|
||||
#define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT)
|
||||
# define SYSCON_DID0_CLASS_TM4C123 (5 << SYSCON_DID0_CLASS_SHIFT) /* Tiva TM4C123x and TM4E123x */
|
||||
# define SYSCON_DID0_CLASS_TM4C129 (10 << SYSCON_DID0_CLASS_SHIFT) /* Tiva TM4C129-class */
|
||||
#define SYSCON_DID0_VER_SHIFT 28 /* Bits 28-30: DID0 Version */
|
||||
#define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT)
|
||||
# define SYSCON_DID0_VER_1 (1 << SYSCON_DID0_VER_SHIFT) /* Second version of DID0 format */
|
||||
|
||||
/* Device Identification 1 */
|
||||
#define SYSCON_DID1_
|
||||
|
||||
#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */
|
||||
#define SYSCON_DID1_QUAL_MASK (3 << SYSCON_DID1_QUAL_SHIFT)
|
||||
# define SYSCON_DID1_QUAL_ES (0 << SYSCON_DID1_QUAL_SHIFT) /* Engineering Sample */
|
||||
# define SYSCON_DID1_QUAL_PP (1 << SYSCON_DID1_QUAL_SHIFT) /* Pilot Production */
|
||||
# define SYSCON_DID1_QUAL_FQ (2 << SYSCON_DID1_QUAL_SHIFT) /* Fully Qualified */
|
||||
#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */
|
||||
#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 3-4: Package Type */
|
||||
#define SYSCON_DID1_PKG_MASK (3 << SYSCON_DID1_PKG_SHIFT)
|
||||
# define SYSCON_DID1_PKG_QFP (1 << SYSCON_DID1_PKG_SHIFT) /* QFP package */
|
||||
# define SYSCON_DID1_PKG_BGA (2 << SYSCON_DID1_PKG_SHIFT) /* BGA package */
|
||||
#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 5-7: Temperature Range */
|
||||
#define SYSCON_DID1_TEMP_MASK (7 << SYSCON_DID1_TEMP_SHIFT)
|
||||
# define SYSCON_DID1_TEMP_C (0 << SYSCON_DID1_TEMP_SHIFT) /* Commercial temperature */
|
||||
# define SYSCON_DID1_TEMP_I (1 << SYSCON_DID1_TEMP_SHIFT) /* Industrial temperature */
|
||||
# define SYSCON_DID1_TEMP_E (2 << SYSCON_DID1_TEMP_SHIFT) /* Extended temperature */
|
||||
# define SYSCON_DID1_TEMP_IE (3 << SYSCON_DID1_TEMP_SHIFT) /* Industrial and extended */
|
||||
#define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 13-15: Package Pin Count */
|
||||
#define SYSCON_DID1_PINCOUNT_MASK (7 << SYSCON_DID1_PINCOUNT_SHIFT)
|
||||
# define SYSCON_DID1_PINCNT_100 (2 << SYSCON_DID1_PINCOUNT_SHIFT) /* 100-pin LQFP */
|
||||
# define SYSCON_DID1_PINCNT_64 (3 << SYSCON_DID1_PINCOUNT_SHIFT) /* 64-pin LQFP */
|
||||
# define SYSCON_DID1_PINCNT_144 (4 << SYSCON_DID1_PINCOUNT_SHIFT) /* 144-pin LQFP */
|
||||
# define SYSCON_DID1_PINCNT_157 (5 << SYSCON_DID1_PINCOUNT_SHIFT) /* 157-pin BGA */
|
||||
# define SYSCON_DID1_PINCNT_128 (6 << SYSCON_DID1_PINCOUNT_SHIFT) /* 128-pin TQFP */
|
||||
# define SYSCON_DID1_PINCNT_1212 (7 << SYSCON_DID1_PINCOUNT_SHIFT) /* 212-pin BGA */
|
||||
#define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 16-23: Part Number */
|
||||
#define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT)
|
||||
# define SYSCON_DID1_TM4C1294NCPDT (31 << SYSCON_DID1_PARTNO_SHIFT) /* TM4C1294NCPDT */
|
||||
# define SYSCON_DID1_TM4C129XNCZAD (50 << SYSCON_DID1_PARTNO_SHIFT) /* TM4C129XNCZAD */
|
||||
#define SYSCON_DID1_FAM_SHIFT 24 /* Bits 24-27: Family */
|
||||
#define SYSCON_DID1_FAM_MASK (15 << SYSCON_DID1_FAM_SHIFT)
|
||||
# define SYSCON_DID1_FAM_TIVA (0 << SYSCON_DID1_FAM_SHIFT) /* Tiva C family */
|
||||
#define SYSCON_DID1_VER_SHIFT 28 /* Bits 28-31: DID1 Version */
|
||||
#define SYSCON_DID1_VER_MASK (15 << SYSCON_DID1_VER_SHIFT)
|
||||
#define SYSCON_DID1_VER_1 (1 << SYSCON_DID1_VER_SHIFT) /* Second version of DID1 format */
|
||||
|
||||
/* Power-Temp Brown Out Control */
|
||||
#define SYSCON_PTBOCTL_
|
||||
|
||||
#define SYSCON_PTBOCTL_VDD_UBOR_SHIFT (0) /* Bits 0-1: VDD (VDDS) under BOR Event Action */
|
||||
#define SYSCON_PTBOCTL_VDD_UBOR_MASK (3 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT)
|
||||
# define SYSCON_PTBOCTL_VDD_UBOR_NONE (0 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* No Action */
|
||||
# define SYSCON_PTBOCTL_VDD_UBOR_SYSINT (1 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* System control interrupt */
|
||||
# define SYSCON_PTBOCTL_VDD_UBOR_NMI (2 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* NMI */
|
||||
# define SYSCON_PTBOCTL_VDD_UBOR_RST (3 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* Reset */
|
||||
#define SYSCON_PTBOCTL_VDDA_UBOR_SHIFT (8) /* Bits 8-9: VDDA under BOR Event Action */
|
||||
#define SYSCON_PTBOCTL_VDDA_UBOR_MASK (3 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT)
|
||||
# define SYSCON_PTBOCTL_VDDA_UBOR_NONE (0 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT) /* No Action */
|
||||
# define SYSCON_PTBOCTL_VDDA_UBOR_SYSINT (1 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT) /* System control interrupt */
|
||||
# define SYSCON_PTBOCTL_VDDA_UBOR_NMI (2 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT) /* NMI */
|
||||
# define SYSCON_PTBOCTL_VDDA_UBOR_RST (3 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT) /* Reset */
|
||||
|
||||
/* Raw Interrupt Status */
|
||||
#define SYSCON_RIS_
|
||||
|
||||
#define SYSCON_RIS_BOR1RIS (1 << 1) /* Bit 1: VDD under BOR1 Raw Interrupt Status */
|
||||
#define SYSCON_RIS_BORRIS (1 << 1) /* Bit 1: Brown-Out Reset Raw Interrupt Status */
|
||||
#define SYSCON_RIS_MOFRIS (1 << 3) /* Bit 3: Main Oscillator Failure Raw Interrupt Status */
|
||||
#define SYSCON_RIS_PLLLRIS (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Status */
|
||||
#define SYSCON_RIS_USBPLLLRIS (1 << 7) /* Bit 7: USB PLL Lock Raw Interrupt Status */
|
||||
#define SYSCON_RIS_MOSCPUPRIS (1 << 8) /* Bit 8: MOSC Power Up Raw Interrupt Status */
|
||||
#define SYSCON_RIS_VDDARIS (1 << 10) /* Bit 10: VDDA Power OK Event Raw Interrupt Status */
|
||||
#define SYSCON_RIS_BOR0RIS (1 << 11) /* Bit 11: VDD under BOR0 Raw Interrupt Status */
|
||||
|
||||
/* Interrupt Mask Control */
|
||||
#define SYSCON_IMC_
|
||||
|
||||
#define SYSCON_IMC_BOR1IM (1 << 1) /* Bit 1: VDD under BOR1 Interrupt Mask */
|
||||
#define SYSCON_IMC_BORIM (1 << 1) /* Bit 1: Brown-Out Reset Interrupt Mask */
|
||||
#define SYSCON_IMC_MOFIM (1 << 3) /* Bit 3: Main Oscillator Failure Interrupt Mask */
|
||||
#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */
|
||||
#define SYSCON_IMC_USBPLLLIM (1 << 7) /* Bit 7: USB PLL Lock Interrupt Mask */
|
||||
#define SYSCON_IMC_MOSCPUPIM (1 << 8) /* Bit 8: MOSC Power Up Interrupt Mask */
|
||||
#define SYSCON_IMC_VDDAIM (1 << 10) /* Bit 10: VDDA Power OK Interrupt Mask */
|
||||
#define SYSCON_IMC_BOR0IM (1 << 11) /* Bit 11: VDD under BOR0 Interrupt Mask */
|
||||
|
||||
/* Masked Interrupt Status and Clear */
|
||||
#define SYSCON_MISC_
|
||||
|
||||
#define SYSCON_MISC_BOR1MIS (1 << 1) /* Bit 1: VDD under BOR1 Masked Interrupt Status */
|
||||
#define SYSCON_MISC_BORMIS (1 << 1) /* Bit 1: BOR Masked Interrupt Status */
|
||||
#define SYSCON_MISC_MOFMIS (1 << 3) /* Bit 3: Main Oscillator Failure Masked Interrupt Status */
|
||||
#define SYSCON_MISC_PLLLMIS (1 << 6) /* Bit 6: PLL Lock Masked Interrupt Status */
|
||||
#define SYSCON_MISC_USBPLLLMIS (1 << 7) /* Bit 7: USB PLL Lock Masked Interrupt Status */
|
||||
#define SYSCON_MISC_MOSCPUPMIS (1 << 8) /* Bit 8: MOSC Power Up Masked Interrupt Status */
|
||||
#define SYSCON_MISC_VDDAMIS (1 << 10) /* Bit 10: VDDA Power OK Masked Interrupt Status */
|
||||
#define SYSCON_MISC_BOR0MIS (1 << 11) /* Bit 11: VDD under BOR0 Masked Interrupt Status */
|
||||
|
||||
/* Reset Cause */
|
||||
#define SYSCON_RESC_
|
||||
|
||||
#define SYSCON_RESC_EXT (1 << 0) /* Bit 0: External Reset */
|
||||
#define SYSCON_RESC_POR (1 << 1) /* Bit 1: Power-On Reset */
|
||||
#define SYSCON_RESC_BOR (1 << 2) /* Bit 2: Brown-Out Reset */
|
||||
#define SYSCON_RESC_WDT0 (1 << 3) /* Bit 3: Watchdog Timer 0 Reset */
|
||||
#define SYSCON_RESC_SW (1 << 4) /* Bit 4: Software Reset */
|
||||
#define SYSCON_RESC_WDT1 (1 << 5) /* Bit 5: Watchdog Timer 1 Reset */
|
||||
#define SYSCON_RESC_HIB (1 << 6) /* Bit 6: HIB Reset */
|
||||
#define SYSCON_RESC_HSSR (1 << 12) /* Bit 12: HSSR Reset */
|
||||
#define SYSCON_RESC_MOSCFAIL (1 << 16) /* Bit 16: MOSC Failure Reset */
|
||||
|
||||
/* Power-Temperature Cause */
|
||||
#define SYSCON_PWRTC_
|
||||
|
||||
#define SYSCON_PWRTC_VDD_UBOR (1 << 0) /* Bit 0: VDD Under BOR Status */
|
||||
#define SYSCON_PWRTC_VDDA_UBOR (1 << 4) /* Bit 4: VDDA Under BOR Status */
|
||||
|
||||
/* NMI Cause Register */
|
||||
#define SYSCON_NMIC_
|
||||
|
||||
#define SYSCON_NMIC_EXTERNAL (1 << 0) /* Bit 0: External Pin NMI */
|
||||
#define SYSCON_NMIC_POWER (1 << 2) /* Bit 2: Power/Brown Out Event NMI */
|
||||
#define SYSCON_NMIC_WDT0 (1 << 3) /* Bit 3: Watch Dog Timer (WDT) 0 NMI */
|
||||
#define SYSCON_NMIC_WDT1 (1 << 5) /* Bit 5: Watch Dog Timer (WDT) 1 NMI */
|
||||
#define SYSCON_NMIC_TAMPER (1 << 9) /* Bit 9: Tamper Event NMI */
|
||||
#define SYSCON_NMIC_MOSCFAIL (1 << 16) /* Bit 16: MOSC Failure NMI */
|
||||
|
||||
/* Main Oscillator Control */
|
||||
#define SYSCON_MOSCCTL_
|
||||
|
||||
#define SYSCON_MOSCCTL_CVAL (1 << 0) /* Bit 0: Clock Validation for MOSC */
|
||||
#define SYSCON_MOSCCTL_MOSCIM (1 << 1) /* Bit 1: MOSC Failure Action */
|
||||
#define SYSCON_MOSCCTL_NOXTAL (1 << 2) /* Bit 2: No Crystal Connected */
|
||||
#define SYSCON_MOSCCTL_PWRDN (1 << 3) /* Bit 3: Power Down */
|
||||
#define SYSCON_MOSCCTL_OSCRNG (1 << 4) /* Bit 4: Oscillator Range */
|
||||
|
||||
/* Run and Sleep Mode Configuration Register */
|
||||
#define SYSCON_RSCLKCFG_
|
||||
|
||||
#define SYSCON_RSCLKCFG_PSYSDIV_SHIFT (0) /* Bits 0-9:PLL System Clock Divisor */
|
||||
#define SYSCON_RSCLKCFG_PSYSDIV_MASK (0x3ff << SYSCON_RSCLKCFG_PSYSDIV_SHIFT)
|
||||
# define SYSCON_RSCLKCFG_PSYSDIV(n) ((uint32_t)(n) << SYSCON_RSCLKCFG_PSYSDIV_SHIFT)
|
||||
#define SYSCON_RSCLKCFG_OSYSDIV_SHIFT (10) /* Bits 10-19: Oscillator System Clock Divisor */
|
||||
#define SYSCON_RSCLKCFG_OSYSDIV_MASK (0x3ff << SYSCON_RSCLKCFG_OSYSDIV_SHIFT)
|
||||
# define SYSCON_RSCLKCFG_OSYSDIV(n) ((uint32_t)(n) << SYSCON_RSCLKCFG_OSYSDIV_SHIFT)
|
||||
#define SYSCON_RSCLKCFG_OSCSRC_SHIFT (20) /* Bits 20-23: Oscillator Source */
|
||||
#define SYSCON_RSCLKCFG_OSCSRC_MASK (15 << SYSCON_RSCLKCFG_OSCSRC_SHIFT)
|
||||
# define SYSCON_RSCLKCFG_OSCSRC_PIOSC (0 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* PIOSC is source */
|
||||
# define SYSCON_RSCLKCFG_OSCSRC_LFIOSC (1 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* LFIOSC is source */
|
||||
# define SYSCON_RSCLKCFG_OSCSRC_MOSC (3 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* MOSC is source */
|
||||
# define SYSCON_RSCLKCFG_OSCSRC_RTC (4 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* RTCOSC is source */
|
||||
#define SYSCON_RSCLKCFG_PLLSRC_SHIFT (24) /* Bits 24-27: PLL Source */
|
||||
#define SYSCON_RSCLKCFG_PLLSRC_MASK (15 << SYSCON_RSCLKCFG_PLLSRC_SHIFT)
|
||||
# define SYSCON_RSCLKCFG_PLLSRC_PIOSC (0 << SYSCON_RSCLKCFG_PLLSRC_SHIFT) /* PIOSC is clock source */
|
||||
# define SYSCON_RSCLKCFG_PLLSRC_MOSC (3 << SYSCON_RSCLKCFG_PLLSRC_SHIFT) /* MOSC is the clock source */
|
||||
#define SYSCON_RSCLKCFG_USEPLL (1 << 28) /* Bit 28: Use PLL */
|
||||
#define SYSCON_RSCLKCFG_ACG (1 << 29) /* Bit 29: Auto Clock Gating */
|
||||
#define SYSCON_RSCLKCFG_NEWFREQ (1 << 30) /* Bit 30: New PLLFREQ Accept */
|
||||
#define SYSCON_RSCLKCFG_MEMTIMU (1 << 31) /* Bit 31: Memory Timing Register Update */
|
||||
|
||||
/* Memory Timing Parameter Register 0 */
|
||||
#define SYSCON_MEMTIM0_
|
||||
|
||||
#define SYSCON_MEMTIM0_FWS_SHIFT (0) /* Bits 0-3: Flash Wait State */
|
||||
#define SYSCON_MEMTIM0_FWS_MASK (15 << SYSCON_MEMTIM0_FWS_SHIFT)
|
||||
# define SYSCON_MEMTIM0_FWS(n) ((uint32_t)(n) << SYSCON_MEMTIM0_FWS_SHIFT)
|
||||
#define SYSCON_MEMTIM0_FBCE (1 << 5) /* Bit 5: Flash Bank Clock Edge */
|
||||
#define SYSCON_MEMTIM0_FBCHT_SHIFT (6) /* Bits 6-9: Flash Bank Clock High Time */
|
||||
#define SYSCON_MEMTIM0_FBCHT_MASK (15 << SYSCON_MEMTIM0_FBCHT_SHIFT)
|
||||
# define SYSCON_MEMTIM0_FBCHT_0p5 (0 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 1/2 system clock period */
|
||||
# define SYSCON_MEMTIM0_FBCHT_1 (1 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 1 system clock period */
|
||||
# define SYSCON_MEMTIM0_FBCHT_1p5 (2 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 1.5 system clock periods */
|
||||
# define SYSCON_MEMTIM0_FBCHT_2 (3 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 2 system clock periods */
|
||||
# define SYSCON_MEMTIM0_FBCHT_2p5 (4 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 2.5 system clock periods */
|
||||
# define SYSCON_MEMTIM0_FBCHT_3 (5 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 3 system clock periods */
|
||||
# define SYSCON_MEMTIM0_FBCHT_3p5 (6 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 3.5 system clock periods */
|
||||
# define SYSCON_MEMTIM0_FBCHT_4 (7 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 4 system clock periods */
|
||||
# define SYSCON_MEMTIM0_FBCHT_4p5 (8 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 4.5 system clock periods */
|
||||
#define SYSCON_MEMTIM0_EWS_SHIFT (16) /* Bits 16-19: EEPROM Wait States */
|
||||
#define SYSCON_MEMTIM0_EWS_MASK (15 << SYSCON_MEMTIM0_EWS_SHIFT)
|
||||
# define SYSCON_MEMTIM0_EWS(n) ((uint32_t)(n) << SYSCON_MEMTIM0_EWS_SHIFT)
|
||||
#define SYSCON_MEMTIM0_EBCE (1 << 21) /* Bit 21: EEPROM Bank Clock Edge */
|
||||
#define SYSCON_MEMTIM0_EBCHT_SHIFT (22) /* Bits 22-25: EEPROM Clock High Time */
|
||||
#define SYSCON_MEMTIM0_EBCHT_MASK (15 << SYSCON_MEMTIM0_EBCHT_SHIFT)
|
||||
# define SYSCON_MEMTIM0_EBCHT_0p5 (0 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 1/2 system clock period */
|
||||
# define SYSCON_MEMTIM0_EBCHT_1 (1 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 1 system clock period */
|
||||
# define SYSCON_MEMTIM0_EBCHT_1p5 (2 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 1.5 system clock periods */
|
||||
# define SYSCON_MEMTIM0_EBCHT_2 (3 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 2 system clock periods */
|
||||
# define SYSCON_MEMTIM0_EBCHT_2p5 (4 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 2.5 system clock periods */
|
||||
# define SYSCON_MEMTIM0_EBCHT_3 (5 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 3 system clock periods */
|
||||
# define SYSCON_MEMTIM0_EBCHT_3p5 (6 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 3.5 system clock periods */
|
||||
# define SYSCON_MEMTIM0_EBCHT_4 (7 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 4 system clock periods */
|
||||
# define SYSCON_MEMTIM0_EBCHT_4p5 (8 << SYSCON_MEMTIM0_EBCHT_SHIFT) /* 4.5 system clock periods */
|
||||
|
||||
#define SYSCON_MEMTIM0_MB1 ((1 << 4) | (1 << 20)) /* Must be one */
|
||||
|
||||
/* Alternate Clock Configuration */
|
||||
#define SYSCON_ALTCLKCFG_
|
||||
|
||||
#define SYSCON_ALTCLKCFG_ALTCLK_SHIFT (0) /* Bits 0-3: Alternate Clock Source */
|
||||
#define SYSCON_ALTCLKCFG_ALTCLK_MASK (15 << SYSCON_ALTCLKCFG_ALTCLK_SHIFT)
|
||||
# define SYSCON_ALTCLKCFG_ALTCLK_PIOSC (0 << SYSCON_ALTCLKCFG_ALTCLK_SHIFT) /* PIOSC */
|
||||
# define SYSCON_ALTCLKCFG_ALTCLK_RTCOSC (3 << SYSCON_ALTCLKCFG_ALTCLK_SHIFT) /* RTCOSC */
|
||||
# define SYSCON_ALTCLKCFG_ALTCLK_LFIOSC (4 << SYSCON_ALTCLKCFG_ALTCLK_SHIFT) /* LFIOSC */
|
||||
|
||||
/* Deep Sleep Clock Configuration Register */
|
||||
#define SYSCON_DSCLKCFG_
|
||||
|
||||
#define SYSCON_DSCLKCFG_DSSYSDIV_SHIFT (0) /* Bits 0-9: Deep Sleep Clock Divisor */
|
||||
#define SYSCON_DSCLKCFG_DSSYSDIV_MASK (0x3ff << SYSCON_DSCLKCFG_DSSYSDIV_SHIFT)
|
||||
# define SYSCON_DSCLKCFG_DSSYSDIV(n) ((uint32_t)(n) << SYSCON_DSCLKCFG_DSSYSDIV_SHIFT)
|
||||
#define SYSCON_DSCLKCFG_DSOSCSRC_SHIFT (20) /* Bits 20-23: Deep Sleep Oscillator Source */
|
||||
#define SYSCON_DSCLKCFG_DSOSCSRC_MASK (15 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT)
|
||||
# define SYSCON_DSCLKCFG_DSOSCSRC_PIOSC (0 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* PIOSC */
|
||||
# define SYSCON_DSCLKCFG_DSOSCSRC_LFIOSC (2 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* LFIOSC */
|
||||
# define SYSCON_DSCLKCFG_DSOSCSRC_MOSC (3 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* MOSC */
|
||||
# define SYSCON_DSCLKCFG_DSOSCSRC_RTC (4 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* RTCOSC */
|
||||
#define SYSCON_DSCLKCFG_MOSCDPD (1 << 30) /* Bit 30: MOSC Disable Power Down */
|
||||
#define SYSCON_DSCLKCFG_PIOSCPD (1 << 31) /* Bit 31: PIOSC Power Down */
|
||||
|
||||
/* Divisor and Source Clock Configuration */
|
||||
#define SYSCON_DIVSCLK_
|
||||
|
||||
#define SYSCON_DIVSCLK_DIV_SHIFT (0) /* Bits 0-7: Divisor Value */
|
||||
#define SYSCON_DIVSCLK_DIV_MASK (0xff << SYSCON_DIVSCLK_DIV_SHIFT)
|
||||
# define SYSCON_DIVSCLK_DIV(n) ((uint32_t)(n) << SYSCON_DIVSCLK_DIV_SHIFT)
|
||||
#define SYSCON_DIVSCLK_SRC_SHIFT (16) /* Bits 16-17: Clock Source */
|
||||
#define SYSCON_DIVSCLK_SRC_MASK (3 << SYSCON_DIVSCLK_SRC_SHIFT)
|
||||
# define SYSCON_DIVSCLK_SRC_SYSCLK (0 << SYSCON_DIVSCLK_SRC_SHIFT) /* System Clock */
|
||||
# define SYSCON_DIVSCLK_SRC_PIOSC (1 << SYSCON_DIVSCLK_SRC_SHIFT) /* PIOSC */
|
||||
# define SYSCON_DIVSCLK_SRC_MOSC (2 << SYSCON_DIVSCLK_SRC_SHIFT) /* MOSC */
|
||||
#define SYSCON_DIVSCLK_EN (1 << 31) /* Bit31: DIVSCLK Enable */
|
||||
|
||||
/* System Properties */
|
||||
#define SYSCON_SYSPROP_
|
||||
|
||||
#define SYSCON_SYSPROP_FPU (1 << 0) /* Bit 0: FPU Present */
|
||||
#define SYSCON_SYSPROP_LDOSEQ (1 << 5) /* Bit 5: Automatic LDO Sequence Control Present */
|
||||
#define SYSCON_SYSPROP_FLASHLPM (1 << 8) /* Bit 8: Flash Memory Sleep/Deep-Sleep Low Power Mode Present */
|
||||
#define SYSCON_SYSPROP_SRAMLPM (1 << 10) /* Bit 10: SRAM Sleep/Deep-Sleep Low Power Mode Present */
|
||||
#define SYSCON_SYSPROP_SRAMSM (1 << 11) /* Bit 11: SRAM Sleep/Deep-Sleep Standby Mode Present */
|
||||
#define SYSCON_SYSPROP_PIOSCPDE (1 << 12) /* Bit 12: PIOSC Power Down Present */
|
||||
#define SYSCON_SYSPROP_TSPDE (1 << 16) /* Bit 16: Temp Sense Power Down Enable */
|
||||
#define SYSCON_SYSPROP_LDOSME (1 << 17) /* Bit 17: LDO Sleep Mode Enable */
|
||||
|
||||
/* Precision Internal Oscillator Calibration */
|
||||
#define SYSCON_PIOSCCAL_
|
||||
|
||||
#define SYSCON_PIOSCCAL_UT_SHIFT (0) /* Bits 0-6: User Trim Value */
|
||||
#define SYSCON_PIOSCCAL_UT_MASK (0x7f << SYSCON_PIOSCCAL_UT_SHIFT)
|
||||
# define SYSCON_PIOSCCAL_UT(n) ((uint32_t)(n) << SYSCON_PIOSCCAL_UT_SHIFT)
|
||||
#define SYSCON_PIOSCCAL_UPDATE (1 << 8) /* Bit 8: Update Trim */
|
||||
#define SYSCON_PIOSCCAL_CAL (1 << 9) /* Bit 9: Start Calibration */
|
||||
#define SYSCON_PIOSCCAL_UTEN (1 << 31) /* Bit 31: Use User Trim Value */
|
||||
|
||||
/* Precision Internal Oscillator Statistics */
|
||||
#define SYSCON_PIOSCSTAT_
|
||||
|
||||
#define SYSCON_PIOSCSTAT_CT_SHIFT (0) /* Bits 0-6: Calibration Trim Value */
|
||||
#define SYSCON_PIOSCSTAT_CT_MASK (0x7f << SYSCON_PIOSCSTAT_CT_SHIFT)
|
||||
# define SYSCON_PIOSCSTAT_CT(n) ((uint32_t)(n) << SYSCON_PIOSCSTAT_CT_SHIFT)
|
||||
#define SYSCON_PIOSCSTAT_RESULT_SHIFT (8) /* Bits 8-9: Calibration Result */
|
||||
#define SYSCON_PIOSCSTAT_RESULT_MASK (3 << SYSCON_PIOSCSTAT_RESULT_SHIFT)
|
||||
# define SYSCON_PIOSCSTAT_RESULT(n) ((uint32_t)(n) << SYSCON_PIOSCSTAT_RESULT_SHIFT)
|
||||
# define SYSCON_PIOSCSTAT_CRNONE (0 << SYSCON_PIOSCSTAT_RESULT_SHIFT)
|
||||
# define SYSCON_PIOSCSTAT_CRPASS (1 << SYSCON_PIOSCSTAT_RESULT_SHIFT)
|
||||
# define SYSCON_PIOSCSTAT_CRFAIL (2 << SYSCON_PIOSCSTAT_RESULT_SHIFT)
|
||||
#define SYSCON_PIOSCSTAT_DT_SHIFT (16) /* Bits 16-22: Default Trim Value */
|
||||
#define SYSCON_PIOSCSTAT_DT_MASK (0x7f << SYSCON_PIOSCSTAT_DT_SHIFT)
|
||||
# define SYSCON_PIOSCSTAT_DT(n) ((uint32_t)(n) << SYSCON_PIOSCSTAT_DT_SHIFT)
|
||||
|
||||
/* PLL Frequency 0 */
|
||||
#define SYSCON_PLLFREQ0_
|
||||
|
||||
#define SYSCON_PLLFREQ0_MINT_SHIFT (0) /* Bits 0-9: PLL M Integer Value */
|
||||
#define SYSCON_PLLFREQ0_MINT_MASK (0x3ff << SYSCON_PLLFREQ0_MINT_SHIFT)
|
||||
# define SYSCON_PLLFREQ0_MINT(n) ((uint32_t)(n) << SYSCON_PLLFREQ0_MINT_SHIFT)
|
||||
#define SYSCON_PLLFREQ0_MFRAC_SHIFT (10) /* Bits 10-19: PLL M Fractional Value */
|
||||
#define SYSCON_PLLFREQ0_MFRAC_MASK (0x3ff << SYSCON_PLLFREQ0_MFRAC_SHIFT)
|
||||
# define SYSCON_PLLFREQ0_MFRAC(n) ((uint32_t)(n) << SYSCON_PLLFREQ0_MFRAC_SHIFT)
|
||||
#define SYSCON_PLLFREQ0_PLLPWR (1 << 23) /* Bit 23: PLL Power */
|
||||
|
||||
/* PLL Frequency 1 */
|
||||
#define SYSCON_PLLFREQ1_
|
||||
|
||||
#define SYSCON_PLLFREQ1_N_SHIFT (0) /* Bits 0-4: PLL N Value */
|
||||
#define SYSCON_PLLFREQ1_N_MASK (31 << SYSCON_PLLFREQ1_N_SHIFT)
|
||||
# define SYSCON_PLLFREQ1_N(n) ((uint32_t)(n) << SYSCON_PLLFREQ1_N_SHIFT)
|
||||
#define SYSCON_PLLFREQ1_Q_SHIFT (8) /* Bits 8-12: PLL Q Value */
|
||||
#define SYSCON_PLLFREQ1_Q_MASK (31 << SYSCON_PLLFREQ1_Q_SHIFT)
|
||||
# define SYSCON_PLLFREQ1_Q(n) ((uint32_t)(n) << SYSCON_PLLFREQ1_Q_SHIFT)
|
||||
|
||||
/* PLL Status */
|
||||
#define SYSCON_PLLSTAT_
|
||||
|
||||
#define SYSCON_PLLSTAT_LOCK (1 << 0) /* Bit 0: PLL Lock */
|
||||
|
||||
/* Sleep Power Configuration */
|
||||
#define SYSCON_SLPPWRCFG_
|
||||
|
||||
#define SYSCON_SLPPWRCFG_SRAMPM_SHIFT (0) /* Bits 1-0: SRAM Power Modes */
|
||||
#define SYSCON_SLPPWRCFG_SRAMPM_MASK (3 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT)
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_LOWPWR (2 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */
|
||||
#define SYSCON_SLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */
|
||||
#define SYSCON_SLPPWRCFG_FLASHPM_MASK (3 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT)
|
||||
# define SYSCON_SLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */
|
||||
# define SYSCON_SLPPWRCFG_FLASHPM_LOWPWRR (2 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) /* Low Power Mode */
|
||||
#define SYSCON_SLPPWRCFG_TSPD (1 << 8) /* Bit 8: Temperature Sense Power Down */
|
||||
#define SYSCON_SLPPWRCFG_LDOSM (1 << 9) /* Bit 9: LDO Sleep Mode */
|
||||
|
||||
/* Deep-Sleep Power Configuration */
|
||||
#define SYSCON_DSLPPWRCFG_
|
||||
/* Non-Volatile Memory Information */
|
||||
|
||||
@ -386,7 +386,7 @@
|
||||
#define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */
|
||||
#define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT)
|
||||
#define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */
|
||||
#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */
|
||||
#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */
|
||||
#define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT)
|
||||
#define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */
|
||||
#define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT)
|
||||
@ -416,13 +416,13 @@
|
||||
|
||||
/* Interrupt Mask Control */
|
||||
|
||||
#define SYSCON_IMC_BORR1RIM (1 << 1) /* Bit 1: VDD under BOR1 Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_MOFRIM (1 << 3) /* Bit 3: Main Oscillator Failure Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_PLLLRIM (1 << 6) /* Bit 6: PLL Lock Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_USBPLLLRIM (1 << 7) /* Bit 7: USB PLL Lock Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_MOSCPUPRIM (1 << 8) /* Bit 8: MOSC Power Up Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_VDDARIM (1 << 10) /* Bit 10: VDDA Power OK Event Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_BOR0RIM (1 << 11) /* Bit 11: VDD under BOR0 Raw Interrupt Mask */
|
||||
#define SYSCON_IMC_BORR1IM (1 << 1) /* Bit 1: VDD under BOR1 Interrupt Mask */
|
||||
#define SYSCON_IMC_MOFIM (1 << 3) /* Bit 3: Main Oscillator Failure Interrupt Mask */
|
||||
#define SYSCON_IMC_PLLLIM (1 << 6) /* Bit 6: PLL Lock Interrupt Mask */
|
||||
#define SYSCON_IMC_USBPLLLIM (1 << 7) /* Bit 7: USB PLL Lock Interrupt Mask */
|
||||
#define SYSCON_IMC_MOSCPUPIM (1 << 8) /* Bit 8: MOSC Power Up Interrupt Mask */
|
||||
#define SYSCON_IMC_VDDAIM (1 << 10) /* Bit 10: VDDA Power OK Event Interrupt Mask */
|
||||
#define SYSCON_IMC_BOR0IM (1 << 11) /* Bit 11: VDD under BOR0 Interrupt Mask */
|
||||
|
||||
/* Masked Interrupt Status and Clear */
|
||||
|
||||
@ -609,7 +609,7 @@
|
||||
#define SYSCON_SLPPWRCFG_SRAMPM_MASK (3 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT)
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_LOWPWR (2 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */
|
||||
# define SYSCON_SLPPWRCFG_SRAMPM_LOWPWR (3 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */
|
||||
#define SYSCON_SLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */
|
||||
#define SYSCON_SLPPWRCFG_FLASHPM_MASK (3 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT)
|
||||
# define SYSCON_SLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */
|
||||
@ -621,7 +621,7 @@
|
||||
#define SYSCON_DSLPPWRCFG_SRAMPM_MASK (3 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT)
|
||||
# define SYSCON_DSLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */
|
||||
# define SYSCON_DSLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */
|
||||
# define SYSCON_DSLPPWRCFG_SRAMPM_LOWPWR (2 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */
|
||||
# define SYSCON_DSLPPWRCFG_SRAMPM_LOWPWR (3 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */
|
||||
#define SYSCON_DSLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */
|
||||
#define SYSCON_DSLPPWRCFG_FLASHPM_MASK (3 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT)
|
||||
# define SYSCON_DSLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user