Add LPC43 clock initialization logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4910 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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06d5e7224a
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e0b01efe74
@ -406,6 +406,21 @@ LPC4330-Xplorer Configuration Options
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CONFIG_ARCH_FPU - The LPC43xxx supports a floating point unit (FPU)
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CONFIG_ARCH_FPU=y
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CONFIG_BOOT_xxx - The startup code needs to know if the code is running
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from internal FLASH, external FLASH, SPIFI, or SRAM in order to
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initialize properly. Note that a boot device is not specified for
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cases where the code is copied into SRAM; those cases are all covered
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by CONFIG_BOOT_SRAM.
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CONFIG_BOOT_SRAM=y : Running from SRAM (0x1000:0000)
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CONFIG_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000)
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CONFIG_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000)
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CONFIG_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000)
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CONFIG_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000)
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CONFIG_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000)
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CONFIG_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000)
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CONFIG_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000)
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
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have LEDs
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@ -53,14 +53,40 @@
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****************************************************************************/
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/* Clocking ****************************************************************/
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/* NOTE: The following definitions require lpc43_syscon.h. It is not included here
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* because the including C file may not have that file in its include path.
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/* NOTE: The following definitions require lpc43_cgu.h. It is not included
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* here because the including C file may not have that file in its include
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* path.
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*
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* The Xplorer board has four crystals on board:
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*
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* Y1 - RTC 32.768 MHz oscillator input,
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* Y2 - 24.576 MHz input to the UDA 1380 audio codec,
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* Y3 - 12.000 MHz LPC43xx crystal oscillator input
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* Y4 - 50 MHz input for Ethernet
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
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#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */
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#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency (Y3) */
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#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency (Y1) */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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/* Integer and direct modes are supported:
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*
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* In integer mode:
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* Fclkin = BOARD_XTAL_FREQUENCY
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* Fclkout = Msel * FClkin / Nsel
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* Fcco = 2 * Psel * Nclkout
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* In direct mode:
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* Fclkin = BOARD_XTAL_FREQUENCY
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* Fclkout = Msel * FClkin / Nsel
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* Fcco = Fclkout
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*/
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#undef BOARD_PLL1_DIRECT /* Integer mode */
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#define BOARD_PLL_MSEL (6) /* Msel = 6 */
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#define BOARD_PLL_NSEL (1) /* Nsel = 1 */
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#define BOARD_PLL_PSEL (2) /* Psel = 2 */
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#define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */
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#define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * 72,000,000 */
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/* This is the clock setup we configure for:
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*
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@ -69,64 +95,7 @@
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* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
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*/
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#define LPC43_CCLK 80000000 /* 80Mhz*/
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/* Select the main oscillator as the frequency source. SYSCLK is then the frequency
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* of the main oscillator.
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*/
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#undef CONFIG_LPC43_MAINOSC
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#define CONFIG_LPC43_MAINOSC 1
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#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
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/* Select the main oscillator and CCLK divider. The output of the divider is CCLK.
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* The input to the divider (PLLCLK) will be determined by the PLL output.
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*/
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#define BOARD_CCLKCFG_DIVIDER 6
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#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
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/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK).
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*
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* Source clock: Main oscillator
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* PLL0 Multiplier value (M): 20
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* PLL0 Pre-divider value (N): 1
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*
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* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz
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*/
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#undef CONFIG_LPC43_PLL0
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#define CONFIG_LPC43_PLL0 1
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#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
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#define BOARD_PLL0CFG_MSEL 20
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#define BOARD_PLL0CFG_NSEL 1
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#define BOARD_PLL0CFG_VALUE \
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(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
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((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
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/* PLL1 -- Not used. */
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#undef CONFIG_LPC43_PLL1
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#define BOARD_PLL1CFG_MSEL 36
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#define BOARD_PLL1CFG_NSEL 1
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#define BOARD_PLL1CFG_VALUE \
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(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
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((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
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/* USB divider. This divider is used when PLL1 is not enabled to get the
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* USB clock from PLL0:
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*
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* USBCLK = PLL0CLK / 10 = 48MHz
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*/
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#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10
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/* FLASH Configuration */
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#undef CONFIG_LP17_FLASH
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#define CONFIG_LP17_FLASH 1
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#define BOARD_FLASHCFG_VALUE 0x0000303a
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#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY
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/* LED definitions *********************************************************/
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/* The LPC4330-Xplorer has 2 user-controllable LEDs labeled D2 an D3 in the
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@ -87,6 +87,26 @@ ifeq ($(CONFIG_LPC43_BUILDROOT),y)
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MAXOPTIMIZATION = -Os
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endif
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# Setup for the kind of memory that we are executing from
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ifeq ($(CONFIG_BOOT_SRAM),y)
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LDSCRIPT = ramconfig.ld
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endif
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ifeq ($(CONFIG_BOOT_SPIFI),y)
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LDSCRIPT = spiconfig.ld
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endif
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ifeq ($(CONFIG_BOOT_FLASHA),y)
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LDSCRIPT = flashaconfig.ld
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endif
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ifeq ($(CONFIG_BOOT_FLASHB),y)
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LDSCRIPT = flashaconfig.ld
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endif
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ifeq ($(CONFIG_BOOT_CS0FLASH),y)
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LDSCRIPT = cs0flash.ld
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endif
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# Setup for Windows vs Linux/Cygwin/OSX environments
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ifeq ($(WINTOOL),y)
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# Windows-native toolchains
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DIRLINK = $(TOPDIR)/tools/winlink.sh
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@ -94,14 +114,14 @@ ifeq ($(WINTOOL),y)
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MKDEP = $(TOPDIR)/tools/mknulldeps.sh
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ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
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ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
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ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ramconfig.ld}"
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ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
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MAXOPTIMIZATION = -O2
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else
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# Linux/Cygwin-native toolchain
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MKDEP = $(TOPDIR)/tools/mkdeps.sh
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ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
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ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
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ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ramconfig.ld
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ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
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endif
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CC = $(CROSSDEV)gcc
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@ -96,6 +96,31 @@ CONFIG_ARCH_CALIBRATION=n
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CONFIG_ARCH_DMA=n
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CONFIG_ARMV7M_CMNVECTOR=y
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#
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# CONFIG_BOOT_xxx - The startup code needs to know if the code is running
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# from internal FLASH, external FLASH, SPIFI, or SRAM in order to
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# initialize properly. Note that a boot device is not specified for
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# cases where the code is copied into SRAM; those cases are all covered
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# by CONFIG_BOOT_SRAM.
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#
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# CONFIG_BOOT_SRAM=y : Running from SRAM (0x1000:0000)
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# CONFIG_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000)
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# CONFIG_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000)
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# CONFIG_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000)
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# CONFIG_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000)
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# CONFIG_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000)
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# CONFIG_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000)
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# CONFIG_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000)
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#
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CONFIG_BOOT_SRAM=y
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CONFIG_BOOT_SPIFI=n
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CONFIG_BOOT_FLASHA=n
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CONFIG_BOOT_FLASHB=n
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CONFIG_BOOT_CS0FLASH=n
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CONFIG_BOOT_CS1FLASH=n
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CONFIG_BOOT_CS2FLASH=n
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CONFIG_BOOT_CS3FLASH=n
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#
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# Identify toolchain and linker options
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#
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@ -32,6 +32,27 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/*
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* Power-Up Reset Overview
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* -----------------------
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*
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* The ARM core starts executing code on reset with the program counter set
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* to 0x0000 0000. The LPC43xx contains a shadow pointer register that
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* allows areas of memory to be mapped to address 0x0000 0000. The default,
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* reset value of the shadow pointer is 0x1040 0000 so that on reset code in
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* the boot ROM is always executed first.
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*
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* The boot starts after reset is released. The IRC is selected as CPU clock
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* and the Cortex-M4 starts the boot loader. By default the JTAG access to the
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* chip is disabled at reset. The boot ROM determines the boot mode based on
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* the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part
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* boots from internal flash by default. Otherwse, the boot ROM copies the
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* image to internal SRAM at location 0x1000 0000, sets the ARM's shadow
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* pointer to 0x1000 0000, and jumps to that location.
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*
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* However, using JTAG the executable image can be also loaded directly into
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* and executed from SRAM.
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*/
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/* The LPC4330 on the LPC4330-Xplorer has the following memory resources:
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*
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@ -41,6 +62,7 @@
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* b. 72KB beginning at address 0x1008:0000 and
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* c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000,
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* 0x2000:8000 and 0x2000:C000.
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* 3. No internal FLASH
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*
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* Here we assume that:
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*
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@ -32,6 +32,27 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/*
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* Power-Up Reset Overview
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* -----------------------
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*
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* The ARM core starts executing code on reset with the program counter set
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* to 0x0000 0000. The LPC43xx contains a shadow pointer register that
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* allows areas of memory to be mapped to address 0x0000 0000. The default,
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* reset value of the shadow pointer is 0x1040 0000 so that on reset code in
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* the boot ROM is always executed first.
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*
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* The boot starts after reset is released. The IRC is selected as CPU clock
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* and the Cortex-M4 starts the boot loader. By default the JTAG access to the
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* chip is disabled at reset. The boot ROM determines the boot mode based on
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* the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part
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* boots from internal flash by default. Otherwse, the boot ROM copies the
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* image to internal SRAM at location 0x1000 0000, sets the ARM's shadow
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* pointer to 0x1000 0000, and jumps to that location.
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*
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* Of course, using JTAG the executable image can be also loaded directly
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* into and executed from SRAM.
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*/
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/* The LPC4330 on the LPC4330-Xplorer has the following memory resources:
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*
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@ -41,6 +62,7 @@
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* b. 72KB beginning at address 0x1008:0000 and
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* c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000,
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* 0x2000:8000 and 0x2000:C000.
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* 3. No internal FLASH
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*
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* Here we assume that:
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*
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