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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2946 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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21
TODO
21
TODO
@ -1,5 +1,5 @@
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NuttX TODO List (Last updated September 6, 2010)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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NuttX TODO List (Last updated September 13, 2010)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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(5) Task/Scheduler (sched/)
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(1) On-demand paging (sched/)
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@ -26,6 +26,7 @@ NuttX TODO List (Last updated September 6, 2010)
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(2) ARM/i.MX (arch/arm/src/imx/)
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(4) ARM/LPC17xx (arch/arm/src/lpc17xx/)
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(7) ARM/LPC214x (arch/arm/src/lpc214x/)
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(1) ARM/LPC313x (arch/arm/src/lpc313x/)
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(3) ARM/STR71x (arch/arm/src/str71x/)
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(4) ARM/LM3S6918 (arch/arm/src/lm3s/)
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(5) ARM/STM32 (arch/arm/src/stm32/)
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@ -789,6 +790,22 @@ o ARM/LPC214x (arch/arm/src/lpc214x/)
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Status: Open
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Priority: Medium
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o ARM/LPC313x (arch/arm/src/lpc313x/)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Description: arch/arm/src/lpc313x/lpc313x_spi.c contains logic that is specific to the
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Embedded Artist's ea3131 board. We need to abstract the assignmen of SPI
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chip selects and logic SPI functions (like SPIDEV_FLASH). My thoughts are:
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- Remove lpc313x_spiselect and lpc313x_spistatus from lpc313x_internal.h
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- Remove configs/ea3131/src/up_spi.c
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- Add configurations CONFIG_LPC3131x_CSOUT1DEV, CONFIG_LPC3131x_CSOUT2DEV,
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and CONFIG_LPC3131x_CSOUT3DEV that maps the lpc313x SPI chip selects to
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SPIDEV_* values.
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- Change arch/arm/src/lpc313x/lpc313x_spi.c to use those configuration
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settings.
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Status: Open
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Priority: High if you want to use SPI on any board other than the ea3131.
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o ARM/STR71x (arch/arm/src/str71x/)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -69,6 +69,17 @@
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* CONFIG_AT45DB_PREWAIT enables higher performance write logic: We leave the chip
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* busy after write and erase operations. This improves write and erase performance
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* because we do not have to wait as long between transactions (other processing can
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* occur while the chip is busy) but means that the chip must stay powered:
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*/
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#if defined(CONFIG_AT45DB_PWRSAVE) && defined(CONFIG_AT45DB_PREWAIT)
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# error "Both CONFIG_AT45DB_PWRSAVE and CONFIG_AT45DB_PREWAIT are defined"
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#endif
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/* If the user has provided no frequency, use 1MHz */
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#ifndef CONFIG_AT45DB_FREQUENCY
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# define CONFIG_AT45DB_FREQUENCY 1000000
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@ -460,14 +471,14 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
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fvdbg("sector: %08lx\n", (long)sector);
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/* If we not trying to conserve power, then we implement some higher performance
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* logic: We leave the chip busy after write and erase operations. This improves
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* performance because we do not have to wait as long being transactions (other
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* processing can occur while the chip is busy) but means that the chip must stay
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* powered.
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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*/
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#ifndef CONFIG_AT45DB_PWRSAVE
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#ifdef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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@ -491,11 +502,11 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
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SPI_SNDBLOCK(priv->spi, erasecmd, 4);
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SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
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/* Wait for any erase to complete if we are not trying to conserve power. (see
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* comments above).
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/* Wait for any erase to complete if we are not trying to improve write
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* performance. (see comments above).
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*/
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#ifdef CONFIG_AT45DB_PWRSAVE
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#ifndef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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fvdbg("Erased\n");
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@ -509,14 +520,14 @@ static inline int at32db_chiperase(struct at45db_dev_s *priv)
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{
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fvdbg("priv: %p\n", priv);
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/* If we not trying to conserve power, then we implement some higher performance
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* logic: We leave the chip busy after write and erase operations. This improves
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* performance because we do not have to wait as long being transactions (other
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* processing can occur while the chip is busy) but means that the chip must stay
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* powered.
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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*/
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#ifndef CONFIG_AT45DB_PWRSAVE
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#ifdef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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@ -532,11 +543,11 @@ static inline int at32db_chiperase(struct at45db_dev_s *priv)
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SPI_SNDBLOCK(priv->spi, g_chiperase, CHIP_ERASE_SIZE);
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SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
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/* Wait for any erase to complete if we are not trying to conserve power. (see
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* comments above).
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/* Wait for any erase to complete if we are not trying to improve write
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* performance. (see comments above).
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*/
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#ifdef CONFIG_AT45DB_PWRSAVE
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#ifndef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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return OK;
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@ -561,14 +572,14 @@ static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *
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wrcmd[2] = (offset >> 8) & 0xff; /* 24-bit address middle byte */
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wrcmd[3] = offset & 0xff; /* 24-bit address LS byte */
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/* If we not trying to conserve power, then we implement some higher performance
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* logic: We leave the chip busy after write and erase operations. This improves
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* performance because we do not have to wait as long being transactions (other
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* processing can occur while the chip is busy) but means that the chip must stay
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* powered.
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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*/
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#ifndef CONFIG_AT45DB_PWRSAVE
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#ifdef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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@ -577,11 +588,11 @@ static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *
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SPI_SNDBLOCK(priv->spi, buffer, 1 << priv->pageshift);
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SPI_SELECT(priv->spi, SPIDEV_FLASH, false);
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/* Wait for any erase to complete if we are not trying to conserve power. (see
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* comments above).
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/* Wait for any erase to complete if we are not trying to improve write
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* performance. (see comments above).
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*/
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#ifdef CONFIG_AT45DB_PWRSAVE
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#ifndef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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fvdbg("Written\n");
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@ -699,14 +710,14 @@ static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbyte
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at45db_lock(priv);
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/* If we not trying to conserve power, then we implement some higher performance
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* logic: We leave the chip busy after write and erase operations. This improves
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* performance because we do not have to wait as long being transactions (other
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* processing can occur while the chip is busy) but means that the chip must stay
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* powered and that we have to add waits at all entry points.
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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*/
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#ifndef CONFIG_AT45DB_PWRSAVE
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#ifdef CONFIG_AT45DB_PREWAIT
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at45db_waitbusy(priv);
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#endif
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