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For all SAM Ethernet, need to enable management interface before reading PHY regisers in IOCTL

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This commit is contained in:
Gregory Nutt 2014-08-17 11:09:54 -06:00
parent 2edcca009c
commit e0ef5a08bc
4 changed files with 99 additions and 0 deletions
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26
arch/arm/src/sam34/sam_emac.c
View File

@ -1826,14 +1826,40 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
case SIOCGMIIREG: /* Get register from MII PHY */ case SIOCGMIIREG: /* Get register from MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
/* Read from the requested register */
ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out); ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
/* Disable management port (probably) */
sam_putreg(priv, SAM_EMAC_NCR, regval);
} }
break; break;
case SIOCSMIIREG: /* Set register in MII PHY */ case SIOCSMIIREG: /* Set register in MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
/* Write to the requested register */
ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in); ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
/* Disable management port (probably) */
sam_putreg(priv, SAM_EMAC_NCR, regval);
} }
break; break;

26
arch/arm/src/sama5/sam_emaca.c
View File

@ -1867,14 +1867,40 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
case SIOCGMIIREG: /* Get register from MII PHY */ case SIOCGMIIREG: /* Get register from MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
/* Read from the requested register */
ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out); ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
/* Disable management port (probably) */
sam_putreg(priv, SAM_EMAC_NCR, regval);
} }
break; break;
case SIOCSMIIREG: /* Set register in MII PHY */ case SIOCSMIIREG: /* Set register in MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR);
sam_putreg(priv, SAM_EMAC_NCR, regval | EMAC_NCR_MPE);
/* Write to the requested register */
ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in); ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
/* Disable management port (probably) */
sam_putreg(priv, SAM_EMAC_NCR, regval);
} }
break; break;

26
arch/arm/src/sama5/sam_emacb.c
View File

@ -2242,14 +2242,40 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
case SIOCGMIIREG: /* Get register from MII PHY */ case SIOCGMIIREG: /* Get register from MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
/* Read from the requested register */
ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out); ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
/* Disable management port (probably) */
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
} }
break; break;
case SIOCSMIIREG: /* Set register in MII PHY */ case SIOCSMIIREG: /* Set register in MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
uint32_t regval;
/* Enable management port */
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval | EMAC_NCR_MPE);
/* Write to the requested register */
ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in); ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
/* Disable management port (probably) */
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);
} }
break; break;

21
arch/arm/src/sama5/sam_gmac.c
View File

@ -1822,14 +1822,35 @@ static int sam_ioctl(struct net_driver_s *dev, int cmd, long arg)
case SIOCGMIIREG: /* Get register from MII PHY */ case SIOCGMIIREG: /* Get register from MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
/* Enable the management port */
sam_enablemdio(priv);
/* Read from the requested register */
ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out); ret = sam_phyread(priv, req->phy_id, req->reg_num, &req->val_out);
/* Disable the management port */
sam_disablemdio(priv);
} }
break; break;
case SIOCSMIIREG: /* Set register in MII PHY */ case SIOCSMIIREG: /* Set register in MII PHY */
{ {
struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg);
/* Enable the management port */
sam_enablemdio(priv);
/* Write to the requested register */
ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in); ret = sam_phywrite(priv, req->phy_id, req->reg_num, req->val_in);
/* Disable the management port */
sam_disablemdio(priv);
} }
break; break;