stm32wb: add i2c driver
This commit is contained in:
Sergey Nikitenko
Xiang Xiao
parent
5e42bd97cd
commit
e0f99d93ac
@ -551,6 +551,19 @@ config STM32WB_LPUART1
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select ARCH_HAVE_LPUART1
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select STM32WB_USART
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config STM32WB_I2C1
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bool "I2C1"
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default n
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select I2C
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select STM32WB_I2C
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config STM32WB_I2C3
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bool "I2C3"
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default n
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depends on STM32WB_HAVE_I2C3
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select I2C
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select STM32WB_I2C
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comment "APB2 Peripherals"
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config STM32WB_SYSCFG
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@ -29,10 +29,10 @@ include armv7-m/Make.defs
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CHIP_CSRCS = stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c
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CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c
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CHIP_CSRCS += stm32wb_serial.c stm32wb_start.c stm32wb_waste.c stm32wb_uid.c
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CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c stm32wb_waste.c
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CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c
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CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c
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CHIP_CSRCS += stm32wb_flash.c
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CHIP_CSRCS += stm32wb_flash.c stm32wb_uid.c
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += stm32wb_idle.c
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220
arch/arm/src/stm32wb/hardware/stm32wb_i2c.h
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220
arch/arm/src/stm32wb/hardware/stm32wb_i2c.h
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@ -0,0 +1,220 @@
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/****************************************************************************
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* arch/arm/src/stm32wb/hardware/stm32wb_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H
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#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */
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#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */
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#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
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#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
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#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */
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#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */
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#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */
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#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */
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#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */
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#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */
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#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */
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/* Register Addresses *******************************************************/
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#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET)
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#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET)
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#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET)
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#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET)
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#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET)
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#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET)
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#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET)
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#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET)
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#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET)
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#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET)
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#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET)
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#ifdef CONFIG_STM32WB_HAVE_I2C3
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# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET)
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# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET)
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# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET)
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# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET)
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# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET)
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# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET)
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# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET)
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# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET)
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# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET)
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# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET)
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# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET)
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#endif
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/* Register Bitfield Definitions ********************************************/
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/* Control register 1 */
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#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
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#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
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#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
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#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
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#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
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#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
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#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
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#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
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#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
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#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
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# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
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#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
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#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
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#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
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#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
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#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
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#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
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#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
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#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
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#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
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#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
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#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
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/* Control register 2 */
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#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
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#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
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#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
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#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
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#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
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#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
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#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
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#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
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#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
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#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
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#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
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#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
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#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
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#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
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#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
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/* Own address register 1 */
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#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
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#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
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#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
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#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
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/* Own address register 2 */
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#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
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#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
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#define I2C_OAR2_OA2MSK_MASK (0x7 << I2C_OAR2_OA2MSK_SHIFT)
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# define I2C_OAR2_OA2MSK_NONE (0x0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
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# define I2C_OAR2_OA2MSK_2_7 (0x1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
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# define I2C_OAR2_OA2MSK_3_7 (0x2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
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# define I2C_OAR2_OA2MSK_4_7 (0x3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
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# define I2C_OAR2_OA2MSK_5_7 (0x4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
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# define I2C_OAR2_OA2MSK_6_7 (0x5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
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# define I2C_OAR2_OA2MSK_7 (0x6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
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# define I2C_OAR2_OA2MSK_ALL (0x7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
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#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
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/* Timing register */
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#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
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#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
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# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
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#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
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#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
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#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT)
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# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
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#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
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#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT)
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# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
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#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
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#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
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# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
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/* Timeout register */
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#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
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#define I2C_TIMEOUTR_A_MASK (0xfff << I2C_TIMEOUTR_A_SHIFT)
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# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
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#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
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#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
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#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
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#define I2C_TIMEOUTR_B_MASK (0xfff << I2C_TIMEOUTR_B_SHIFT)
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# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
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#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
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/* Interrupt and Status register and interrupt clear register */
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/* Common interrupt bits */
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#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
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#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
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#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
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#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
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#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
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#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
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#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
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#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
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#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
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/* Fields unique to the Interrupt and Status register */
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#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
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#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
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#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
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#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
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#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
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#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
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#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
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#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
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#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
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#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
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#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
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| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
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/* Packet error checking register */
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#define I2C_PECR_MASK (0xff)
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/* Receive data register */
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#define I2C_RXDR_MASK (0xff)
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/* Transmit data register */
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#define I2C_TXDR_MASK (0xff)
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#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H */
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2652
arch/arm/src/stm32wb/stm32wb_i2c.c
Normal file
2652
arch/arm/src/stm32wb/stm32wb_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
89
arch/arm/src/stm32wb/stm32wb_i2c.h
Normal file
89
arch/arm/src/stm32wb/stm32wb_i2c.h
Normal file
@ -0,0 +1,89 @@
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/****************************************************************************
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* arch/arm/src/stm32wb/stm32wb_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H
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#define __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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|
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#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32wb_i2c.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
|
||||
* seconds per byte value must be provided as well.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32WB_I2C_DYNTIMEO
|
||||
# if CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE < 1
|
||||
# warning "Ignoring CONFIG_STM32WB_I2C_DYNTIMEO because of CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE"
|
||||
# undef CONFIG_STM32WB_I2C_DYNTIMEO
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32wb_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected I2C port. And return a unique instance of struct
|
||||
* struct i2c_master_s. This function may be called to obtain multiple
|
||||
* instances of the interface, each of which may be set up with a
|
||||
* different frequency and slave address.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple I2C interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2C device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct i2c_master_s *stm32wb_i2cbus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32wb_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* De-initialize the selected I2C port, and power down the device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device structure as returned by the stm32wb_i2cbus_initialize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR when internal reference count mismatch or dev
|
||||
* points to invalid hardware device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H */
|
||||
Loading…
Reference in New Issue
Block a user